[J-u-boot.git] / include / configs / sama5d3xek.h

/*
 * Configuation settings for the SAMA5D3xEK board.
 *
 * Copyright (C) 2012 - 2013 Atmel
 *
 * based on at91sam9m10g45ek.h by:
 * Stelian Pop <[email protected]>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * If has No NOR flash, please put the definition: CONFIG_SYS_NO_FLASH
 * before the common header.
 */
#include "at91-sama5_common.h"

#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

/* serial console */
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
#define	CONFIG_USART_ID			ATMEL_ID_DBGU

/*
 * This needs to be defined for the OHCI code to work but it is defined as
 * ATMEL_ID_UHPHS in the CPU specific header files.
 */
#define ATMEL_ID_UHP			ATMEL_ID_UHPHS

/*
 * Specify the clock enable bit in the PMC_SCER register.
 */
#define ATMEL_PMC_UHP			AT91SAM926x_PMC_UHP

/* LCD */
#define LCD_BPP				LCD_COLOR16
#define LCD_OUTPUT_BPP                  24
#define CONFIG_LCD_LOGO
#define CONFIG_LCD_INFO
#define CONFIG_LCD_INFO_BELOW_LOGO
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_ATMEL_HLCD
#define CONFIG_ATMEL_LCD_RGB565
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* board specific (not enough SRAM) */
#define CONFIG_SAMA5D3_LCD_BASE		0x23E00000

/* NOR flash */
#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_BASE		0x10000000
#define CONFIG_SYS_MAX_FLASH_SECT	131
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#endif

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
#define CONFIG_SYS_SDRAM_SIZE		0x20000000

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR		0x310000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif

/* SerialFlash */

#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
#define CONFIG_SF_DEFAULT_SPEED		30000000
#endif

/* NAND flash */
#define CONFIG_CMD_NAND

#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP		4
#define CONFIG_PMECC_SECTOR_SIZE	512
#define CONFIG_CMD_NAND_TRIMFFS
#endif

/* Ethernet Hardware */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_MACB_SEARCH_PHY
#define CONFIG_RGMII
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021

/* MMC */

#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI			ATMEL_BASE_MCI0
#endif

/* USB */

#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"sama5d3"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
#define CONFIG_DOS_PARTITION
#endif

/* USB device */
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D3xEK"

#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
#define CONFIG_FAT_WRITE
#endif

#define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */

#ifdef CONFIG_SYS_USE_SERIALFLASH
/* override the bootcmd, bootargs and other configuration for spi flash env*/
#elif CONFIG_SYS_USE_NANDFLASH
/* override the bootcmd, bootargs and other configuration nandflash env */
#elif CONFIG_SYS_USE_MMC
/* override the bootcmd, bootargs and other configuration for sd/mmc env */
#else
#define CONFIG_ENV_IS_NOWHERE
#endif

/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x300000
#define CONFIG_SPL_MAX_SIZE		0x10000
#define CONFIG_SPL_BSS_START_ADDR	0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000

#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN		(512 << 10)

#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT		arch/arm/mach-at91/armv7/u-boot-spl.lds
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"

#elif CONFIG_SYS_USE_NANDFLASH
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER

#elif CONFIG_SYS_USE_SERIALFLASH
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000

#endif

#endif
Commit	Line	Data
3225f34e BS	1	/*
	2	* Configuation settings for the SAMA5D3xEK board.
	3	*
	4	* Copyright (C) 2012 - 2013 Atmel
	5	*
	6	* based on at91sam9m10g45ek.h by:
	7	* Stelian Pop <[email protected]>
	8	* Lead Tech Design <www.leadtechdesign.com>
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
3225f34e BS	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
b2d387bc WJ	16	/*
	17	* If has No NOR flash, please put the definition: CONFIG_SYS_NO_FLASH
	18	* before the common header.
	19	*/
	20	#include "at91-sama5_common.h"
3225f34e	21
89a3658a WJ	22	#define CONFIG_BOARD_LATE_INIT
	23	#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	24
3225f34e BS	25	/* serial console */
	26	#define CONFIG_ATMEL_USART
	27	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
	28	#define CONFIG_USART_ID ATMEL_ID_DBGU
	29
	30	/*
	31	* This needs to be defined for the OHCI code to work but it is defined as
	32	* ATMEL_ID_UHPHS in the CPU specific header files.
	33	*/
	34	#define ATMEL_ID_UHP ATMEL_ID_UHPHS
	35
	36	/*
	37	* Specify the clock enable bit in the PMC_SCER register.
	38	*/
	39	#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
	40
	41	/* LCD */
3225f34e BS	42	#define LCD_BPP LCD_COLOR16
	43	#define LCD_OUTPUT_BPP 24
	44	#define CONFIG_LCD_LOGO
3225f34e BS	45	#define CONFIG_LCD_INFO
	46	#define CONFIG_LCD_INFO_BELOW_LOGO
	47	#define CONFIG_SYS_WHITE_ON_BLACK
	48	#define CONFIG_ATMEL_HLCD
	49	#define CONFIG_ATMEL_LCD_RGB565
	50	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	51
	52	/* board specific (not enough SRAM) */
	53	#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
	54
d6b79434	55	/* NOR flash */
b2d387bc	56	#ifndef CONFIG_SYS_NO_FLASH
d6b79434 BS	57	#define CONFIG_FLASH_CFI_DRIVER
	58	#define CONFIG_SYS_FLASH_CFI
	59	#define CONFIG_SYS_FLASH_PROTECTION
	60	#define CONFIG_SYS_FLASH_BASE 0x10000000
	61	#define CONFIG_SYS_MAX_FLASH_SECT 131
	62	#define CONFIG_SYS_MAX_FLASH_BANKS 1
d6b79434	63	#endif
3225f34e	64
3225f34e BS	65	/* SDRAM */
	66	#define CONFIG_NR_DRAM_BANKS 1
	67	#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
	68	#define CONFIG_SYS_SDRAM_SIZE 0x20000000
	69
c5e8885a BS	70	#ifdef CONFIG_SPL_BUILD
	71	#define CONFIG_SYS_INIT_SP_ADDR 0x310000
	72	#else
3225f34e BS	73	#define CONFIG_SYS_INIT_SP_ADDR \
3225f34e BS	74	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
c5e8885a	75	#endif
3225f34e BS	76
3225f34e BS	77	/* SerialFlash */
3225f34e BS	78
	79	#ifdef CONFIG_CMD_SF
	80	#define CONFIG_ATMEL_SPI
3225f34e BS	81	#define CONFIG_SF_DEFAULT_SPEED 30000000
	82	#endif
	83
	84	/* NAND flash */
	85	#define CONFIG_CMD_NAND
	86
	87	#ifdef CONFIG_CMD_NAND
3225f34e BS	88	#define CONFIG_NAND_ATMEL
	89	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	90	#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
	91	/* our ALE is AD21 */
	92	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	93	/* our CLE is AD22 */
	94	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
	95	#define CONFIG_SYS_NAND_ONFI_DETECTION
	96	/* PMECC & PMERRLOC */
	97	#define CONFIG_ATMEL_NAND_HWECC
	98	#define CONFIG_ATMEL_NAND_HW_PMECC
	99	#define CONFIG_PMECC_CAP 4
	100	#define CONFIG_PMECC_SECTOR_SIZE 512
3225f34e BS	101	#define CONFIG_CMD_NAND_TRIMFFS
	102	#endif
	103
	104	/* Ethernet Hardware */
	105	#define CONFIG_MACB
	106	#define CONFIG_RMII
3225f34e BS	107	#define CONFIG_NET_RETRY_COUNT 20
3225f34e BS	108	#define CONFIG_MACB_SEARCH_PHY
e08d6f3a	109	#define CONFIG_RGMII
e08d6f3a BS	110	#define CONFIG_PHYLIB
	111	#define CONFIG_PHY_MICREL
	112	#define CONFIG_PHY_MICREL_KSZ9021
3225f34e BS	113
3225f34e BS	114	/* MMC */
3225f34e BS	115
	116	#ifdef CONFIG_CMD_MMC
	117	#define CONFIG_MMC
	118	#define CONFIG_GENERIC_MMC
	119	#define CONFIG_GENERIC_ATMEL_MCI
	120	#define ATMEL_BASE_MMCI ATMEL_BASE_MCI0
	121	#endif
	122
	123	/* USB */
3225f34e BS	124
	125	#ifdef CONFIG_CMD_USB
	126	#define CONFIG_USB_ATMEL
dcd2f1a0	127	#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
3225f34e BS	128	#define CONFIG_USB_OHCI_NEW
	129	#define CONFIG_SYS_USB_OHCI_CPU_INIT
	130	#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
	131	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
	132	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
	133	#define CONFIG_DOS_PARTITION
3225f34e BS	134	#endif
3225f34e BS	135
3668ce3c	136	/* USB device */
3668ce3c BS	137	#define CONFIG_USB_ETHER
	138	#define CONFIG_USB_ETH_RNDIS
	139	#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK"
	140
3225f34e	141	#if defined(CONFIG_CMD_USB) \|\| defined(CONFIG_CMD_MMC)
a248558a	142	#define CONFIG_FAT_WRITE
3225f34e BS	143	#endif
	144
	145	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
	146
	147	#ifdef CONFIG_SYS_USE_SERIALFLASH
7a53b954	148	/* override the bootcmd, bootargs and other configuration for spi flash env*/
3225f34e	149	#elif CONFIG_SYS_USE_NANDFLASH
dc018fef	150	/* override the bootcmd, bootargs and other configuration nandflash env */
3225f34e	151	#elif CONFIG_SYS_USE_MMC
372ca03f	152	/* override the bootcmd, bootargs and other configuration for sd/mmc env */
3225f34e	153	#else
a4c79b3a	154	#define CONFIG_ENV_IS_NOWHERE
3225f34e BS	155	#endif
3225f34e BS	156
c5e8885a	157	/* SPL */
c5e8885a BS	158	#define CONFIG_SPL_FRAMEWORK
	159	#define CONFIG_SPL_TEXT_BASE 0x300000
	160	#define CONFIG_SPL_MAX_SIZE 0x10000
	161	#define CONFIG_SPL_BSS_START_ADDR 0x20000000
	162	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	163	#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
	164	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	165
c5e8885a	166	#define CONFIG_SPL_BOARD_INIT
8a45b0ba BS	167	#define CONFIG_SYS_MONITOR_LEN (512 << 10)
8a45b0ba BS	168
c5e8885a	169	#ifdef CONFIG_SYS_USE_MMC
993ea97e	170	#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
c5e8885a BS	171	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
c5e8885a BS	172	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
e2ccdf89	173	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
205b4f33	174	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
8a45b0ba	175
27019e4a	176	#elif CONFIG_SYS_USE_NANDFLASH
27019e4a BS	177	#define CONFIG_SPL_NAND_DRIVERS
	178	#define CONFIG_SPL_NAND_BASE
	179	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	180	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	181	#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
	182	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	183	#define CONFIG_SYS_NAND_OOBSIZE 64
	184	#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
	185	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
e166a831	186	#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
27019e4a	187
8a45b0ba	188	#elif CONFIG_SYS_USE_SERIALFLASH
8a45b0ba	189	#define CONFIG_SPL_SPI_LOAD
7a53b954	190	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
8a45b0ba	191
c5e8885a BS	192	#endif
c5e8885a BS	193
3225f34e	194	#endif