[J-u-boot.git] / board / freescale / ls1046ardb / cpld.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2016 Freescale Semiconductor
 *
 * Freescale LS1046ARDB board-specific CPLD controlling supports.
 */

#include <config.h>
#include <command.h>
#include <asm/io.h>
#include "cpld.h"

u8 cpld_read(unsigned int reg)
{
	void *p = (void *)CFG_SYS_CPLD_BASE;

	return in_8(p + reg);
}

void cpld_write(unsigned int reg, u8 value)
{
	void *p = (void *)CFG_SYS_CPLD_BASE;

	out_8(p + reg, value);
}

/* Set the boot bank to the alternate bank */
void cpld_set_altbank(void)
{
	u16 reg = CPLD_CFG_RCW_SRC_QSPI;
	u8 reg4 = CPLD_READ(soft_mux_on);
	u8 reg5 = (u8)(reg >> 1);
	u8 reg6 = (u8)(reg & 1);
	u8 reg7 = CPLD_READ(vbank);

	cpld_rev_bit(&reg5);

	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);

	CPLD_WRITE(cfg_rcw_src1, reg5);
	CPLD_WRITE(cfg_rcw_src2, reg6);

	reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
	CPLD_WRITE(vbank, reg7);

	CPLD_WRITE(system_rst, 1);
}

/* Set the boot bank to the default bank */
void cpld_set_defbank(void)
{
	u16 reg = CPLD_CFG_RCW_SRC_QSPI;
	u8 reg4 = CPLD_READ(soft_mux_on);
	u8 reg5 = (u8)(reg >> 1);
	u8 reg6 = (u8)(reg & 1);

	cpld_rev_bit(&reg5);

	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);

	CPLD_WRITE(cfg_rcw_src1, reg5);
	CPLD_WRITE(cfg_rcw_src2, reg6);

	CPLD_WRITE(vbank, 0);

	CPLD_WRITE(system_rst, 1);
}

void cpld_set_sd(void)
{
	u16 reg = CPLD_CFG_RCW_SRC_SD;
	u8 reg5 = (u8)(reg >> 1);
	u8 reg6 = (u8)(reg & 1);

	cpld_rev_bit(&reg5);

	CPLD_WRITE(soft_mux_on, 1);

	CPLD_WRITE(cfg_rcw_src1, reg5);
	CPLD_WRITE(cfg_rcw_src2, reg6);

	CPLD_WRITE(system_rst, 1);
}

void cpld_select_core_volt(bool en_0v9)
{
	u8 reg17 = en_0v9;

	CPLD_WRITE(vdd_en, 1);
	CPLD_WRITE(vdd_sel, reg17);
}

#ifdef DEBUG
static void cpld_dump_regs(void)
{
	printf("cpld_ver	= %x\n", CPLD_READ(cpld_ver));
	printf("cpld_ver_sub	= %x\n", CPLD_READ(cpld_ver_sub));
	printf("pcba_ver	= %x\n", CPLD_READ(pcba_ver));
	printf("soft_mux_on	= %x\n", CPLD_READ(soft_mux_on));
	printf("cfg_rcw_src1	= %x\n", CPLD_READ(cfg_rcw_src1));
	printf("cfg_rcw_src2	= %x\n", CPLD_READ(cfg_rcw_src2));
	printf("vbank		= %x\n", CPLD_READ(vbank));
	printf("sysclk_sel	= %x\n", CPLD_READ(sysclk_sel));
	printf("uart_sel	= %x\n", CPLD_READ(uart_sel));
	printf("sd1refclk_sel	= %x\n", CPLD_READ(sd1refclk_sel));
	printf("rgmii_1588_sel	= %x\n", CPLD_READ(rgmii_1588_sel));
	printf("1588_clk_sel	= %x\n", CPLD_READ(reg_1588_clk_sel));
	printf("status_led	= %x\n", CPLD_READ(status_led));
	printf("sd_emmc		= %x\n", CPLD_READ(sd_emmc));
	printf("vdd_en		= %x\n", CPLD_READ(vdd_en));
	printf("vdd_sel		= %x\n", CPLD_READ(vdd_sel));
	putc('\n');
}
#endif

void cpld_rev_bit(unsigned char *value)
{
	u8 rev_val, val;
	int i;

	val = *value;
	rev_val = val & 1;
	for (i = 1; i <= 7; i++) {
		val >>= 1;
		rev_val <<= 1;
		rev_val |= val & 1;
	}

	*value = rev_val;
}

int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	int rc = 0;

	if (argc <= 1)
		return cmd_usage(cmdtp);

	if (strcmp(argv[1], "reset") == 0) {
		if (strcmp(argv[2], "altbank") == 0)
			cpld_set_altbank();
		else if (strcmp(argv[2], "sd") == 0)
			cpld_set_sd();
		else
			cpld_set_defbank();
#ifdef DEBUG
	} else if (strcmp(argv[1], "dump") == 0) {
		cpld_dump_regs();
#endif
	} else {
		rc = cmd_usage(cmdtp);
	}

	return rc;
}

U_BOOT_CMD(
	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
	"Reset the board or alternate bank",
	"reset: reset to default bank\n"
	"cpld reset altbank: reset to alternate bank\n"
	"cpld reset sd: reset to boot from SD card\n"
#ifdef DEBUG
	"cpld dump - display the CPLD registers\n"
#endif
);
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
dd02936f MH	2	/*
	3	* Copyright 2016 Freescale Semiconductor
	4	*
dd02936f MH	5	* Freescale LS1046ARDB board-specific CPLD controlling supports.
	6	*/
	7
b8d59ba0	8	#include <config.h>
dd02936f MH	9	#include <command.h>
	10	#include <asm/io.h>
	11	#include "cpld.h"
	12
	13	u8 cpld_read(unsigned int reg)
	14	{
65cc0e2a	15	void p = (void )CFG_SYS_CPLD_BASE;
dd02936f MH	16
	17	return in_8(p + reg);
	18	}
	19
	20	void cpld_write(unsigned int reg, u8 value)
	21	{
65cc0e2a	22	void p = (void )CFG_SYS_CPLD_BASE;
dd02936f MH	23
	24	out_8(p + reg, value);
	25	}
	26
	27	/* Set the boot bank to the alternate bank */
	28	void cpld_set_altbank(void)
	29	{
	30	u16 reg = CPLD_CFG_RCW_SRC_QSPI;
	31	u8 reg4 = CPLD_READ(soft_mux_on);
	32	u8 reg5 = (u8)(reg >> 1);
	33	u8 reg6 = (u8)(reg & 1);
	34	u8 reg7 = CPLD_READ(vbank);
	35
	36	cpld_rev_bit(&reg5);
	37
	38	CPLD_WRITE(soft_mux_on, reg4 \| CPLD_SW_MUX_BANK_SEL \| 1);
	39
	40	CPLD_WRITE(cfg_rcw_src1, reg5);
	41	CPLD_WRITE(cfg_rcw_src2, reg6);
	42
	43	reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) \| CPLD_BANK_SEL_ALTBANK;
	44	CPLD_WRITE(vbank, reg7);
	45
	46	CPLD_WRITE(system_rst, 1);
	47	}
	48
	49	/* Set the boot bank to the default bank */
	50	void cpld_set_defbank(void)
	51	{
	52	u16 reg = CPLD_CFG_RCW_SRC_QSPI;
	53	u8 reg4 = CPLD_READ(soft_mux_on);
	54	u8 reg5 = (u8)(reg >> 1);
	55	u8 reg6 = (u8)(reg & 1);
	56
	57	cpld_rev_bit(&reg5);
	58
	59	CPLD_WRITE(soft_mux_on, reg4 \| CPLD_SW_MUX_BANK_SEL \| 1);
	60
	61	CPLD_WRITE(cfg_rcw_src1, reg5);
	62	CPLD_WRITE(cfg_rcw_src2, reg6);
	63
	64	CPLD_WRITE(vbank, 0);
	65
	66	CPLD_WRITE(system_rst, 1);
	67	}
	68
	69	void cpld_set_sd(void)
	70	{
	71	u16 reg = CPLD_CFG_RCW_SRC_SD;
	72	u8 reg5 = (u8)(reg >> 1);
	73	u8 reg6 = (u8)(reg & 1);
	74
	75	cpld_rev_bit(&reg5);
	76
	77	CPLD_WRITE(soft_mux_on, 1);
	78
	79	CPLD_WRITE(cfg_rcw_src1, reg5);
	80	CPLD_WRITE(cfg_rcw_src2, reg6);
	81
	82	CPLD_WRITE(system_rst, 1);
	83	}
6424577b HZ	84
	85	void cpld_select_core_volt(bool en_0v9)
	86	{
	87	u8 reg17 = en_0v9;
	88
	89	CPLD_WRITE(vdd_en, 1);
	90	CPLD_WRITE(vdd_sel, reg17);
	91	}
	92
dd02936f MH	93	#ifdef DEBUG
	94	static void cpld_dump_regs(void)
	95	{
	96	printf("cpld_ver = %x\n", CPLD_READ(cpld_ver));
	97	printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub));
	98	printf("pcba_ver = %x\n", CPLD_READ(pcba_ver));
	99	printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on));
	100	printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1));
	101	printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2));
	102	printf("vbank = %x\n", CPLD_READ(vbank));
	103	printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel));
	104	printf("uart_sel = %x\n", CPLD_READ(uart_sel));
	105	printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel));
	106	printf("rgmii_1588_sel = %x\n", CPLD_READ(rgmii_1588_sel));
	107	printf("1588_clk_sel = %x\n", CPLD_READ(reg_1588_clk_sel));
	108	printf("status_led = %x\n", CPLD_READ(status_led));
	109	printf("sd_emmc = %x\n", CPLD_READ(sd_emmc));
	110	printf("vdd_en = %x\n", CPLD_READ(vdd_en));
	111	printf("vdd_sel = %x\n", CPLD_READ(vdd_sel));
	112	putc('\n');
	113	}
	114	#endif
	115
	116	void cpld_rev_bit(unsigned char *value)
	117	{
	118	u8 rev_val, val;
	119	int i;
	120
	121	val = *value;
	122	rev_val = val & 1;
	123	for (i = 1; i <= 7; i++) {
	124	val >>= 1;
	125	rev_val <<= 1;
	126	rev_val \|= val & 1;
	127	}
	128
	129	*value = rev_val;
	130	}
	131
09140113	132	int do_cpld(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
dd02936f MH	133	{
	134	int rc = 0;
	135
	136	if (argc <= 1)
	137	return cmd_usage(cmdtp);
	138
	139	if (strcmp(argv[1], "reset") == 0) {
	140	if (strcmp(argv[2], "altbank") == 0)
	141	cpld_set_altbank();
	142	else if (strcmp(argv[2], "sd") == 0)
	143	cpld_set_sd();
	144	else
	145	cpld_set_defbank();
	146	#ifdef DEBUG
	147	} else if (strcmp(argv[1], "dump") == 0) {
	148	cpld_dump_regs();
	149	#endif
	150	} else {
	151	rc = cmd_usage(cmdtp);
	152	}
	153
	154	return rc;
	155	}
	156
	157	U_BOOT_CMD(
	158	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
	159	"Reset the board or alternate bank",
	160	"reset: reset to default bank\n"
	161	"cpld reset altbank: reset to alternate bank\n"
	162	"cpld reset sd: reset to boot from SD card\n"
	163	#ifdef DEBUG
	164	"cpld dump - display the CPLD registers\n"
	165	#endif
	166	);