[J-u-boot.git] / include / configs / bf537-stamp.h

/*
 * U-boot - Configuration file for BF537 STAMP board
 */

#ifndef __CONFIG_BF537_H__
#define __CONFIG_BF537_H__

#include <asm/blackfin-config-pre.h>

#define CFG_LONGHELP		1
#define CONFIG_CMDLINE_EDITING	1
#define CONFIG_BAUDRATE		57600
/* Set default serial console for bf537 */
#define CONFIG_UART_CONSOLE	0
#define CONFIG_BF537		1
#define CONFIG_BOOTDELAY	5
/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
/*#define CONFIG_BF537_STAMP_LEDCMD	1*/

/*
 * Boot Mode Set
 * Blackfin can support several boot modes
 */
#define BF537_BYPASS_BOOT	0x0011	/* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM)  */
#define BF537_PARA_BOOT		0x0012	/* Bootmode 1: Boot from 8-bit or 16-bit flash                          */
#define BF537_SPI_MASTER_BOOT	0x0014	/* Bootmode 3: SPI master mode boot from SPI flash                      */
#define BF537_SPI_SLAVE_BOOT	0x0015	/* Bootmode 4: SPI slave mode boot from SPI flash                       */
#define BF537_TWI_MASTER_BOOT	0x0016	/* Bootmode 5: TWI master mode boot from EEPROM                         */
#define BF537_TWI_SLAVE_BOOT	0x0017	/* Bootmode 6: TWI slave mode boot from EEPROM                          */
#define BF537_UART_BOOT		0x0018	/* Bootmode 7: UART slave mdoe boot via UART host                       */
/* Define the boot mode */
#define BFIN_BOOT_MODE		BF537_BYPASS_BOOT

#define CONFIG_PANIC_HANG 1

#define CONFIG_BFIN_CPU	bf537-0.2
#define CONFIG_BFIN_MAC

/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
#define CONFIG_DCACHE_ON

/* Define if want to do post memory test */
#undef CONFIG_POST_TEST

/* Define where the uboot will be loaded by on-chip boot rom */
#define APP_ENTRY 0x00001000

#define CONFIG_RTC_BFIN		1
#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */

/* CONFIG_CLKIN_HZ is any value in Hz				*/
#define CONFIG_CLKIN_HZ		25000000
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
/*						    1=CLKIN/2	*/
#define CONFIG_CLKIN_HALF	0
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
/*						    1=bypass PLL*/
#define CONFIG_PLL_BYPASS	0
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
/* Values can range from 1-64					*/
#define CONFIG_VCO_MULT			20
/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
/* Values can be 1, 2, 4, or 8 ONLY				*/
#define CONFIG_CCLK_DIV			1
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
/* Values can range from 1-15					*/
#define CONFIG_SCLK_DIV			5
/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
/* Values can range from 2-65535				*/
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
#define CONFIG_SPI_BAUD			2
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
#define CONFIG_SPI_BAUD_INITBLOCK	4
#endif

#if ( CONFIG_CLKIN_HALF == 0 )
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
#else
#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
#endif

#if (CONFIG_PLL_BYPASS == 0)
#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
#else
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif

#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
#define CONFIG_SPI_FLASH_FAST_READ 1	/* Needed if SPI_CLK > 20 MHz */
#else
#undef CONFIG_SPI_FLASH_FAST_READ
#endif
#endif

#define CONFIG_MEM_SIZE			64	/* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH		10	/* 8, 9, 10, 11 */
#define CONFIG_MEM_MT48LC32M8A2_75	1

#define CONFIG_LOADS_ECHO		1

/*
 * rarpb, bootp or dhcp commands will perform only a
 * configuration lookup from the BOOTP/DHCP server
 * but not try to load any image using TFTP
 */
#define CFG_AUTOLOAD			"no"

/*
 * Network Settings
 */
/* network support */
#ifdef CONFIG_BFIN_MAC
#define CONFIG_IPADDR		192.168.0.15
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_GATEWAYIP	192.168.0.1
#define CONFIG_SERVERIP		192.168.0.2
#define CONFIG_HOSTNAME		BF537
#endif

#define CONFIG_ROOTPATH		/romfs
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */

#define CFG_LONGHELP		1
#define CONFIG_BOOTDELAY	5
#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
#define CONFIG_BOOTCOMMAND 	"run ramboot"

#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) && defined(CONFIG_POST_TEST)
/* POST support */
#define CONFIG_POST 		( CFG_POST_MEMORY | \
				  CFG_POST_UART	  | \
				  CFG_POST_FLASH  | \
				  CFG_POST_ETHER  | \
				  CFG_POST_LED	  | \
				  CFG_POST_BUTTON)
#else
#undef CONFIG_POST
#endif

#ifdef CONFIG_POST
#define FLASH_START_POST_BLOCK	11	/* Should > = 11 */
#define FLASH_END_POST_BLOCK	71	/* Should < = 71 */
#endif

/* CF-CARD IDE-HDD Support */

/* #define CONFIG_BFIN_TRUE_IDE */	/* Add CF flash card support */
/* #define CONFIG_BFIN_CF_IDE */	/* Add CF flash card support */
/* #define CONFIG_BFIN_HDD_IDE */	/* Add IDE Disk Drive (HDD) support */

#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
# define CONFIG_BFIN_IDE	1
#endif

/*#define CONFIG_BF537_NAND */		/* Add nand flash support */

#define CONFIG_NETCONSOLE	1
#define CONFIG_NET_MULTI	1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)

#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_DATE

#ifndef CONFIG_BFIN_MAC
#undef CONFIG_CMD_NET
#else
#define CONFIG_CMD_PING
#endif

#if defined(CONFIG_BFIN_CF_IDE) \
	|| defined(CONFIG_BFIN_HDD_IDE) \
	|| defined(CONFIG_BFIN_TRUE_IDE)
#define CONFIG_CMD_IDE
#endif

#endif

#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)

#define CONFIG_CMD_DHCP

#if defined(CONFIG_POST)
#define CONFIG_CMD_DIAG
#endif

#ifdef CONFIG_BF537_NAND
#define CONFIG_CMD_NAND
#endif

#endif


#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
#define CONFIG_LOADADDR	0x1000000

#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
#ifdef CONFIG_BFIN_MAC
#define CONFIG_EXTRA_ENV_SETTINGS				\
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
	"nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
	"addip=setenv bootargs $(bootargs) "			\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
	":$(hostname):eth0:off\0"				\
	"ramboot=tftpboot $(loadaddr) linux;"			\
	"run ramargs;run addip;bootelf\0"			\
	"nfsboot=tftpboot $(loadaddr) linux;"			\
	"run nfsargs;run addip;bootelf\0"			\
	"flashboot=bootm 0x20100000\0"				\
	"update=tftpboot $(loadaddr) u-boot.bin;"		\
	"protect off 0x20000000 0x2007FFFF;"			\
	"erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0"	\
	""
#else
#define CONFIG_EXTRA_ENV_SETTINGS				\
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
	"flashboot=bootm 0x20100000\0"				\
	""
#endif
#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
#ifdef CONFIG_BFIN_MAC
#define CONFIG_EXTRA_ENV_SETTINGS				\
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
	"nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
	"addip=setenv bootargs $(bootargs) "			\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
	":$(hostname):eth0:off\0"				\
	"ramboot=tftpboot $(loadaddr) linux;"			\
	"run ramargs;run addip;bootelf\0"			\
	"nfsboot=tftpboot $(loadaddr) linux;"			\
	"run nfsargs;run addip;bootelf\0"			\
	"flashboot=bootm 0x20100000\0"				\
	"update=tftpboot $(loadaddr) u-boot.ldr;"		\
	"eeprom write $(loadaddr) 0x0 $(filesize);\0"		\
	""
#else
#define CONFIG_EXTRA_ENV_SETTINGS				\
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
	"flashboot=bootm 0x20100000\0"				\
	""
#endif
#endif

#define	CFG_PROMPT		"bfin> "	/* Monitor Command Prompt */

#if defined(CONFIG_CMD_KGDB)
#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
#endif
#define CFG_MAX_RAM_SIZE       	(CONFIG_MEM_SIZE * 1024*1024)
#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define	CFG_MAXARGS		16	/* max number of command args */
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_MEMTEST_START	0x0	/* memtest works on */
#define CFG_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024*1024)	/* 1 ... 63 MB in DRAM */
#define	CFG_LOAD_ADDR		CONFIG_LOADADDR	/* default load address */
#define	CFG_HZ			1000	/* decrementer freq: 10 ms ticks */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
#define	CFG_SDRAM_BASE		0x00000000

#define CFG_FLASH_BASE		0x20000000

#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_SIZE	0x4000
#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)

#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */

#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT)
/* for bf537-stamp, usrt boot mode still store env in flash */
#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		0x20004000
#define CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
#define CFG_ENV_IS_IN_EEPROM	1
#define CFG_ENV_OFFSET		0x4000
#define CFG_ENV_HEADER		(CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
#endif
#define CFG_ENV_SIZE		0x2000
#define	CFG_ENV_SECT_SIZE	0x2000	/* Total Size of Environment Sector */
/* #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) */
#define ENV_IS_EMBEDDED
/* #endif */

/* JFFS Partition offset set  */
#define CFG_JFFS2_FIRST_BANK	0
#define CFG_JFFS2_NUM_BANKS	1
/* 512k reserved for u-boot */
#define CFG_JFFS2_FIRST_SECTOR	15

#define CONFIG_SPI

/*
 * Stack sizes
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */

#define POLL_MODE		1
#define FLASH_TOT_SECT		71
#define FLASH_SIZE		0x400000
#define CFG_FLASH_SIZE		0x400000

/*
 * Board NAND Infomation
 */

#define CFG_NAND_ADDR		0x20212000
#define CFG_NAND_BASE		CFG_NAND_ADDR
#define CFG_MAX_NAND_DEVICE	1
#define SECTORSIZE		512
#define ADDR_COLUMN		1
#define ADDR_PAGE		2
#define ADDR_COLUMN_PAGE	3
#define NAND_ChipID_UNKNOWN	0x00
#define NAND_MAX_FLOORS		1
#define NAND_MAX_CHIPS		1
#define BFIN_NAND_READY		PF3

#define NAND_WAIT_READY(nand)  			\
	do { 					\
		int timeout = 0; 		\
		while(!(*pPORTFIO & PF3)) 	\
			if (timeout++ > 100000)	\
				break;		\
	} while (0)

#define BFIN_NAND_CLE		(1<<2)	/* A2 -> Command Enable */
#define BFIN_NAND_ALE		(1<<1)	/* A1 -> Address Enable */

#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))

/*
 * Initialize PSD4256 registers for using I2C
 */
#define CONFIG_MISC_INIT_R

#define CFG_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */

/*
 * I2C settings
 * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
 */
/* #define CONFIG_SOFT_I2C	1*/	/* I2C bit-banged */
#define CONFIG_HARD_I2C		1	/* I2C TWI */
#if defined CONFIG_HARD_I2C
#define CONFIG_TWICLK_KHZ	50
#endif

#if defined CONFIG_SOFT_I2C
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PF_SCL			PF0
#define PF_SDA			PF1

#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
#define I2C_SDA(bit)		if(bit) { \
					*pFIO_FLAG_S = PF_SDA; \
					asm("ssync;"); \
					} \
				else    { \
					*pFIO_FLAG_C = PF_SDA; \
					asm("ssync;"); \
					}
#define I2C_SCL(bit)		if(bit) { \
					*pFIO_FLAG_S = PF_SCL; \
					asm("ssync;"); \
					} \
				else    { \
					*pFIO_FLAG_C = PF_SCL; \
					asm("ssync;"); \
					}
#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
#endif

#define CFG_I2C_SPEED		50000
#define CFG_I2C_SLAVE		0xFE

/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
/* #define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
#define AMBCTL0VAL		(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
				~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
#define AMBCTL1VAL		(B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
				B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
*/

#define AMGCTLVAL		0xFF
#define AMBCTL0VAL		0x7BB07BB0
#define AMBCTL1VAL		0xFFC27BB0

#define CONFIG_VDSP		1

#ifdef CONFIG_VDSP
#define ET_EXEC_VDSP		0x8
#define SHT_STRTAB_VDSP		0x1
#define ELFSHDRSIZE_VDSP	0x2C
#define VDSP_ENTRY_ADDR		0xFFA00000
#endif

#if defined(CONFIG_BFIN_IDE)

#define CONFIG_DOS_PARTITION	1
/*
 * IDE/ATA stuff
 */
#undef  CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
#undef  CONFIG_IDE_LED		/* no led for ide supported */
#undef  CONFIG_IDE_RESET	/* no reset for ide supported */

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses */
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1)	/* max. 1 drives per IDE bus */

#undef  AMBCTL1VAL
#define AMBCTL1VAL		0xFFC3FFC3

#define CONFIG_CF_ATASEL_DIS	0x20311800
#define CONFIG_CF_ATASEL_ENA	0x20311802

#if defined(CONFIG_BFIN_TRUE_IDE)
/*
 * Note that these settings aren't for the most part used in include/ata.h
 * when all of the ATA registers are setup
 */
#define CFG_ATA_BASE_ADDR	0x2031C000
#define CFG_ATA_IDE0_OFFSET	0x0000
#define CFG_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
#define CFG_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET	0x001C	/* Offset for alternate registers */
#define CFG_ATA_STRIDE		2	/* CF.A0 --> Blackfin.Ax */
#endif				/* CONFIG_BFIN_TRUE_IDE */

#if defined(CONFIG_BFIN_CF_IDE)	/* USE CompactFlash Storage Card in the common memory space */
#define CFG_ATA_BASE_ADDR	0x20211800
#define CFG_ATA_IDE0_OFFSET	0x0000
#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET	0x000E	/* Offset for alternate registers */
#define CFG_ATA_STRIDE		1	/* CF.A0 --> Blackfin.Ax */
#endif				/* CONFIG_BFIN_CF_IDE */

#if defined(CONFIG_BFIN_HDD_IDE)	/* USE TRUE IDE */
#define CFG_ATA_BASE_ADDR	0x20314000
#define CFG_ATA_IDE0_OFFSET	0x0000
#define CFG_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
#define CFG_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET	0x001C	/* Offset for alternate registers */
#define CFG_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A1 */

#undef  CONFIG_SCLK_DIV
#define CONFIG_SCLK_DIV		8
#endif				/* CONFIG_BFIN_HDD_IDE */

#endif				/*CONFIG_BFIN_IDE */

#endif
Commit	Line	Data
26bf7dec AL	1	/*
	2	* U-boot - Configuration file for BF537 STAMP board
	3	*/
	4
	5	#ifndef __CONFIG_BF537_H__
	6	#define __CONFIG_BF537_H__
	7
f7ce12cb MF	8	#include <asm/blackfin-config-pre.h>
f7ce12cb MF	9
26bf7dec AL	10	#define CFG_LONGHELP 1
	11	#define CONFIG_CMDLINE_EDITING 1
	12	#define CONFIG_BAUDRATE 57600
	13	/* Set default serial console for bf537 */
	14	#define CONFIG_UART_CONSOLE 0
	15	#define CONFIG_BF537 1
	16	#define CONFIG_BOOTDELAY 5
	17	/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
	18	/#define CONFIG_BF537_STAMP_LEDCMD 1/
	19
	20	/*
	21	* Boot Mode Set
	22	* Blackfin can support several boot modes
	23	*/
	24	#define BF537_BYPASS_BOOT 0x0011 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
	25	#define BF537_PARA_BOOT 0x0012 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
	26	#define BF537_SPI_MASTER_BOOT 0x0014 /* Bootmode 3: SPI master mode boot from SPI flash */
	27	#define BF537_SPI_SLAVE_BOOT 0x0015 /* Bootmode 4: SPI slave mode boot from SPI flash */
	28	#define BF537_TWI_MASTER_BOOT 0x0016 /* Bootmode 5: TWI master mode boot from EEPROM */
	29	#define BF537_TWI_SLAVE_BOOT 0x0017 /* Bootmode 6: TWI slave mode boot from EEPROM */
	30	#define BF537_UART_BOOT 0x0018 /* Bootmode 7: UART slave mdoe boot via UART host */
	31	/* Define the boot mode */
	32	#define BFIN_BOOT_MODE BF537_BYPASS_BOOT
	33
	34	#define CONFIG_PANIC_HANG 1
	35
f7ce12cb MF	36	#define CONFIG_BFIN_CPU bf537-0.2
f7ce12cb MF	37	#define CONFIG_BFIN_MAC
26bf7dec AL	38
	39	/* This sets the default state of the cache on U-Boot's boot */
	40	#define CONFIG_ICACHE_ON
	41	#define CONFIG_DCACHE_ON
	42
	43	/* Define if want to do post memory test */
	44	#undef CONFIG_POST_TEST
	45
	46	/* Define where the uboot will be loaded by on-chip boot rom */
	47	#define APP_ENTRY 0x00001000
	48
	49	#define CONFIG_RTC_BFIN 1
	50	#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
	51
	52	/* CONFIG_CLKIN_HZ is any value in Hz */
	53	#define CONFIG_CLKIN_HZ 25000000
	54	/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
	55	/* 1=CLKIN/2 */
	56	#define CONFIG_CLKIN_HALF 0
	57	/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
	58	/* 1=bypass PLL*/
	59	#define CONFIG_PLL_BYPASS 0
	60	/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
	61	/* Values can range from 1-64 */
	62	#define CONFIG_VCO_MULT 20
	63	/* CONFIG_CCLK_DIV controls what the core clock divider is */
	64	/* Values can be 1, 2, 4, or 8 ONLY */
	65	#define CONFIG_CCLK_DIV 1
	66	/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
	67	/* Values can range from 1-15 */
	68	#define CONFIG_SCLK_DIV 5
	69	/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
	70	/* Values can range from 2-65535 */
	71	/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
	72	#define CONFIG_SPI_BAUD 2
	73	#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
	74	#define CONFIG_SPI_BAUD_INITBLOCK 4
	75	#endif
	76
	77	#if ( CONFIG_CLKIN_HALF == 0 )
	78	#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
	79	#else
	80	#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
	81	#endif
	82
	83	#if (CONFIG_PLL_BYPASS == 0)
	84	#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
	85	#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
	86	#else
	87	#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
	88	#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
	89	#endif
	90
	91	#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
	92	#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
	93	#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
	94	#else
	95	#undef CONFIG_SPI_FLASH_FAST_READ
	96	#endif
	97	#endif
	98
	99	#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
	100	#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
	101	#define CONFIG_MEM_MT48LC32M8A2_75 1
102
103	#define CONFIG_LOADS_ECHO 1
104
105	/*
106	* rarpb, bootp or dhcp commands will perform only a
107	* configuration lookup from the BOOTP/DHCP server
108	* but not try to load any image using TFTP
109	*/
110	#define CFG_AUTOLOAD "no"
111
112	/*
113	* Network Settings
114	*/
115	/* network support */
f7ce12cb	116	#ifdef CONFIG_BFIN_MAC
26bf7dec AL	117	#define CONFIG_IPADDR 192.168.0.15
	118	#define CONFIG_NETMASK 255.255.255.0
	119	#define CONFIG_GATEWAYIP 192.168.0.1
	120	#define CONFIG_SERVERIP 192.168.0.2
	121	#define CONFIG_HOSTNAME BF537
	122	#endif
	123
	124	#define CONFIG_ROOTPATH /romfs
	125	/* Uncomment next line to use fixed MAC address */
	126	/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
	127	/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
	128
	129	#define CFG_LONGHELP 1
	130	#define CONFIG_BOOTDELAY 5
	131	#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
	132	#define CONFIG_BOOTCOMMAND "run ramboot"
	133
	134	#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) && defined(CONFIG_POST_TEST)
	135	/* POST support */
	136	#define CONFIG_POST ( CFG_POST_MEMORY \| \
	137	CFG_POST_UART \| \
	138	CFG_POST_FLASH \| \
	139	CFG_POST_ETHER \| \
	140	CFG_POST_LED \| \
	141	CFG_POST_BUTTON)
	142	#else
	143	#undef CONFIG_POST
	144	#endif
	145
	146	#ifdef CONFIG_POST
26bf7dec AL	147	#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
26bf7dec AL	148	#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
26bf7dec AL	149	#endif
	150
	151	/* CF-CARD IDE-HDD Support */
	152
	153	/* #define CONFIG_BFIN_TRUE_IDE / / Add CF flash card support */
	154	/* #define CONFIG_BFIN_CF_IDE / / Add CF flash card support */
	155	/* #define CONFIG_BFIN_HDD_IDE / / Add IDE Disk Drive (HDD) support */
	156
	157	#if defined(CONFIG_BFIN_CF_IDE) \|\| defined(CONFIG_BFIN_HDD_IDE) \|\| defined(CONFIG_BFIN_TRUE_IDE)
	158	# define CONFIG_BFIN_IDE 1
26bf7dec AL	159	#endif
	160
	161	/#define CONFIG_BF537_NAND / /* Add nand flash support */
	162
26bf7dec AL	163	#define CONFIG_NETCONSOLE 1
	164	#define CONFIG_NET_MULTI 1
	165
079a136c JL	166	/*
	167	* BOOTP options
	168	*/
	169	#define CONFIG_BOOTP_BOOTFILESIZE
	170	#define CONFIG_BOOTP_BOOTPATH
	171	#define CONFIG_BOOTP_GATEWAY
	172	#define CONFIG_BOOTP_HOSTNAME
	173
	174
ba2351f9 JL	175	/*
	176	* Command line configuration.
	177	*/
	178	#include <config_cmd_default.h>
	179
	180	#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) \|\| (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
	181
	182	#define CONFIG_CMD_ELF
	183	#define CONFIG_CMD_I2C
	184	#define CONFIG_CMD_CACHE
	185	#define CONFIG_CMD_JFFS2
	186	#define CONFIG_CMD_EEPROM
	187	#define CONFIG_CMD_DATE
	188
f7ce12cb	189	#ifndef CONFIG_BFIN_MAC
ba2351f9	190	#undef CONFIG_CMD_NET
26bf7dec	191	#else
ba2351f9 JL	192	#define CONFIG_CMD_PING
	193	#endif
	194
	195	#if defined(CONFIG_BFIN_CF_IDE) \
	196	\|\| defined(CONFIG_BFIN_HDD_IDE) \
	197	\|\| defined(CONFIG_BFIN_TRUE_IDE)
	198	#define CONFIG_CMD_IDE
26bf7dec AL	199	#endif
26bf7dec AL	200
ba2351f9 JL	201	#endif
ba2351f9 JL	202
26bf7dec	203	#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
ba2351f9 JL	204
ba2351f9 JL	205	#define CONFIG_CMD_DHCP
af075ee9 JL	206
	207	#if defined(CONFIG_POST)
	208	#define CONFIG_CMD_DIAG
	209	#endif
ba2351f9 JL	210
	211	#ifdef CONFIG_BF537_NAND
	212	#define CONFIG_CMD_NAND
26bf7dec AL	213	#endif
26bf7dec AL	214
ba2351f9 JL	215	#endif
	216
	217
26bf7dec AL	218	#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
	219	#define CONFIG_LOADADDR 0x1000000
	220
	221	#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
f7ce12cb	222	#ifdef CONFIG_BFIN_MAC
26bf7dec AL	223	#define CONFIG_EXTRA_ENV_SETTINGS \
	224	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	225	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	226	"nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
	227	"addip=setenv bootargs $(bootargs) " \
	228	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	229	":$(hostname):eth0:off\0" \
	230	"ramboot=tftpboot $(loadaddr) linux;" \
	231	"run ramargs;run addip;bootelf\0" \
	232	"nfsboot=tftpboot $(loadaddr) linux;" \
	233	"run nfsargs;run addip;bootelf\0" \
	234	"flashboot=bootm 0x20100000\0" \
	235	"update=tftpboot $(loadaddr) u-boot.bin;" \
	236	"protect off 0x20000000 0x2007FFFF;" \
	237	"erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0" \
	238	""
	239	#else
	240	#define CONFIG_EXTRA_ENV_SETTINGS \
	241	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	242	"flashboot=bootm 0x20100000\0" \
	243	""
	244	#endif
	245	#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
f7ce12cb	246	#ifdef CONFIG_BFIN_MAC
26bf7dec AL	247	#define CONFIG_EXTRA_ENV_SETTINGS \
	248	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	249	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	250	"nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
	251	"addip=setenv bootargs $(bootargs) " \
	252	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	253	":$(hostname):eth0:off\0" \
	254	"ramboot=tftpboot $(loadaddr) linux;" \
	255	"run ramargs;run addip;bootelf\0" \
	256	"nfsboot=tftpboot $(loadaddr) linux;" \
	257	"run nfsargs;run addip;bootelf\0" \
	258	"flashboot=bootm 0x20100000\0" \
	259	"update=tftpboot $(loadaddr) u-boot.ldr;" \
	260	"eeprom write $(loadaddr) 0x0 $(filesize);\0" \
	261	""
	262	#else
	263	#define CONFIG_EXTRA_ENV_SETTINGS \
	264	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	265	"flashboot=bootm 0x20100000\0" \
	266	""
	267	#endif
	268	#endif
	269
f7ce12cb	270	#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
26bf7dec	271
ba2351f9	272	#if defined(CONFIG_CMD_KGDB)
26bf7dec AL	273	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	274	#else
	275	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	276	#endif
	277	#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024)
	278	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	279	#define CFG_MAXARGS 16 /* max number of command args */
	280	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	281	#define CFG_MEMTEST_START 0x0 /* memtest works on */
	282	#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 10241024) / 1 ... 63 MB in DRAM */
	283	#define CFG_LOAD_ADDR CONFIG_LOADADDR /* default load address */
	284	#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */
	285	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	286	#define CFG_SDRAM_BASE 0x00000000
	287
	288	#define CFG_FLASH_BASE 0x20000000
	289
	290	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	291	#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
	292	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	293	#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
	294	#define CFG_GBL_DATA_SIZE 0x4000
	295	#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
	296	#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
	297
	298	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	299	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	300	#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
	301
	302	#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) \|\| (BFIN_BOOT_MODE == BF537_UART_BOOT)
	303	/* for bf537-stamp, usrt boot mode still store env in flash */
	304	#define CFG_ENV_IS_IN_FLASH 1
	305	#define CFG_ENV_ADDR 0x20004000
	306	#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
	307	#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
	308	#define CFG_ENV_IS_IN_EEPROM 1
	309	#define CFG_ENV_OFFSET 0x4000
	310	#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
	311	#endif
	312	#define CFG_ENV_SIZE 0x2000
	313	#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
	314	/* #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) */
	315	#define ENV_IS_EMBEDDED
	316	/* #endif */
	317
	318	/* JFFS Partition offset set */
	319	#define CFG_JFFS2_FIRST_BANK 0
	320	#define CFG_JFFS2_NUM_BANKS 1
	321	/* 512k reserved for u-boot */
	322	#define CFG_JFFS2_FIRST_SECTOR 15
	323
	324	#define CONFIG_SPI
	325
	326	/*
	327	* Stack sizes
	328	*/
	329	#define CONFIG_STACKSIZE (1281024) / regular stack */
	330
	331	#define POLL_MODE 1
	332	#define FLASH_TOT_SECT 71
	333	#define FLASH_SIZE 0x400000
	334	#define CFG_FLASH_SIZE 0x400000
	335
	336	/*
337	* Board NAND Infomation
338	*/
339
340	#define CFG_NAND_ADDR 0x20212000
341	#define CFG_NAND_BASE CFG_NAND_ADDR
342	#define CFG_MAX_NAND_DEVICE 1
343	#define SECTORSIZE 512
344	#define ADDR_COLUMN 1
345	#define ADDR_PAGE 2
346	#define ADDR_COLUMN_PAGE 3
347	#define NAND_ChipID_UNKNOWN 0x00
348	#define NAND_MAX_FLOORS 1
349	#define NAND_MAX_CHIPS 1
350	#define BFIN_NAND_READY PF3
351
352	#define NAND_WAIT_READY(nand) \
353	do { \
354	int timeout = 0; \
355	while(!(*pPORTFIO & PF3)) \
356	if (timeout++ > 100000) \
357	break; \
358	} while (0)
359
360	#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
361	#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
362
363	#define WRITE_NAND_COMMAND(d, adr) do{ (volatile __u8 )((unsigned long)adr \| BFIN_NAND_CLE) = (__u8)(d); } while(0)
364	#define WRITE_NAND_ADDRESS(d, adr) do{ (volatile __u8 )((unsigned long)adr \| BFIN_NAND_ALE) = (__u8)(d); } while(0)
365	#define WRITE_NAND(d, adr) do{ (volatile __u8 )((unsigned long)adr) = (__u8)d; } while(0)
366	#define READ_NAND(adr) ((volatile unsigned char)((volatile __u8 )(unsigned long)adr))
367
368	/*
369	* Initialize PSD4256 registers for using I2C
370	*/
371	#define CONFIG_MISC_INIT_R
372
373	#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
374
375	/*
376	* I2C settings
377	* By default PF1 is used as SDA and PF0 as SCL on the Stamp board
378	*/
379	/* #define CONFIG_SOFT_I2C 1/ / I2C bit-banged */
380	#define CONFIG_HARD_I2C 1 /* I2C TWI */
381	#if defined CONFIG_HARD_I2C
382	#define CONFIG_TWICLK_KHZ 50
383	#endif
384
385	#if defined CONFIG_SOFT_I2C
386	/*
387	* Software (bit-bang) I2C driver configuration
388	*/
389	#define PF_SCL PF0
390	#define PF_SDA PF1
391
392	#define I2C_INIT (*pFIO_DIR \|= PF_SCL); asm("ssync;")
393	#define I2C_ACTIVE (pFIO_DIR \|= PF_SDA); pFIO_INEN &= ~PF_SDA; asm("ssync;")
394	#define I2C_TRISTATE (pFIO_DIR &= ~PF_SDA); pFIO_INEN \|= PF_SDA; asm("ssync;")
395	#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
396	#define I2C_SDA(bit) if(bit) { \
397	*pFIO_FLAG_S = PF_SDA; \
398	asm("ssync;"); \
399	} \
400	else { \
401	*pFIO_FLAG_C = PF_SDA; \
402	asm("ssync;"); \
403	}
404	#define I2C_SCL(bit) if(bit) { \
405	*pFIO_FLAG_S = PF_SCL; \
406	asm("ssync;"); \
407	} \
408	else { \
409	*pFIO_FLAG_C = PF_SCL; \
410	asm("ssync;"); \
411	}
412	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
413	#endif
414
415	#define CFG_I2C_SPEED 50000
416	#define CFG_I2C_SLAVE 0xFE
417
418	/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
419	/* #define AMGCTLVAL (AMBEN_P0 \| AMBEN_P1 \| AMBEN_P2 \| AMCKEN)
420	#define AMBCTL0VAL (B1WAT_7 \| B1RAT_11 \| B1HT_2 \| B1ST_3 \| B1TT_4 \| ~B1RDYPOL \| \
421	~B1RDYEN \| B0WAT_7 \| B0RAT_11 \| B0HT_2 \| B0ST_3 \| B0TT_4 \| ~B0RDYPOL \| ~B0RDYEN)
422	#define AMBCTL1VAL (B3WAT_2 \| B3RAT_2 \| B3HT_1 \| B3ST_1 \| B3TT_4 \| B3RDYPOL \| ~B3RDYEN \| \
423	B2WAT_7 \| B2RAT_11 \| B2HT_2 \| B2ST_3 \| B2TT_4 \| ~B2RDYPOL \| ~B2RDYEN)
424	*/
425
426	#define AMGCTLVAL 0xFF
427	#define AMBCTL0VAL 0x7BB07BB0
428	#define AMBCTL1VAL 0xFFC27BB0
429
430	#define CONFIG_VDSP 1
431
432	#ifdef CONFIG_VDSP
433	#define ET_EXEC_VDSP 0x8
434	#define SHT_STRTAB_VDSP 0x1
435	#define ELFSHDRSIZE_VDSP 0x2C
436	#define VDSP_ENTRY_ADDR 0xFFA00000
437	#endif
438
439	#if defined(CONFIG_BFIN_IDE)
440
441	#define CONFIG_DOS_PARTITION 1
442	/*
443	* IDE/ATA stuff
444	*/
445	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
446	#undef CONFIG_IDE_LED /* no led for ide supported */
447	#undef CONFIG_IDE_RESET /* no reset for ide supported */
448
449	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
450	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS1) / max. 1 drives per IDE bus */
451
452	#undef AMBCTL1VAL
453	#define AMBCTL1VAL 0xFFC3FFC3
454
455	#define CONFIG_CF_ATASEL_DIS 0x20311800
456	#define CONFIG_CF_ATASEL_ENA 0x20311802
457
458	#if defined(CONFIG_BFIN_TRUE_IDE)
459	/*
460	* Note that these settings aren't for the most part used in include/ata.h
461	* when all of the ATA registers are setup
462	*/
463	#define CFG_ATA_BASE_ADDR 0x2031C000
464	#define CFG_ATA_IDE0_OFFSET 0x0000
465	#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
466	#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
467	#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
468	#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
469	#endif /* CONFIG_BFIN_TRUE_IDE */
470
471	#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
472	#define CFG_ATA_BASE_ADDR 0x20211800
473	#define CFG_ATA_IDE0_OFFSET 0x0000
474	#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
475	#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
476	#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
477	#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
478	#endif /* CONFIG_BFIN_CF_IDE */
479
480	#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
481	#define CFG_ATA_BASE_ADDR 0x20314000
482	#define CFG_ATA_IDE0_OFFSET 0x0000
483	#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
484	#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
485	#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
486	#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
487
488	#undef CONFIG_SCLK_DIV
489	#define CONFIG_SCLK_DIV 8
490	#endif /* CONFIG_BFIN_HDD_IDE */
491
492	#endif /CONFIG_BFIN_IDE /
493
494	#endif