[J-u-boot.git] / drivers / spi / ti_qspi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * TI QSPI driver
 *
 * Copyright (C) 2013, Texas Instruments, Incorporated
 */

#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/arch/omap.h>
#include <malloc.h>
#include <spi.h>
#include <spi-mem.h>
#include <dm.h>
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <regmap.h>
#include <syscon.h>

DECLARE_GLOBAL_DATA_PTR;

/* ti qpsi register bit masks */
#define QSPI_TIMEOUT                    2000000
#define QSPI_FCLK			192000000
#define QSPI_DRA7XX_FCLK                76800000
#define QSPI_WLEN_MAX_BITS		128
#define QSPI_WLEN_MAX_BYTES		(QSPI_WLEN_MAX_BITS >> 3)
#define QSPI_WLEN_MASK			QSPI_WLEN(QSPI_WLEN_MAX_BITS)
/* clock control */
#define QSPI_CLK_EN                     BIT(31)
#define QSPI_CLK_DIV_MAX                0xffff
/* command */
#define QSPI_EN_CS(n)                   (n << 28)
#define QSPI_WLEN(n)                    ((n-1) << 19)
#define QSPI_3_PIN                      BIT(18)
#define QSPI_RD_SNGL                    BIT(16)
#define QSPI_WR_SNGL                    (2 << 16)
#define QSPI_INVAL                      (4 << 16)
#define QSPI_RD_QUAD                    (7 << 16)
/* device control */
#define QSPI_CKPHA(n)                   (1 << (2 + n*8))
#define QSPI_CSPOL(n)                   (1 << (1 + n*8))
#define QSPI_CKPOL(n)                   (1 << (n*8))
/* status */
#define QSPI_WC                         BIT(1)
#define QSPI_BUSY                       BIT(0)
#define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
#define QSPI_XFER_DONE                  QSPI_WC
#define MM_SWITCH                       0x01
#define MEM_CS(cs)                      ((cs + 1) << 8)
#define MEM_CS_UNSELECT                 0xfffff8ff

#define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
#define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
#define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
#define QSPI_SETUP0_ADDR_SHIFT		(8)
#define QSPI_SETUP0_DBITS_SHIFT		(10)

#define TI_QSPI_SETUP_REG(priv, cs)	(&(priv)->base->setup0 + (cs))

/* ti qspi register set */
struct ti_qspi_regs {
	u32 pid;
	u32 pad0[3];
	u32 sysconfig;
	u32 pad1[3];
	u32 int_stat_raw;
	u32 int_stat_en;
	u32 int_en_set;
	u32 int_en_ctlr;
	u32 intc_eoi;
	u32 pad2[3];
	u32 clk_ctrl;
	u32 dc;
	u32 cmd;
	u32 status;
	u32 data;
	u32 setup0;
	u32 setup1;
	u32 setup2;
	u32 setup3;
	u32 memswitch;
	u32 data1;
	u32 data2;
	u32 data3;
};

/* ti qspi priv */
struct ti_qspi_priv {
	void *memory_map;
	size_t mmap_size;
	uint max_hz;
	u32 num_cs;
	struct ti_qspi_regs *base;
	void *ctrl_mod_mmap;
	ulong fclk;
	unsigned int mode;
	u32 cmd;
	u32 dc;
};

static int ti_qspi_set_speed(struct udevice *bus, uint hz)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);
	uint clk_div;

	if (!hz)
		clk_div = 0;
	else
		clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;

	/* truncate clk_div value to QSPI_CLK_DIV_MAX */
	if (clk_div > QSPI_CLK_DIV_MAX)
		clk_div = QSPI_CLK_DIV_MAX;

	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);

	/* disable SCLK */
	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
	       &priv->base->clk_ctrl);
	/* enable SCLK and program the clk divider */
	writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);

	return 0;
}

static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
{
	writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
	/* dummy readl to ensure bus sync */
	readl(&priv->base->cmd);
}

static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
{
	u32 val;

	val = readl(ctrl_mod_mmap);
	if (enable)
		val |= MEM_CS(cs);
	else
		val &= MEM_CS_UNSELECT;
	writel(val, ctrl_mod_mmap);
}

static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
			const void *dout, void *din, unsigned long flags)
{
	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;
	uint words = bitlen >> 3; /* fixed 8-bit word length */
	const uchar *txp = dout;
	uchar *rxp = din;
	uint status;
	int timeout;
	unsigned int cs = slave->cs;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	if (cs > priv->num_cs) {
		debug("invalid qspi chip select\n");
		return -EINVAL;
	}

	if (bitlen == 0)
		return -1;

	if (bitlen % 8) {
		debug("spi_xfer: Non byte aligned SPI transfer\n");
		return -1;
	}

	/* Setup command reg */
	priv->cmd = 0;
	priv->cmd |= QSPI_WLEN(8);
	priv->cmd |= QSPI_EN_CS(cs);
	if (priv->mode & SPI_3WIRE)
		priv->cmd |= QSPI_3_PIN;
	priv->cmd |= 0xfff;

	while (words) {
		u8 xfer_len = 0;

		if (txp) {
			u32 cmd = priv->cmd;

			if (words >= QSPI_WLEN_MAX_BYTES) {
				u32 *txbuf = (u32 *)txp;
				u32 data;

				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data3);
				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data2);
				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data1);
				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data);
				cmd &= ~QSPI_WLEN_MASK;
				cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
				xfer_len = QSPI_WLEN_MAX_BYTES;
			} else {
				writeb(*txp, &priv->base->data);
				xfer_len = 1;
			}
			debug("tx cmd %08x dc %08x\n",
			      cmd | QSPI_WR_SNGL, priv->dc);
			writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
			status = readl(&priv->base->status);
			timeout = QSPI_TIMEOUT;
			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
				if (--timeout < 0) {
					printf("spi_xfer: TX timeout!\n");
					return -1;
				}
				status = readl(&priv->base->status);
			}
			txp += xfer_len;
			debug("tx done, status %08x\n", status);
		}
		if (rxp) {
			debug("rx cmd %08x dc %08x\n",
			      ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
			writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
			status = readl(&priv->base->status);
			timeout = QSPI_TIMEOUT;
			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
				if (--timeout < 0) {
					printf("spi_xfer: RX timeout!\n");
					return -1;
				}
				status = readl(&priv->base->status);
			}
			*rxp++ = readl(&priv->base->data);
			xfer_len = 1;
			debug("rx done, status %08x, read %02x\n",
			      status, *(rxp-1));
		}
		words -= xfer_len;
	}

	/* Terminate frame */
	if (flags & SPI_XFER_END)
		ti_qspi_cs_deactivate(priv);

	return 0;
}

/* TODO: control from sf layer to here through dm-spi */
static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
{
#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
	unsigned int			addr = (unsigned int) (data);
	unsigned int			edma_slot_num = 1;

	/* Invalidate the area, so no writeback into the RAM races with DMA */
	invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));

	/* enable edma3 clocks */
	enable_edma3_clocks();

	/* Call edma3 api to do actual DMA transfer	*/
	edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);

	/* disable edma3 clocks */
	disable_edma3_clocks();
#else
	memcpy_fromio(data, offset, len);
#endif

	*((unsigned int *)offset) += len;
}

static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
				    u8 opcode, u8 data_nbits, u8 addr_width,
				    u8 dummy_bytes)
{
	u32 memval = opcode;

	switch (data_nbits) {
	case 4:
		memval |= QSPI_SETUP0_READ_QUAD;
		break;
	case 2:
		memval |= QSPI_SETUP0_READ_DUAL;
		break;
	default:
		memval |= QSPI_SETUP0_READ_NORMAL;
		break;
	}

	memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
		   dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);

	writel(memval, TI_QSPI_SETUP_REG(priv, cs));
}

static int ti_qspi_set_mode(struct udevice *bus, uint mode)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);

	priv->dc = 0;
	if (mode & SPI_CPHA)
		priv->dc |= QSPI_CKPHA(0);
	if (mode & SPI_CPOL)
		priv->dc |= QSPI_CKPOL(0);
	if (mode & SPI_CS_HIGH)
		priv->dc |= QSPI_CSPOL(0);

	return 0;
}

static int ti_qspi_exec_mem_op(struct spi_slave *slave,
			       const struct spi_mem_op *op)
{
	struct dm_spi_slave_platdata *slave_plat;
	struct ti_qspi_priv *priv;
	struct udevice *bus;
	u32 from = 0;
	int ret = 0;

	bus = slave->dev->parent;
	priv = dev_get_priv(bus);
	slave_plat = dev_get_parent_platdata(slave->dev);

	/* Only optimize read path. */
	if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
	    !op->addr.nbytes || op->addr.nbytes > 4)
		return -ENOTSUPP;

	/* Address exceeds MMIO window size, fall back to regular mode. */
	from = op->addr.val;
	if (from + op->data.nbytes > priv->mmap_size)
		return -ENOTSUPP;

	ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
				op->data.buswidth, op->addr.nbytes,
				op->dummy.nbytes);

	ti_qspi_copy_mmap((void *)op->data.buf.in,
			  (void *)priv->memory_map + from, op->data.nbytes);

	return ret;
}

static int ti_qspi_claim_bus(struct udevice *dev)
{
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	if (slave_plat->cs > priv->num_cs) {
		debug("invalid qspi chip select\n");
		return -EINVAL;
	}

	writel(MM_SWITCH, &priv->base->memswitch);
	if (priv->ctrl_mod_mmap)
		ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
				       slave_plat->cs, true);

	writel(priv->dc, &priv->base->dc);
	writel(0, &priv->base->cmd);
	writel(0, &priv->base->data);

	priv->dc <<= slave_plat->cs * 8;
	writel(priv->dc, &priv->base->dc);

	return 0;
}

static int ti_qspi_release_bus(struct udevice *dev)
{
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	writel(~MM_SWITCH, &priv->base->memswitch);
	if (priv->ctrl_mod_mmap)
		ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
				       slave_plat->cs, false);

	writel(0, &priv->base->dc);
	writel(0, &priv->base->cmd);
	writel(0, &priv->base->data);
	writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));

	return 0;
}

static int ti_qspi_probe(struct udevice *bus)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);

	priv->fclk = dev_get_driver_data(bus);

	return 0;
}

static void *map_syscon_chipselects(struct udevice *bus)
{
#if CONFIG_IS_ENABLED(SYSCON)
	struct udevice *syscon;
	struct regmap *regmap;
	const fdt32_t *cell;
	int len, err;

	err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
					   "syscon-chipselects", &syscon);
	if (err) {
		debug("%s: unable to find syscon device (%d)\n", __func__,
		      err);
		return NULL;
	}

	regmap = syscon_get_regmap(syscon);
	if (IS_ERR(regmap)) {
		debug("%s: unable to find regmap (%ld)\n", __func__,
		      PTR_ERR(regmap));
		return NULL;
	}

	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
			   "syscon-chipselects", &len);
	if (len < 2*sizeof(fdt32_t)) {
		debug("%s: offset not available\n", __func__);
		return NULL;
	}

	return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
#else
	fdt_addr_t addr;
	addr = devfdt_get_addr_index(bus, 2);
	return (addr == FDT_ADDR_T_NONE) ? NULL :
		map_physmem(addr, 0, MAP_NOCACHE);
#endif
}

static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);
	fdt_addr_t mmap_addr;
	fdt_addr_t mmap_size;

	priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
	priv->base = map_physmem(devfdt_get_addr(bus),
				 sizeof(struct ti_qspi_regs), MAP_NOCACHE);
	mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
	priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
	priv->mmap_size = mmap_size;

	priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
	if (priv->max_hz < 0) {
		debug("Error: Max frequency missing\n");
		return -ENODEV;
	}
	priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);

	debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
	      (int)priv->base, priv->max_hz);

	return 0;
}

static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
	.exec_op = ti_qspi_exec_mem_op,
};

static const struct dm_spi_ops ti_qspi_ops = {
	.claim_bus	= ti_qspi_claim_bus,
	.release_bus	= ti_qspi_release_bus,
	.xfer		= ti_qspi_xfer,
	.set_speed	= ti_qspi_set_speed,
	.set_mode	= ti_qspi_set_mode,
	.mem_ops        = &ti_qspi_mem_ops,
};

static const struct udevice_id ti_qspi_ids[] = {
	{ .compatible = "ti,dra7xxx-qspi",	.data = QSPI_DRA7XX_FCLK},
	{ .compatible = "ti,am4372-qspi",	.data = QSPI_FCLK},
	{ }
};

U_BOOT_DRIVER(ti_qspi) = {
	.name	= "ti_qspi",
	.id	= UCLASS_SPI,
	.of_match = ti_qspi_ids,
	.ops	= &ti_qspi_ops,
	.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
	.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
	.probe	= ti_qspi_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
1d0933ea MP	2	/*
	3	* TI QSPI driver
	4	*
	5	* Copyright (C) 2013, Texas Instruments, Incorporated
1d0933ea MP	6	*/
	7
	8	#include <common.h>
1eb69ae4	9	#include <cpu_func.h>
f7ae49fc	10	#include <log.h>
90526e9f	11	#include <asm/cache.h>
1d0933ea MP	12	#include <asm/io.h>
	13	#include <asm/arch/omap.h>
	14	#include <malloc.h>
	15	#include <spi.h>
4c96c612	16	#include <spi-mem.h>
106f8139	17	#include <dm.h>
570533b8 SP	18	#include <asm/gpio.h>
570533b8 SP	19	#include <asm/omap_gpio.h>
8ddd9c48 V	20	#include <asm/omap_common.h>
8ddd9c48 V	21	#include <asm/ti-common/ti-edma3.h>
61b29b82	22	#include <linux/err.h>
948b8bbd	23	#include <linux/kernel.h>
b06a381a JJH	24	#include <regmap.h>
b06a381a JJH	25	#include <syscon.h>
1d0933ea	26
106f8139 M	27	DECLARE_GLOBAL_DATA_PTR;
106f8139 M	28
1d0933ea MP	29	/* ti qpsi register bit masks */
1d0933ea MP	30	#define QSPI_TIMEOUT 2000000
a6f56ad1 V	31	#define QSPI_FCLK 192000000
a6f56ad1 V	32	#define QSPI_DRA7XX_FCLK 76800000
26036850 V	33	#define QSPI_WLEN_MAX_BITS 128
	34	#define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
	35	#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
1d0933ea	36	/* clock control */
847720c4	37	#define QSPI_CLK_EN BIT(31)
1d0933ea MP	38	#define QSPI_CLK_DIV_MAX 0xffff
	39	/* command */
	40	#define QSPI_EN_CS(n) (n << 28)
	41	#define QSPI_WLEN(n) ((n-1) << 19)
847720c4 JT	42	#define QSPI_3_PIN BIT(18)
847720c4 JT	43	#define QSPI_RD_SNGL BIT(16)
1d0933ea MP	44	#define QSPI_WR_SNGL (2 << 16)
	45	#define QSPI_INVAL (4 << 16)
	46	#define QSPI_RD_QUAD (7 << 16)
	47	/* device control */
1d0933ea MP	48	#define QSPI_CKPHA(n) (1 << (2 + n*8))
	49	#define QSPI_CSPOL(n) (1 << (1 + n*8))
	50	#define QSPI_CKPOL(n) (1 << (n*8))
	51	/* status */
847720c4 JT	52	#define QSPI_WC BIT(1)
847720c4 JT	53	#define QSPI_BUSY BIT(0)
1d0933ea MP	54	#define QSPI_WC_BUSY (QSPI_WC \| QSPI_BUSY)
	55	#define QSPI_XFER_DONE QSPI_WC
	56	#define MM_SWITCH 0x01
ec712f49	57	#define MEM_CS(cs) ((cs + 1) << 8)
8dfd6e21	58	#define MEM_CS_UNSELECT 0xfffff8ff
1d0933ea	59
1d0933ea	60	#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
106f8139	61	#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
1d0933ea	62	#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
4c96c612 VR	63	#define QSPI_SETUP0_ADDR_SHIFT (8)
4c96c612 VR	64	#define QSPI_SETUP0_DBITS_SHIFT (10)
1d0933ea	65
5502c88e VR	66	#define TI_QSPI_SETUP_REG(priv, cs) (&(priv)->base->setup0 + (cs))
5502c88e VR	67
1d0933ea MP	68	/* ti qspi register set */
	69	struct ti_qspi_regs {
	70	u32 pid;
	71	u32 pad0[3];
	72	u32 sysconfig;
	73	u32 pad1[3];
	74	u32 int_stat_raw;
	75	u32 int_stat_en;
	76	u32 int_en_set;
	77	u32 int_en_ctlr;
	78	u32 intc_eoi;
	79	u32 pad2[3];
	80	u32 clk_ctrl;
	81	u32 dc;
	82	u32 cmd;
	83	u32 status;
	84	u32 data;
	85	u32 setup0;
	86	u32 setup1;
	87	u32 setup2;
	88	u32 setup3;
	89	u32 memswitch;
	90	u32 data1;
	91	u32 data2;
	92	u32 data3;
	93	};
	94
9c42558a M	95	/* ti qspi priv */
9c42558a M	96	struct ti_qspi_priv {
106f8139	97	void *memory_map;
4c96c612	98	size_t mmap_size;
106f8139 M	99	uint max_hz;
106f8139 M	100	u32 num_cs;
1d0933ea	101	struct ti_qspi_regs *base;
22309144	102	void *ctrl_mod_mmap;
a6f56ad1	103	ulong fclk;
1d0933ea MP	104	unsigned int mode;
	105	u32 cmd;
	106	u32 dc;
	107	};
	108
61ae9782	109	static int ti_qspi_set_speed(struct udevice *bus, uint hz)
1d0933ea	110	{
61ae9782	111	struct ti_qspi_priv *priv = dev_get_priv(bus);
1d0933ea MP	112	uint clk_div;
1d0933ea MP	113
1d0933ea MP	114	if (!hz)
	115	clk_div = 0;
	116	else
948b8bbd V	117	clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
	118
	119	/* truncate clk_div value to QSPI_CLK_DIV_MAX */
	120	if (clk_div > QSPI_CLK_DIV_MAX)
	121	clk_div = QSPI_CLK_DIV_MAX;
1d0933ea	122
c595a285 V	123	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
c595a285 V	124
1d0933ea	125	/* disable SCLK */
9c42558a M	126	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
9c42558a M	127	&priv->base->clk_ctrl);
948b8bbd	128	/* enable SCLK and program the clk divider */
9c42558a	129	writel(QSPI_CLK_EN \| clk_div, &priv->base->clk_ctrl);
61ae9782 VR	130
61ae9782 VR	131	return 0;
1d0933ea MP	132	}
1d0933ea MP	133
22309144	134	static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
1d0933ea	135	{
9c42558a	136	writel(priv->cmd \| QSPI_INVAL, &priv->base->cmd);
857db48e	137	/* dummy readl to ensure bus sync */
22309144	138	readl(&priv->base->cmd);
1d0933ea MP	139	}
1d0933ea MP	140
22309144 M	141	static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
	142	{
	143	u32 val;
	144
	145	val = readl(ctrl_mod_mmap);
	146	if (enable)
	147	val \|= MEM_CS(cs);
	148	else
	149	val &= MEM_CS_UNSELECT;
	150	writel(val, ctrl_mod_mmap);
	151	}
	152
61ae9782 VR	153	static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
61ae9782 VR	154	const void dout, void din, unsigned long flags)
1d0933ea	155	{
61ae9782 VR	156	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
	157	struct ti_qspi_priv *priv;
	158	struct udevice *bus;
1d0933ea MP	159	uint words = bitlen >> 3; /* fixed 8-bit word length */
	160	const uchar *txp = dout;
	161	uchar *rxp = din;
	162	uint status;
570533b8	163	int timeout;
61ae9782 VR	164	unsigned int cs = slave->cs;
	165
	166	bus = dev->parent;
	167	priv = dev_get_priv(bus);
	168
	169	if (cs > priv->num_cs) {
	170	debug("invalid qspi chip select\n");
	171	return -EINVAL;
	172	}
570533b8	173
1d0933ea MP	174	if (bitlen == 0)
	175	return -1;
	176
	177	if (bitlen % 8) {
	178	debug("spi_xfer: Non byte aligned SPI transfer\n");
	179	return -1;
	180	}
	181
	182	/* Setup command reg */
9c42558a M	183	priv->cmd = 0;
9c42558a M	184	priv->cmd \|= QSPI_WLEN(8);
22309144	185	priv->cmd \|= QSPI_EN_CS(cs);
9c42558a M	186	if (priv->mode & SPI_3WIRE)
	187	priv->cmd \|= QSPI_3_PIN;
	188	priv->cmd \|= 0xfff;
1d0933ea	189
26036850 V	190	while (words) {
	191	u8 xfer_len = 0;
	192
1d0933ea	193	if (txp) {
26036850 V	194	u32 cmd = priv->cmd;
	195
	196	if (words >= QSPI_WLEN_MAX_BYTES) {
	197	u32 txbuf = (u32 )txp;
	198	u32 data;
	199
	200	data = cpu_to_be32(*txbuf++);
	201	writel(data, &priv->base->data3);
	202	data = cpu_to_be32(*txbuf++);
	203	writel(data, &priv->base->data2);
	204	data = cpu_to_be32(*txbuf++);
	205	writel(data, &priv->base->data1);
	206	data = cpu_to_be32(*txbuf++);
	207	writel(data, &priv->base->data);
	208	cmd &= ~QSPI_WLEN_MASK;
	209	cmd \|= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
	210	xfer_len = QSPI_WLEN_MAX_BYTES;
	211	} else {
	212	writeb(*txp, &priv->base->data);
	213	xfer_len = 1;
	214	}
	215	debug("tx cmd %08x dc %08x\n",
	216	cmd \| QSPI_WR_SNGL, priv->dc);
	217	writel(cmd \| QSPI_WR_SNGL, &priv->base->cmd);
9c42558a	218	status = readl(&priv->base->status);
1d0933ea MP	219	timeout = QSPI_TIMEOUT;
	220	while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
	221	if (--timeout < 0) {
	222	printf("spi_xfer: TX timeout!\n");
	223	return -1;
	224	}
9c42558a	225	status = readl(&priv->base->status);
1d0933ea	226	}
26036850	227	txp += xfer_len;
1d0933ea MP	228	debug("tx done, status %08x\n", status);
	229	}
	230	if (rxp) {
1d0933ea	231	debug("rx cmd %08x dc %08x\n",
69eeefaa	232	((u32)(priv->cmd \| QSPI_RD_SNGL)), priv->dc);
69eeefaa	233	writel(priv->cmd \| QSPI_RD_SNGL, &priv->base->cmd);
9c42558a	234	status = readl(&priv->base->status);
1d0933ea MP	235	timeout = QSPI_TIMEOUT;
	236	while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
	237	if (--timeout < 0) {
	238	printf("spi_xfer: RX timeout!\n");
	239	return -1;
	240	}
9c42558a	241	status = readl(&priv->base->status);
1d0933ea	242	}
9c42558a	243	*rxp++ = readl(&priv->base->data);
26036850	244	xfer_len = 1;
1d0933ea MP	245	debug("rx done, status %08x, read %02x\n",
	246	status, *(rxp-1));
	247	}
26036850	248	words -= xfer_len;
1d0933ea MP	249	}
	250
	251	/* Terminate frame */
	252	if (flags & SPI_XFER_END)
22309144	253	ti_qspi_cs_deactivate(priv);
1d0933ea MP	254
	255	return 0;
	256	}
8ddd9c48 V	257
8ddd9c48 V	258	/* TODO: control from sf layer to here through dm-spi */
4c96c612	259	static void ti_qspi_copy_mmap(void data, void offset, size_t len)
8ddd9c48	260	{
4c96c612	261	#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
8ddd9c48 V	262	unsigned int addr = (unsigned int) (data);
	263	unsigned int edma_slot_num = 1;
	264
	265	/* Invalidate the area, so no writeback into the RAM races with DMA */
	266	invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
	267
	268	/* enable edma3 clocks */
	269	enable_edma3_clocks();
	270
	271	/* Call edma3 api to do actual DMA transfer */
	272	edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
	273
	274	/* disable edma3 clocks */
	275	disable_edma3_clocks();
4c96c612 VR	276	#else
	277	memcpy_fromio(data, offset, len);
	278	#endif
8ddd9c48 V	279
	280	((unsigned int )offset) += len;
	281	}
22309144	282
5502c88e VR	283	static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
5502c88e VR	284	u8 opcode, u8 data_nbits, u8 addr_width,
4c96c612	285	u8 dummy_bytes)
106f8139	286	{
4c96c612	287	u32 memval = opcode;
106f8139	288
4c96c612 VR	289	switch (data_nbits) {
4c96c612 VR	290	case 4:
106f8139	291	memval \|= QSPI_SETUP0_READ_QUAD;
106f8139	292	break;
4c96c612	293	case 2:
106f8139 M	294	memval \|= QSPI_SETUP0_READ_DUAL;
	295	break;
	296	default:
106f8139 M	297	memval \|= QSPI_SETUP0_READ_NORMAL;
	298	break;
	299	}
	300
4c96c612 VR	301	memval \|= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT \|
	302	dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
	303
5502c88e	304	writel(memval, TI_QSPI_SETUP_REG(priv, cs));
106f8139 M	305	}
106f8139 M	306
61ae9782	307	static int ti_qspi_set_mode(struct udevice *bus, uint mode)
106f8139 M	308	{
	309	struct ti_qspi_priv *priv = dev_get_priv(bus);
	310
61ae9782 VR	311	priv->dc = 0;
	312	if (mode & SPI_CPHA)
	313	priv->dc \|= QSPI_CKPHA(0);
	314	if (mode & SPI_CPOL)
	315	priv->dc \|= QSPI_CKPOL(0);
	316	if (mode & SPI_CS_HIGH)
	317	priv->dc \|= QSPI_CSPOL(0);
106f8139 M	318
	319	return 0;
	320	}
	321
4c96c612 VR	322	static int ti_qspi_exec_mem_op(struct spi_slave *slave,
	323	const struct spi_mem_op *op)
	324	{
5502c88e	325	struct dm_spi_slave_platdata *slave_plat;
4c96c612 VR	326	struct ti_qspi_priv *priv;
4c96c612 VR	327	struct udevice *bus;
5502c88e VR	328	u32 from = 0;
5502c88e VR	329	int ret = 0;
4c96c612 VR	330
	331	bus = slave->dev->parent;
	332	priv = dev_get_priv(bus);
5502c88e	333	slave_plat = dev_get_parent_platdata(slave->dev);
4c96c612 VR	334
	335	/* Only optimize read path. */
	336	if (!op->data.nbytes \|\| op->data.dir != SPI_MEM_DATA_IN \|\|
	337	!op->addr.nbytes \|\| op->addr.nbytes > 4)
	338	return -ENOTSUPP;
	339
	340	/* Address exceeds MMIO window size, fall back to regular mode. */
	341	from = op->addr.val;
	342	if (from + op->data.nbytes > priv->mmap_size)
	343	return -ENOTSUPP;
	344
5502c88e VR	345	ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
	346	op->data.buswidth, op->addr.nbytes,
	347	op->dummy.nbytes);
4c96c612 VR	348
	349	ti_qspi_copy_mmap((void *)op->data.buf.in,
	350	(void *)priv->memory_map + from, op->data.nbytes);
	351
	352	return ret;
	353	}
	354
106f8139 M	355	static int ti_qspi_claim_bus(struct udevice *dev)
	356	{
	357	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
106f8139 M	358	struct ti_qspi_priv *priv;
	359	struct udevice *bus;
	360
	361	bus = dev->parent;
	362	priv = dev_get_priv(bus);
	363
	364	if (slave_plat->cs > priv->num_cs) {
	365	debug("invalid qspi chip select\n");
	366	return -EINVAL;
	367	}
	368
4c96c612 VR	369	writel(MM_SWITCH, &priv->base->memswitch);
	370	if (priv->ctrl_mod_mmap)
	371	ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
	372	slave_plat->cs, true);
106f8139	373
61ae9782 VR	374	writel(priv->dc, &priv->base->dc);
	375	writel(0, &priv->base->cmd);
	376	writel(0, &priv->base->data);
	377
	378	priv->dc <<= slave_plat->cs * 8;
	379	writel(priv->dc, &priv->base->dc);
	380
	381	return 0;
106f8139 M	382	}
	383
	384	static int ti_qspi_release_bus(struct udevice *dev)
	385	{
4c96c612	386	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
106f8139 M	387	struct ti_qspi_priv *priv;
	388	struct udevice *bus;
	389
	390	bus = dev->parent;
	391	priv = dev_get_priv(bus);
	392
4c96c612 VR	393	writel(~MM_SWITCH, &priv->base->memswitch);
	394	if (priv->ctrl_mod_mmap)
	395	ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
	396	slave_plat->cs, false);
106f8139	397
61ae9782 VR	398	writel(0, &priv->base->dc);
	399	writel(0, &priv->base->cmd);
	400	writel(0, &priv->base->data);
5502c88e	401	writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
106f8139	402
61ae9782	403	return 0;
106f8139 M	404	}
	405
	406	static int ti_qspi_probe(struct udevice *bus)
	407	{
a6f56ad1 V	408	struct ti_qspi_priv *priv = dev_get_priv(bus);
	409
	410	priv->fclk = dev_get_driver_data(bus);
	411
106f8139 M	412	return 0;
	413	}
	414
b06a381a JJH	415	static void map_syscon_chipselects(struct udevice bus)
	416	{
	417	#if CONFIG_IS_ENABLED(SYSCON)
	418	struct udevice *syscon;
	419	struct regmap *regmap;
	420	const fdt32_t *cell;
	421	int len, err;
	422
	423	err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
	424	"syscon-chipselects", &syscon);
	425	if (err) {
	426	debug("%s: unable to find syscon device (%d)\n", __func__,
	427	err);
	428	return NULL;
	429	}
	430
	431	regmap = syscon_get_regmap(syscon);
	432	if (IS_ERR(regmap)) {
	433	debug("%s: unable to find regmap (%ld)\n", __func__,
	434	PTR_ERR(regmap));
	435	return NULL;
	436	}
	437
da409ccc SG	438	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
da409ccc SG	439	"syscon-chipselects", &len);
b06a381a JJH	440	if (len < 2*sizeof(fdt32_t)) {
	441	debug("%s: offset not available\n", __func__);
	442	return NULL;
	443	}
	444
	445	return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
	446	#else
	447	fdt_addr_t addr;
a821c4af	448	addr = devfdt_get_addr_index(bus, 2);
b06a381a JJH	449	return (addr == FDT_ADDR_T_NONE) ? NULL :
	450	map_physmem(addr, 0, MAP_NOCACHE);
	451	#endif
	452	}
	453
106f8139 M	454	static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
	455	{
	456	struct ti_qspi_priv *priv = dev_get_priv(bus);
	457	const void *blob = gd->fdt_blob;
e160f7d4	458	int node = dev_of_offset(bus);
4c96c612 VR	459	fdt_addr_t mmap_addr;
4c96c612 VR	460	fdt_addr_t mmap_size;
106f8139	461
b06a381a	462	priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
a821c4af SG	463	priv->base = map_physmem(devfdt_get_addr(bus),
a821c4af SG	464	sizeof(struct ti_qspi_regs), MAP_NOCACHE);
4c96c612 VR	465	mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
	466	priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
	467	priv->mmap_size = mmap_size;
106f8139 M	468
	469	priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
	470	if (priv->max_hz < 0) {
	471	debug("Error: Max frequency missing\n");
	472	return -ENODEV;
	473	}
	474	priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
	475
	476	debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
	477	(int)priv->base, priv->max_hz);
	478
	479	return 0;
	480	}
	481
4c96c612 VR	482	static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
	483	.exec_op = ti_qspi_exec_mem_op,
	484	};
106f8139 M	485
	486	static const struct dm_spi_ops ti_qspi_ops = {
	487	.claim_bus = ti_qspi_claim_bus,
	488	.release_bus = ti_qspi_release_bus,
	489	.xfer = ti_qspi_xfer,
	490	.set_speed = ti_qspi_set_speed,
	491	.set_mode = ti_qspi_set_mode,
4c96c612	492	.mem_ops = &ti_qspi_mem_ops,
106f8139 M	493	};
	494
	495	static const struct udevice_id ti_qspi_ids[] = {
a6f56ad1 V	496	{ .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
a6f56ad1 V	497	{ .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
106f8139 M	498	{ }
	499	};
	500
	501	U_BOOT_DRIVER(ti_qspi) = {
	502	.name = "ti_qspi",
	503	.id = UCLASS_SPI,
	504	.of_match = ti_qspi_ids,
	505	.ops = &ti_qspi_ops,
	506	.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
	507	.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
	508	.probe = ti_qspi_probe,
106f8139	509	};