[J-u-boot.git] / drivers / rtc / pl031.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2008
 * Gururaja Hebbar [email protected]
 *
 * reference linux-2.6.20.6/drivers/rtc/rtc-pl031.c
 */

#include <common.h>
#include <command.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <rtc.h>
#include <asm/io.h>
#include <asm/types.h>

/*
 * Register definitions
 */
#define	RTC_DR		0x00	/* Data read register */
#define	RTC_MR		0x04	/* Match register */
#define	RTC_LR		0x08	/* Data load register */
#define	RTC_CR		0x0c	/* Control register */
#define	RTC_IMSC	0x10	/* Interrupt mask and set register */
#define	RTC_RIS		0x14	/* Raw interrupt status register */
#define	RTC_MIS		0x18	/* Masked interrupt status register */
#define	RTC_ICR		0x1c	/* Interrupt clear register */

#define RTC_CR_START	(1 << 0)

struct pl031_platdata {
	phys_addr_t base;
};

static inline u32 pl031_read_reg(struct udevice *dev, int reg)
{
	struct pl031_platdata *pdata = dev_get_platdata(dev);

	return readl(pdata->base + reg);
}

static inline u32 pl031_write_reg(struct udevice *dev, int reg, u32 value)
{
	struct pl031_platdata *pdata = dev_get_platdata(dev);

	return writel(value, pdata->base + reg);
}

/*
 * Probe RTC device
 */
static int pl031_probe(struct udevice *dev)
{
	/* Enable RTC Start in Control register*/
	pl031_write_reg(dev, RTC_CR, RTC_CR_START);

	return 0;
}

/*
 * Get the current time from the RTC
 */
static int pl031_get(struct udevice *dev, struct rtc_time *tm)
{
	unsigned long tim;

	if (!tm)
		return -EINVAL;

	tim = pl031_read_reg(dev, RTC_DR);

	rtc_to_tm(tim, tm);

	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
	      tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
	      tm->tm_hour, tm->tm_min, tm->tm_sec);

	return 0;
}

/*
 * Set the RTC
 */
static int pl031_set(struct udevice *dev, const struct rtc_time *tm)
{
	unsigned long tim;

	if (!tm)
		return -EINVAL;

	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
	      tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
	      tm->tm_hour, tm->tm_min, tm->tm_sec);

	/* Calculate number of seconds this incoming time represents */
	tim = rtc_mktime(tm);

	pl031_write_reg(dev, RTC_LR, tim);

	return 0;
}

/*
 * Reset the RTC. We set the date back to 1970-01-01.
 */
static int pl031_reset(struct udevice *dev)
{
	pl031_write_reg(dev, RTC_LR, 0);

	return 0;
}

static const struct rtc_ops pl031_ops = {
	.get = pl031_get,
	.set = pl031_set,
	.reset = pl031_reset,
};

static const struct udevice_id pl031_ids[] = {
	{ .compatible = "arm,pl031" },
	{ }
};

static int pl031_ofdata_to_platdata(struct udevice *dev)
{
	struct pl031_platdata *pdata = dev_get_platdata(dev);

	pdata->base = dev_read_addr(dev);

	return 0;
}

U_BOOT_DRIVER(rtc_pl031) = {
	.name	= "rtc-pl031",
	.id	= UCLASS_RTC,
	.of_match = pl031_ids,
	.probe	= pl031_probe,
	.ofdata_to_platdata = pl031_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct pl031_platdata),
	.ops	= &pl031_ops,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
535cfa4f GH	2	/*
	3	* (C) Copyright 2008
	4	* Gururaja Hebbar [email protected]
	5	*
	6	* reference linux-2.6.20.6/drivers/rtc/rtc-pl031.c
535cfa4f GH	7	*/
	8
	9	#include <common.h>
	10	#include <command.h>
a370e429 AT	11	#include <dm.h>
a370e429 AT	12	#include <errno.h>
f7ae49fc	13	#include <log.h>
535cfa4f	14	#include <rtc.h>
a370e429 AT	15	#include <asm/io.h>
a370e429 AT	16	#include <asm/types.h>
535cfa4f GH	17
	18	/*
	19	* Register definitions
	20	*/
	21	#define RTC_DR 0x00 /* Data read register */
	22	#define RTC_MR 0x04 /* Match register */
	23	#define RTC_LR 0x08 /* Data load register */
	24	#define RTC_CR 0x0c /* Control register */
	25	#define RTC_IMSC 0x10 /* Interrupt mask and set register */
	26	#define RTC_RIS 0x14 /* Raw interrupt status register */
	27	#define RTC_MIS 0x18 /* Masked interrupt status register */
	28	#define RTC_ICR 0x1c /* Interrupt clear register */
	29
	30	#define RTC_CR_START (1 << 0)
	31
a370e429 AT	32	struct pl031_platdata {
	33	phys_addr_t base;
	34	};
535cfa4f	35
a370e429 AT	36	static inline u32 pl031_read_reg(struct udevice *dev, int reg)
	37	{
	38	struct pl031_platdata *pdata = dev_get_platdata(dev);
535cfa4f	39
a370e429 AT	40	return readl(pdata->base + reg);
	41	}
	42
	43	static inline u32 pl031_write_reg(struct udevice *dev, int reg, u32 value)
535cfa4f	44	{
a370e429	45	struct pl031_platdata *pdata = dev_get_platdata(dev);
535cfa4f	46
a370e429	47	return writel(value, pdata->base + reg);
535cfa4f GH	48	}
	49
	50	/*
a370e429 AT	51	* Probe RTC device
	52	*/
	53	static int pl031_probe(struct udevice *dev)
	54	{
	55	/* Enable RTC Start in Control register*/
	56	pl031_write_reg(dev, RTC_CR, RTC_CR_START);
	57
	58	return 0;
	59	}
	60
	61	/*
	62	* Get the current time from the RTC
535cfa4f	63	*/
a370e429	64	static int pl031_get(struct udevice dev, struct rtc_time tm)
535cfa4f	65	{
a370e429 AT	66	unsigned long tim;
	67
	68	if (!tm)
	69	return -EINVAL;
	70
	71	tim = pl031_read_reg(dev, RTC_DR);
	72
	73	rtc_to_tm(tim, tm);
	74
	75	debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
	76	tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
	77	tm->tm_hour, tm->tm_min, tm->tm_sec);
	78
	79	return 0;
535cfa4f GH	80	}
	81
	82	/*
	83	* Set the RTC
a370e429 AT	84	*/
a370e429 AT	85	static int pl031_set(struct udevice dev, const struct rtc_time tm)
535cfa4f GH	86	{
	87	unsigned long tim;
	88
a370e429 AT	89	if (!tm)
a370e429 AT	90	return -EINVAL;
535cfa4f	91
a370e429 AT	92	debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
	93	tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
	94	tm->tm_hour, tm->tm_min, tm->tm_sec);
535cfa4f GH	95
535cfa4f GH	96	/* Calculate number of seconds this incoming time represents */
a370e429	97	tim = rtc_mktime(tm);
535cfa4f	98
a370e429	99	pl031_write_reg(dev, RTC_LR, tim);
d1e23194	100
a370e429	101	return 0;
535cfa4f GH	102	}
	103
	104	/*
a370e429	105	* Reset the RTC. We set the date back to 1970-01-01.
535cfa4f	106	*/
a370e429	107	static int pl031_reset(struct udevice *dev)
535cfa4f	108	{
a370e429	109	pl031_write_reg(dev, RTC_LR, 0);
535cfa4f	110
a370e429 AT	111	return 0;
a370e429 AT	112	}
535cfa4f	113
a370e429 AT	114	static const struct rtc_ops pl031_ops = {
	115	.get = pl031_get,
	116	.set = pl031_set,
	117	.reset = pl031_reset,
	118	};
535cfa4f	119
a370e429 AT	120	static const struct udevice_id pl031_ids[] = {
	121	{ .compatible = "arm,pl031" },
	122	{ }
	123	};
535cfa4f	124
a370e429 AT	125	static int pl031_ofdata_to_platdata(struct udevice *dev)
	126	{
	127	struct pl031_platdata *pdata = dev_get_platdata(dev);
535cfa4f	128
a370e429	129	pdata->base = dev_read_addr(dev);
535cfa4f GH	130
	131	return 0;
	132	}
	133
a370e429 AT	134	U_BOOT_DRIVER(rtc_pl031) = {
	135	.name = "rtc-pl031",
	136	.id = UCLASS_RTC,
	137	.of_match = pl031_ids,
	138	.probe = pl031_probe,
	139	.ofdata_to_platdata = pl031_ofdata_to_platdata,
	140	.platdata_auto_alloc_size = sizeof(struct pl031_platdata),
	141	.ops = &pl031_ops,
	142	};