[J-u-boot.git] / drivers / cpu / riscv_cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2018, Bin Meng <[email protected]>
 */

#include <common.h>
#include <cpu.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <dm/device-internal.h>
#include <dm/lists.h>

DECLARE_GLOBAL_DATA_PTR;

static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size)
{
	const char *isa;

	isa = dev_read_string(dev, "riscv,isa");
	if (size < (strlen(isa) + 1))
		return -ENOSPC;

	strcpy(buf, isa);

	return 0;
}

static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
{
	const char *mmu;

	dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);

	mmu = dev_read_string(dev, "mmu-type");
	if (!mmu)
		info->features |= BIT(CPU_FEAT_MMU);

	return 0;
}

static int riscv_cpu_get_count(struct udevice *dev)
{
	ofnode node;
	int num = 0;

	ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
		const char *device_type;

		/* skip if hart is marked as not available in the device tree */
		if (!ofnode_is_available(node))
			continue;

		device_type = ofnode_read_string(node, "device_type");
		if (!device_type)
			continue;
		if (strcmp(device_type, "cpu") == 0)
			num++;
	}

	return num;
}

static int riscv_cpu_bind(struct udevice *dev)
{
	struct cpu_platdata *plat = dev_get_parent_platdata(dev);
	struct driver *drv;
	int ret;

	/* save the hart id */
	plat->cpu_id = dev_read_addr(dev);
	/* first examine the property in current cpu node */
	ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
	/* if not found, then look at the parent /cpus node */
	if (ret)
		dev_read_u32(dev->parent, "timebase-frequency",
			     &plat->timebase_freq);

	/*
	 * Bind riscv-timer driver on boot hart.
	 *
	 * We only instantiate one timer device which is enough for U-Boot.
	 * Pass the "timebase-frequency" value as the driver data for the
	 * timer device.
	 *
	 * Return value is not checked since it's possible that the timer
	 * driver is not included.
	 */
	if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) {
		drv = lists_driver_lookup_name("riscv_timer");
		if (!drv) {
			debug("Cannot find the timer driver, not included?\n");
			return 0;
		}

		device_bind_with_driver_data(dev, drv, "riscv_timer",
					     plat->timebase_freq, ofnode_null(),
					     NULL);
	}

	return 0;
}

static const struct cpu_ops riscv_cpu_ops = {
	.get_desc	= riscv_cpu_get_desc,
	.get_info	= riscv_cpu_get_info,
	.get_count	= riscv_cpu_get_count,
};

static const struct udevice_id riscv_cpu_ids[] = {
	{ .compatible = "riscv" },
	{ }
};

U_BOOT_DRIVER(riscv_cpu) = {
	.name = "riscv_cpu",
	.id = UCLASS_CPU,
	.of_match = riscv_cpu_ids,
	.bind = riscv_cpu_bind,
	.ops = &riscv_cpu_ops,
	.flags = DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
833508c0 BM	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2018, Bin Meng <[email protected]>
	4	*/
	5
	6	#include <common.h>
	7	#include <cpu.h>
	8	#include <dm.h>
	9	#include <errno.h>
f7ae49fc	10	#include <log.h>
833508c0 BM	11	#include <dm/device-internal.h>
	12	#include <dm/lists.h>
	13
007056f4 AP	14	DECLARE_GLOBAL_DATA_PTR;
007056f4 AP	15
833508c0 BM	16	static int riscv_cpu_get_desc(struct udevice dev, char buf, int size)
	17	{
	18	const char *isa;
	19
	20	isa = dev_read_string(dev, "riscv,isa");
	21	if (size < (strlen(isa) + 1))
	22	return -ENOSPC;
	23
	24	strcpy(buf, isa);
	25
	26	return 0;
	27	}
	28
	29	static int riscv_cpu_get_info(struct udevice dev, struct cpu_info info)
	30	{
	31	const char *mmu;
	32
	33	dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
	34
	35	mmu = dev_read_string(dev, "mmu-type");
	36	if (!mmu)
	37	info->features \|= BIT(CPU_FEAT_MMU);
	38
	39	return 0;
	40	}
	41
	42	static int riscv_cpu_get_count(struct udevice *dev)
	43	{
	44	ofnode node;
	45	int num = 0;
	46
	47	ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
	48	const char *device_type;
	49
4dfea4b5 BM	50	/* skip if hart is marked as not available in the device tree */
	51	if (!ofnode_is_available(node))
	52	continue;
	53
833508c0 BM	54	device_type = ofnode_read_string(node, "device_type");
	55	if (!device_type)
	56	continue;
	57	if (strcmp(device_type, "cpu") == 0)
	58	num++;
	59	}
	60
	61	return num;
	62	}
	63
	64	static int riscv_cpu_bind(struct udevice *dev)
	65	{
	66	struct cpu_platdata *plat = dev_get_parent_platdata(dev);
	67	struct driver *drv;
	68	int ret;
	69
	70	/* save the hart id */
	71	plat->cpu_id = dev_read_addr(dev);
833508c0 BM	72	/* first examine the property in current cpu node */
	73	ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
	74	/* if not found, then look at the parent /cpus node */
	75	if (ret)
	76	dev_read_u32(dev->parent, "timebase-frequency",
	77	&plat->timebase_freq);
	78
	79	/*
007056f4	80	* Bind riscv-timer driver on boot hart.
833508c0 BM	81	*
	82	* We only instantiate one timer device which is enough for U-Boot.
	83	* Pass the "timebase-frequency" value as the driver data for the
	84	* timer device.
	85	*
	86	* Return value is not checked since it's possible that the timer
	87	* driver is not included.
	88	*/
007056f4	89	if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) {
833508c0 BM	90	drv = lists_driver_lookup_name("riscv_timer");
	91	if (!drv) {
	92	debug("Cannot find the timer driver, not included?\n");
	93	return 0;
	94	}
	95
	96	device_bind_with_driver_data(dev, drv, "riscv_timer",
	97	plat->timebase_freq, ofnode_null(),
	98	NULL);
	99	}
	100
	101	return 0;
	102	}
	103
	104	static const struct cpu_ops riscv_cpu_ops = {
	105	.get_desc = riscv_cpu_get_desc,
	106	.get_info = riscv_cpu_get_info,
	107	.get_count = riscv_cpu_get_count,
	108	};
	109
	110	static const struct udevice_id riscv_cpu_ids[] = {
	111	{ .compatible = "riscv" },
	112	{ }
	113	};
	114
	115	U_BOOT_DRIVER(riscv_cpu) = {
	116	.name = "riscv_cpu",
	117	.id = UCLASS_CPU,
	118	.of_match = riscv_cpu_ids,
	119	.bind = riscv_cpu_bind,
	120	.ops = &riscv_cpu_ops,
	121	.flags = DM_FLAG_PRE_RELOC,
	122	};