[J-u-boot.git] / include / configs / ls1043a_common.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2015 Freescale Semiconductor
 * Copyright 2019-2021 NXP
 */

#ifndef __LS1043A_COMMON_H
#define __LS1043A_COMMON_H

/* SPL build */
#ifdef CONFIG_SPL_BUILD
#define SPL_NO_FMAN
#define SPL_NO_DSPI
#define SPL_NO_PCIE
#define SPL_NO_ENV
#define SPL_NO_MISC
#define SPL_NO_USB
#define SPL_NO_SATA
#define SPL_NO_QE
#define SPL_NO_EEPROM
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
#define SPL_NO_MMC
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
#define SPL_NO_IFC
#endif

#define CONFIG_REMAKE_ELF

#include <asm/arch/stream_id_lsch2.h>
#include <asm/arch/config.h>

/* Link Definitions */
#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
#else
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#endif

#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL

#define CPU_RELEASE_ADDR               secondary_boot_addr

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())

/* SD boot SPL */
#ifdef CONFIG_SD_BOOT

#define CONFIG_SPL_MAX_SIZE		0x17000
#define CONFIG_SPL_STACK		0x1001e000
#define CONFIG_SPL_PAD_TO		0x1d000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_NXP_ESBC */
#endif

/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
#endif /* ifdef CONFIG_NXP_ESBC */

#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */

#endif

/* GPIO */

/* IFC */
#ifndef SPL_NO_IFC
#if defined(CONFIG_TFABOOT) || \
	(!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
/*
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 */
#define CONFIG_SYS_FLASH_BASE			0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
#endif
#endif
#endif

/* I2C */

/* PCIe */
#ifndef SPL_NO_PCIE
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */
#define CONFIG_PCIE3		/* PCIE controller 3 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
#endif

/*  DSPI  */

/* FMan ucode */
#ifndef SPL_NO_FMAN
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE	0x60000

#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
#endif

/* Miscellaneous configurable options */

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#ifndef SPL_NO_MISC
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 0) \
	func(USB, usb, 0) \
	func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#endif

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"fdt_high=0xffffffffffffffff\0"		\
	"initrd_high=0xffffffffffffffff\0"	\
	"fdt_addr=0x64f00000\0"			\
	"kernel_addr=0x61000000\0"		\
	"scriptaddr=0x80000000\0"		\
	"scripthdraddr=0x80080000\0"		\
	"fdtheader_addr_r=0x80100000\0"		\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"		\
	"kernel_start=0x1000000\0"		\
	"kernelheader_start=0x800000\0"		\
	"fdt_addr_r=0x90000000\0"		\
	"load_addr=0xa0000000\0"		\
	"kernelheader_addr=0x60600000\0"	\
	"kernel_size=0x2800000\0"		\
	"kernelheader_size=0x40000\0"		\
	"kernel_addr_sd=0x8000\0"		\
	"kernel_size_sd=0x14000\0"		\
	"kernelhdr_addr_sd=0x3000\0"		\
	"kernelhdr_size_sd=0x10\0"		\
	"console=ttyS0,115200\0"		\
	"boot_os=y\0"				\
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"	\
	BOOTENV					\
	"boot_scripts=ls1043ardb_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1043ardb_bs.out\0"	\
	"scan_dev_for_boot_part="		\
		"part list ${devtype} ${devnum} devplist; "	\
		"env exists devplist || setenv devplist 1; "	\
		"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "			\
				"${devnum}:${distro_bootpart} "	\
				"bootfstype; then "		\
				"run scan_dev_for_boot; "	\
			"fi; "					\
		"done\0"			\
	"boot_a_script="					\
		"load ${devtype} ${devnum}:${distro_bootpart} "	\
			"${scriptaddr} ${prefix}${script}; "	\
		"env exists secureboot && load ${devtype} "	\
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
			"env exists secureboot "	\
			"&& esbc_validate ${scripthdraddr};"	\
		"source ${scriptaddr}\0"			\
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_start $kernel_size; env exists secureboot "	\
		"&& sf read $kernelheader_addr_r $kernelheader_start "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"	\
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "	\
		"$kernel_size; env exists secureboot "	\
		"&& cp.b $kernelheader_addr $kernelheader_addr_r "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"	    \
	"nand_bootcmd=echo Trying load from NAND..;"	\
		"nand info; nand read $load_addr "	\
		"$kernel_start $kernel_size; env exists secureboot "	\
		"&& nand read $kernelheader_addr_r $kernelheader_start "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"	\
	"sd_bootcmd=echo Trying load from SD ..;"       \
		"mmcinfo; mmc read $load_addr "         \
		"$kernel_addr_sd $kernel_size_sd && "     \
		"env exists secureboot && mmc read $kernelheader_addr_r "		\
		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$board\0"


#ifdef CONFIG_TFABOOT
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
			   "env exists secureboot && esbc_halt;"
#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "  \
			   "env exists secureboot && esbc_halt;"
#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "	\
			   "env exists secureboot && esbc_halt;"
#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "	\
			   "env exists secureboot && esbc_halt;"
#endif
#endif

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */

#define CONFIG_SYS_MAXARGS		64	/* max command args */

#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */

#include <asm/arch/soc.h>

#endif /* __LS1043A_COMMON_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
f3a8e2b7 MH	2	/*
f3a8e2b7 MH	3	* Copyright (C) 2015 Freescale Semiconductor
34f39ce8	4	* Copyright 2019-2021 NXP
f3a8e2b7 MH	5	*/
	6
	7	#ifndef __LS1043A_COMMON_H
	8	#define __LS1043A_COMMON_H
	9
4139b170 SG	10	/* SPL build */
	11	#ifdef CONFIG_SPL_BUILD
	12	#define SPL_NO_FMAN
	13	#define SPL_NO_DSPI
	14	#define SPL_NO_PCIE
	15	#define SPL_NO_ENV
	16	#define SPL_NO_MISC
	17	#define SPL_NO_USB
	18	#define SPL_NO_SATA
	19	#define SPL_NO_QE
	20	#define SPL_NO_EEPROM
	21	#endif
	22	#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
	23	#define SPL_NO_MMC
	24	#endif
3c7d647e	25	#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
4139b170 SG	26	#define SPL_NO_IFC
	27	#endif
	28
f3a8e2b7	29	#define CONFIG_REMAKE_ELF
f3a8e2b7	30
5344c7b7	31	#include <asm/arch/stream_id_lsch2.h>
f3a8e2b7	32	#include <asm/arch/config.h>
f3a8e2b7 MH	33
f3a8e2b7 MH	34	/* Link Definitions */
f71b5f11 RB	35	#ifdef CONFIG_TFABOOT
	36	#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
	37	#else
f3a8e2b7	38	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
f71b5f11	39	#endif
f3a8e2b7	40
f3a8e2b7 MH	41	#define CONFIG_VERY_BIG_RAM
	42	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	43	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	44	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
e994dddb	45	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
f3a8e2b7	46
3d3fe8b1	47	#define CPU_RELEASE_ADDR secondary_boot_addr
831c068f	48
f3a8e2b7 MH	49	/* Generic Timer Definitions */
	50	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
	51
f3a8e2b7	52	/* Serial Port */
f3a8e2b7 MH	53	#define CONFIG_SYS_NS16550_SERIAL
f3a8e2b7 MH	54	#define CONFIG_SYS_NS16550_REG_SIZE 1
904110c7	55	#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
f3a8e2b7	56
c7ca8b07 GQ	57	/* SD boot SPL */
c7ca8b07 GQ	58	#ifdef CONFIG_SD_BOOT
c7ca8b07	59
70f9661c	60	#define CONFIG_SPL_MAX_SIZE 0x17000
c7ca8b07 GQ	61	#define CONFIG_SPL_STACK 0x1001e000
	62	#define CONFIG_SPL_PAD_TO 0x1d000
	63
23af484b YS	64	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
23af484b YS	65	CONFIG_SPL_BSS_MAX_SIZE)
c7ca8b07	66	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
23af484b	67	#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
c7ca8b07	68	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
70f9661c	69
5536c3c9	70	#ifdef CONFIG_NXP_ESBC
70f9661c RG	71	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
	72	/*
	73	* HDR would be appended at end of image and copied to DDR along
	74	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	75	* size increases then increase this size in case of secure boot as
	76	* it uses raw u-boot image instead of fit image.
	77	*/
	78	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
	79	#else
	80	#define CONFIG_SYS_MONITOR_LEN 0x100000
5536c3c9	81	#endif /* ifdef CONFIG_NXP_ESBC */
c7ca8b07 GQ	82	#endif
c7ca8b07 GQ	83
3ad44729 GQ	84	/* NAND SPL */
	85	#ifdef CONFIG_NAND_BOOT
	86	#define CONFIG_SPL_PBL_PAD
3ad44729 GQ	87	#define CONFIG_SPL_MAX_SIZE 0x1a000
	88	#define CONFIG_SPL_STACK 0x1001d000
	89	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	90	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	91	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	92	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	93	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	94	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
762f92a6	95
5536c3c9	96	#ifdef CONFIG_NXP_ESBC
762f92a6	97	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
5536c3c9	98	#endif /* ifdef CONFIG_NXP_ESBC */
762f92a6 RG	99
	100	#ifdef CONFIG_U_BOOT_HDR_SIZE
	101	/*
	102	* HDR would be appended at end of image and copied to DDR along
	103	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	104	* size increases then increase this size in case of secure boot as
	105	* it uses raw u-boot image instead of fit image.
	106	*/
	107	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
	108	#else
	109	#define CONFIG_SYS_MONITOR_LEN 0x100000
	110	#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
	111
3ad44729 GQ	112	#endif
3ad44729 GQ	113
be7b6d59	114	/* GPIO */
be7b6d59	115
f3a8e2b7	116	/* IFC */
4139b170	117	#ifndef SPL_NO_IFC
f71b5f11 RB	118	#if defined(CONFIG_TFABOOT) \|\| \
f71b5f11 RB	119	(!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
f3a8e2b7 MH	120	/*
	121	* CONFIG_SYS_FLASH_BASE has the final address (core view)
	122	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
	123	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
	124	* CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
	125	*/
	126	#define CONFIG_SYS_FLASH_BASE 0x60000000
	127	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	128	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
	129
e856bdcf	130	#ifdef CONFIG_MTD_NOR_FLASH
f3a8e2b7 MH	131	#define CONFIG_SYS_FLASH_QUIET_TEST
	132	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	133	#endif
166ef1e9	134	#endif
4139b170	135	#endif
f3a8e2b7 MH	136
f3a8e2b7 MH	137	/* I2C */
f3a8e2b7 MH	138
f3a8e2b7 MH	139	/* PCIe */
4139b170	140	#ifndef SPL_NO_PCIE
f3a8e2b7 MH	141	#define CONFIG_PCIE1 /* PCIE controller 1 */
	142	#define CONFIG_PCIE2 /* PCIE controller 2 */
	143	#define CONFIG_PCIE3 /* PCIE controller 3 */
f3a8e2b7	144
f3a8e2b7	145	#ifdef CONFIG_PCI
f3a8e2b7	146	#define CONFIG_PCI_SCAN_SHOW
f3a8e2b7	147	#endif
4139b170	148	#endif
f3a8e2b7	149
e0579a58	150	/* DSPI */
e0579a58	151
e8297341	152	/* FMan ucode */
4139b170	153	#ifndef SPL_NO_FMAN
e8297341 SX	154	#define CONFIG_SYS_DPAA_FMAN
	155	#ifdef CONFIG_SYS_DPAA_FMAN
	156	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
	157
e8297341 SX	158	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
e8297341 SX	159	#endif
4139b170	160	#endif
e8297341	161
f3a8e2b7	162	/* Miscellaneous configurable options */
f3a8e2b7 MH	163
	164	#define CONFIG_HWCONFIG
	165	#define HWCONFIG_BUFFER_SIZE 128
	166
4139b170	167	#ifndef SPL_NO_MISC
5ba909f4 SL	168	#ifndef CONFIG_SPL_BUILD
	169	#define BOOT_TARGET_DEVICES(func) \
	170	func(MMC, mmc, 0) \
688cdf4c MYK	171	func(USB, usb, 0) \
688cdf4c MYK	172	func(DHCP, dhcp, na)
5ba909f4 SL	173	#include <config_distro_bootcmd.h>
	174	#endif
	175
f3a8e2b7 MH	176	/* Initial environment variables */
	177	#define CONFIG_EXTRA_ENV_SETTINGS \
	178	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
f3a8e2b7 MH	179	"fdt_high=0xffffffffffffffff\0" \
f3a8e2b7 MH	180	"initrd_high=0xffffffffffffffff\0" \
0cf207ec	181	"fdt_addr=0x64f00000\0" \
9b457cc6	182	"kernel_addr=0x61000000\0" \
5ba909f4	183	"scriptaddr=0x80000000\0" \
76bbf1c6	184	"scripthdraddr=0x80080000\0" \
5ba909f4 SL	185	"fdtheader_addr_r=0x80100000\0" \
	186	"kernelheader_addr_r=0x80200000\0" \
	187	"kernel_addr_r=0x81000000\0" \
eb967b96 WH	188	"kernel_start=0x1000000\0" \
eb967b96 WH	189	"kernelheader_start=0x800000\0" \
5ba909f4 SL	190	"fdt_addr_r=0x90000000\0" \
5ba909f4 SL	191	"load_addr=0xa0000000\0" \
507103f8	192	"kernelheader_addr=0x60600000\0" \
ad6767b6	193	"kernel_size=0x2800000\0" \
9b457cc6	194	"kernelheader_size=0x40000\0" \
1c8263de SL	195	"kernel_addr_sd=0x8000\0" \
1c8263de SL	196	"kernel_size_sd=0x14000\0" \
507103f8	197	"kernelhdr_addr_sd=0x3000\0" \
9b457cc6	198	"kernelhdr_size_sd=0x10\0" \
5ba909f4	199	"console=ttyS0,115200\0" \
23af484b	200	"boot_os=y\0" \
43ede0bc	201	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
5ba909f4 SL	202	BOOTENV \
5ba909f4 SL	203	"boot_scripts=ls1043ardb_boot.scr\0" \
76bbf1c6	204	"boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
5ba909f4 SL	205	"scan_dev_for_boot_part=" \
	206	"part list ${devtype} ${devnum} devplist; " \
	207	"env exists devplist \|\| setenv devplist 1; " \
	208	"for distro_bootpart in ${devplist}; do " \
	209	"if fstype ${devtype} " \
	210	"${devnum}:${distro_bootpart} " \
	211	"bootfstype; then " \
	212	"run scan_dev_for_boot; " \
	213	"fi; " \
	214	"done\0" \
76bbf1c6 SG	215	"boot_a_script=" \
	216	"load ${devtype} ${devnum}:${distro_bootpart} " \
	217	"${scriptaddr} ${prefix}${script}; " \
	218	"env exists secureboot && load ${devtype} " \
	219	"${devnum}:${distro_bootpart} " \
78c58082 VP	220	"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
78c58082 VP	221	"env exists secureboot " \
76bbf1c6 SG	222	"&& esbc_validate ${scripthdraddr};" \
76bbf1c6 SG	223	"source ${scriptaddr}\0" \
5ba909f4 SL	224	"qspi_bootcmd=echo Trying load from qspi..;" \
5ba909f4 SL	225	"sf probe && sf read $load_addr " \
283e4ab5 WH	226	"$kernel_start $kernel_size; env exists secureboot " \
283e4ab5 WH	227	"&& sf read $kernelheader_addr_r $kernelheader_start " \
9b457cc6 VPB	228	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
9b457cc6 VPB	229	"bootm $load_addr#$board\0" \
5ba909f4 SL	230	"nor_bootcmd=echo Trying load from nor..;" \
5ba909f4 SL	231	"cp.b $kernel_addr $load_addr " \
9b457cc6 VPB	232	"$kernel_size; env exists secureboot " \
	233	"&& cp.b $kernelheader_addr $kernelheader_addr_r " \
	234	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	235	"bootm $load_addr#$board\0" \
eb967b96 WH	236	"nand_bootcmd=echo Trying load from NAND..;" \
	237	"nand info; nand read $load_addr " \
	238	"$kernel_start $kernel_size; env exists secureboot " \
	239	"&& nand read $kernelheader_addr_r $kernelheader_start " \
	240	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	241	"bootm $load_addr#$board\0" \
1c8263de SL	242	"sd_bootcmd=echo Trying load from SD ..;" \
	243	"mmcinfo; mmc read $load_addr " \
	244	"$kernel_addr_sd $kernel_size_sd && " \
9b457cc6 VPB	245	"env exists secureboot && mmc read $kernelheader_addr_r " \
	246	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	247	" && esbc_validate ${kernelheader_addr_r};" \
1c8263de SL	248	"bootm $load_addr#$board\0"
1c8263de SL	249
5ba909f4	250
f71b5f11 RB	251	#ifdef CONFIG_TFABOOT
	252	#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
	253	"env exists secureboot && esbc_halt;"
	254	#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
	255	"env exists secureboot && esbc_halt;"
	256	#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
	257	"env exists secureboot && esbc_halt;"
1f3d739a PG	258	#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
1f3d739a PG	259	"env exists secureboot && esbc_halt;"
4139b170	260	#endif
f71b5f11	261	#endif
f3a8e2b7 MH	262
	263	/* Monitor Command Prompt */
	264	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
4139b170	265
f3a8e2b7 MH	266	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	267
	268	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	269
457e51cf SG	270	#include <asm/arch/soc.h>
457e51cf SG	271
f3a8e2b7	272	#endif /* __LS1043A_COMMON_H */