[J-u-boot.git] / include / configs / imx8mm_venice.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2021 Gateworks Corporation
 */

#ifndef __IMX8MM_VENICE_H
#define __IMX8MM_VENICE_H

#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>

#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
#define CONFIG_SYS_MONITOR_LEN		SZ_512K
#define CONFIG_SYS_UBOOT_BASE	\
	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_STACK		0x920000
#define CONFIG_SPL_BSS_START_ADDR	0x910000
#define CONFIG_SPL_BSS_MAX_SIZE		SZ_8K
#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_1M

/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR		0x930000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE

#endif

#define MEM_LAYOUT_ENV_SETTINGS \
	"fdt_addr_r=0x44000000\0" \
	"kernel_addr_r=0x42000000\0" \
	"ramdisk_addr_r=0x46400000\0" \
	"scriptaddr=0x46000000\0"

/* Link Definitions */

/* Enable Distro Boot */
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 1) \
	func(MMC, mmc, 2) \
	func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#undef CONFIG_ISO_PARTITION
#else
#define BOOTENV
#endif

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
	BOOTENV \
	MEM_LAYOUT_ENV_SETTINGS \
	"script=boot.scr\0" \
	"bootm_size=0x10000000\0" \
	"ipaddr=192.168.1.22\0" \
	"serverip=192.168.1.146\0" \
	"dev=2\0" \
	"preboot=gsc wd-disable\0" \
	"console=ttymxc1,115200\0" \
	"update_firmware=" \
		"tftpboot $loadaddr $image && " \
		"setexpr blkcnt $filesize + 0x1ff && " \
		"setexpr blkcnt $blkcnt / 0x200 && " \
		"mmc dev $dev && " \
		"mmc write $loadaddr 0x42 $blkcnt\0" \
	"boot_net=" \
		"tftpboot $kernel_addr_r $image && " \
		"booti $kernel_addr_r - $fdtcontroladdr\0" \
	"update_rootfs=" \
		"tftpboot $loadaddr $image && " \
		"gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
	"update_all=" \
		"tftpboot $loadaddr $image && " \
		"gzwrite mmc $dev $loadaddr $filesize\0" \
	"erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"

#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE        SZ_2M
#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#define CONFIG_SYS_SDRAM_BASE           0x40000000

/* SDRAM configuration */
#define PHYS_SDRAM                      0x40000000
#define PHYS_SDRAM_SIZE			SZ_1G /* 1GB DDR */
#define CONFIG_SYS_BOOTM_LEN		SZ_256M

/* UART */
#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		SZ_2K
#define CONFIG_SYS_MAXARGS		64
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)

/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM	2
#define CONFIG_SYS_FSL_ESDHC_ADDR	0
#define CONFIG_SYS_MMC_IMG_LOAD_PART	1

/* FEC */
#define CONFIG_ETHPRIME                 "eth0"
#define CONFIG_FEC_XCV_TYPE             RGMII
#define CONFIG_FEC_MXC_PHYADDR          0
#define FEC_QUIRK_ENET_MAC
#define IMX_FEC_BASE			0x30BE0000

#endif
Commit	Line	Data
03bf8436 TH	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* Copyright 2021 Gateworks Corporation
	4	*/
	5
	6	#ifndef __IMX8MM_VENICE_H
	7	#define __IMX8MM_VENICE_H
	8
	9	#include <asm/arch/imx-regs.h>
	10	#include <linux/sizes.h>
	11
	12	#define CONFIG_SPL_MAX_SIZE (148 * 1024)
	13	#define CONFIG_SYS_MONITOR_LEN SZ_512K
03bf8436 TH	14	#define CONFIG_SYS_UBOOT_BASE \
	15	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
	16
	17	#ifdef CONFIG_SPL_BUILD
	18	#define CONFIG_SPL_STACK 0x920000
	19	#define CONFIG_SPL_BSS_START_ADDR 0x910000
72b3732d	20	#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
03bf8436	21	#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
72b3732d	22	#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M
03bf8436 TH	23
	24	/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
	25	#define CONFIG_MALLOC_F_ADDR 0x930000
	26	/* For RAW image gives a error info not panic */
	27	#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
	28
	29	#endif
	30
	31	#define MEM_LAYOUT_ENV_SETTINGS \
	32	"fdt_addr_r=0x44000000\0" \
	33	"kernel_addr_r=0x42000000\0" \
	34	"ramdisk_addr_r=0x46400000\0" \
	35	"scriptaddr=0x46000000\0"
	36
	37	/* Link Definitions */
03bf8436 TH	38
	39	/* Enable Distro Boot */
	40	#ifndef CONFIG_SPL_BUILD
	41	#define BOOT_TARGET_DEVICES(func) \
	42	func(MMC, mmc, 1) \
	43	func(MMC, mmc, 2) \
	44	func(DHCP, dhcp, na)
	45	#include <config_distro_bootcmd.h>
	46	#undef CONFIG_ISO_PARTITION
	47	#else
	48	#define BOOTENV
	49	#endif
	50
	51	/* Initial environment variables */
	52	#define CONFIG_EXTRA_ENV_SETTINGS \
	53	BOOTENV \
	54	MEM_LAYOUT_ENV_SETTINGS \
	55	"script=boot.scr\0" \
	56	"bootm_size=0x10000000\0" \
	57	"ipaddr=192.168.1.22\0" \
	58	"serverip=192.168.1.146\0" \
	59	"dev=2\0" \
	60	"preboot=gsc wd-disable\0" \
	61	"console=ttymxc1,115200\0" \
	62	"update_firmware=" \
	63	"tftpboot $loadaddr $image && " \
	64	"setexpr blkcnt $filesize + 0x1ff && " \
	65	"setexpr blkcnt $blkcnt / 0x200 && " \
	66	"mmc dev $dev && " \
	67	"mmc write $loadaddr 0x42 $blkcnt\0" \
	68	"boot_net=" \
	69	"tftpboot $kernel_addr_r $image && " \
	70	"booti $kernel_addr_r - $fdtcontroladdr\0" \
	71	"update_rootfs=" \
	72	"tftpboot $loadaddr $image && " \
	73	"gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
	74	"update_all=" \
	75	"tftpboot $loadaddr $image && " \
	76	"gzwrite mmc $dev $loadaddr $filesize\0" \
	77	"erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
	78
	79	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
	80	#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
	81	#define CONFIG_SYS_INIT_SP_OFFSET \
	82	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	83	#define CONFIG_SYS_INIT_SP_ADDR \
	84	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	85
03bf8436 TH	86	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	87
	88	/* SDRAM configuration */
	89	#define PHYS_SDRAM 0x40000000
	90	#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
	91	#define CONFIG_SYS_BOOTM_LEN SZ_256M
	92
	93	/* UART */
	94	#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
	95
	96	/* Monitor Command Prompt */
03bf8436 TH	97	#define CONFIG_SYS_CBSIZE SZ_2K
	98	#define CONFIG_SYS_MAXARGS 64
	99	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	100	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	101	sizeof(CONFIG_SYS_PROMPT) + 16)
	102
	103	/* USDHC */
	104	#define CONFIG_SYS_FSL_USDHC_NUM 2
	105	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	106	#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
	107
03bf8436 TH	108	/* FEC */
	109	#define CONFIG_ETHPRIME "eth0"
	110	#define CONFIG_FEC_XCV_TYPE RGMII
	111	#define CONFIG_FEC_MXC_PHYADDR 0
	112	#define FEC_QUIRK_ENET_MAC
	113	#define IMX_FEC_BASE 0x30BE0000
	114
	115	#endif