[J-u-boot.git] / include / configs / ethernut5.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2011
 * egnite GmbH <[email protected]>
 *
 * Configuation settings for Ethernut 5 with AT91SAM9XE.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/hardware.h>

/* The first stage boot loader expects u-boot running at this address. */

/* The first stage boot loader takes care of low level initialization. */

/* CPU information */

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* 18.432 MHz crystal */

/* 32kB internal SRAM */
#define CONFIG_SRAM_BASE	0x00300000 /*AT91SAM9XE_SRAM_BASE */
#define CONFIG_SRAM_SIZE	(32 << 10)
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
				GENERATED_GBL_DATA_SIZE)

/* 128MB SDRAM in 1 bank */
#define CONFIG_SYS_SDRAM_BASE		0x20000000
#define CONFIG_SYS_SDRAM_SIZE		(128 << 20)

/* 512kB on-chip NOR flash */
# define CONFIG_SYS_MAX_FLASH_BANKS	1
# define CONFIG_SYS_FLASH_BASE		0x00200000 /* AT91SAM9XE_FLASH_BASE */
# define CONFIG_AT91_EFLASH
# define CONFIG_SYS_MAX_FLASH_SECT	32
# define CONFIG_EFLASH_PROTSECTORS	1


/* bootstrap + u-boot + env + linux in dataflash on CS0 */

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x40000000
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
#endif

/* JFFS2 */
#ifdef CONFIG_CMD_JFFS2
#define CONFIG_JFFS2_NAND
#endif

/* Ethernet */
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_RMII
#define CONFIG_PHY_ID			0
#define CONFIG_MACB_SEARCH_PHY

/* MMC */
#ifdef CONFIG_CMD_MMC
#define CONFIG_SYS_MMC_CD_PIN		AT91_PIO_PORTC, 8
#endif

/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00500000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"host"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#endif

/* RTC */
#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
#define CONFIG_SYS_I2C_RTC_ADDR		0x51
#endif

/* I2C */
#define CONFIG_SYS_MAX_I2C_BUS	1

#define I2C_SOFT_DECLARATIONS

#define GPIO_I2C_SCL		AT91_PIO_PORTA, 24
#define GPIO_I2C_SDA		AT91_PIO_PORTA, 23

#define I2C_INIT { \
	at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
	at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
	at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
}

#define I2C_ACTIVE	at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
#define I2C_TRISTATE	at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
#define I2C_SCL(bit)	at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
#define I2C_SDA(bit)	at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
#define I2C_DELAY	udelay(100)
#define I2C_READ	at91_get_pio_value(AT91_PIO_PORTA, 23)

/* DHCP/BOOTP options */
#ifdef CONFIG_CMD_DHCP
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_SYS_AUTOLOAD	"n"
#endif

/* File systems */

/* Boot command */

/* Misc. u-boot settings */

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
14c32614 TS	2	/*
	3	* (C) Copyright 2011
	4	* egnite GmbH <[email protected]>
	5	*
	6	* Configuation settings for Ethernut 5 with AT91SAM9XE.
14c32614 TS	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	#include <asm/hardware.h>
	13
	14	/* The first stage boot loader expects u-boot running at this address. */
14c32614 TS	15
14c32614 TS	16	/* The first stage boot loader takes care of low level initialization. */
14c32614	17
14c32614	18	/* CPU information */
14c32614 TS	19
	20	/* ARM asynchronous clock */
	21	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
	22	#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
14c32614 TS	23
	24	/* 32kB internal SRAM */
	25	#define CONFIG_SRAM_BASE 0x00300000 /AT91SAM9XE_SRAM_BASE /
	26	#define CONFIG_SRAM_SIZE (32 << 10)
3d6ba91e RH	27	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
3d6ba91e RH	28	GENERATED_GBL_DATA_SIZE)
14c32614 TS	29
14c32614 TS	30	/* 128MB SDRAM in 1 bank */
14c32614 TS	31	#define CONFIG_SYS_SDRAM_BASE 0x20000000
14c32614 TS	32	#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
14c32614 TS	33
	34	/* 512kB on-chip NOR flash */
	35	# define CONFIG_SYS_MAX_FLASH_BANKS 1
	36	# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
	37	# define CONFIG_AT91_EFLASH
	38	# define CONFIG_SYS_MAX_FLASH_SECT 32
14c32614 TS	39	# define CONFIG_EFLASH_PROTSECTORS 1
14c32614 TS	40
94db5120 WY	41
94db5120 WY	42	/* bootstrap + u-boot + env + linux in dataflash on CS0 */
14c32614	43
14c32614 TS	44	/* NAND flash */
	45	#ifdef CONFIG_CMD_NAND
	46	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	47	#define CONFIG_SYS_NAND_BASE 0x40000000
	48	#define CONFIG_SYS_NAND_DBW_8
14c32614 TS	49	/* our ALE is AD21 */
	50	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	51	/* our CLE is AD22 */
	52	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
ac45bb16	53	#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
14c32614 TS	54	#endif
	55
	56	/* JFFS2 */
	57	#ifdef CONFIG_CMD_JFFS2
14c32614 TS	58	#define CONFIG_JFFS2_NAND
	59	#endif
	60
	61	/* Ethernet */
14c32614	62	#define CONFIG_NET_RETRY_COUNT 20
14c32614 TS	63	#define CONFIG_RMII
	64	#define CONFIG_PHY_ID 0
	65	#define CONFIG_MACB_SEARCH_PHY
	66
	67	/* MMC */
	68	#ifdef CONFIG_CMD_MMC
14c32614 TS	69	#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
	70	#endif
	71
	72	/* USB */
	73	#ifdef CONFIG_CMD_USB
	74	#define CONFIG_USB_ATMEL
dcd2f1a0	75	#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
14c32614 TS	76	#define CONFIG_USB_OHCI_NEW
	77	#define CONFIG_SYS_USB_OHCI_CPU_INIT
	78	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
	79	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
	80	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
14c32614 TS	81	#endif
	82
	83	/* RTC */
	84	#if defined(CONFIG_CMD_DATE) \|\| defined(CONFIG_CMD_SNTP)
14c32614 TS	85	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
	86	#endif
	87
	88	/* I2C */
	89	#define CONFIG_SYS_MAX_I2C_BUS 1
14c32614	90
14c32614 TS	91	#define I2C_SOFT_DECLARATIONS
	92
	93	#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
	94	#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
	95
	96	#define I2C_INIT { \
	97	at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
	98	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
	99	at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
	100	at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
	101	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
	102	}
	103
	104	#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
	105	#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
	106	#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
	107	#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
	108	#define I2C_DELAY udelay(100)
	109	#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
	110
	111	/* DHCP/BOOTP options */
	112	#ifdef CONFIG_CMD_DHCP
	113	#define CONFIG_BOOTP_BOOTFILESIZE
14c32614 TS	114	#define CONFIG_SYS_AUTOLOAD "n"
	115	#endif
	116
	117	/* File systems */
14c32614 TS	118
14c32614 TS	119	/* Boot command */
14c32614 TS	120
14c32614 TS	121	/* Misc. u-boot settings */
14c32614 TS	122
14c32614 TS	123	#endif