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Commit | Line | Data |
---|---|---|
439321b2 | 1 | CONFIG_ARM=y |
439321b2 PF |
2 | CONFIG_ARCH_IMX8M=y |
3 | CONFIG_SYS_TEXT_BASE=0x40200000 | |
9802154a TR |
4 | CONFIG_SYS_MALLOC_LEN=0x2000000 |
5 | CONFIG_SYS_MALLOC_F_LEN=0x10000 | |
83061dbd | 6 | CONFIG_SPL_GPIO=y |
439321b2 PF |
7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | |
556fd590 TR |
9 | CONFIG_ENV_SIZE=0x1000 |
10 | CONFIG_ENV_OFFSET=0x400000 | |
052170c6 TR |
11 | CONFIG_SYS_I2C_MXC_I2C1=y |
12 | CONFIG_SYS_I2C_MXC_I2C2=y | |
13 | CONFIG_SYS_I2C_MXC_I2C3=y | |
439321b2 | 14 | CONFIG_DM_GPIO=y |
2bba7807 | 15 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" |
c5a6e9f8 | 16 | CONFIG_SPL_TEXT_BASE=0x920000 |
439321b2 | 17 | CONFIG_TARGET_IMX8MP_EVK=y |
103c5f18 | 18 | CONFIG_SPL_MMC=y |
2a736066 | 19 | CONFIG_SPL_SERIAL=y |
9ca00684 | 20 | CONFIG_SPL_DRIVERS_MISC=y |
439321b2 PF |
21 | CONFIG_SPL=y |
22 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | |
06f4e426 | 23 | CONFIG_DISTRO_DEFAULTS=y |
49c8ef0e | 24 | CONFIG_SYS_LOAD_ADDR=0x40480000 |
439321b2 PF |
25 | CONFIG_FIT=y |
26 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | |
27 | CONFIG_SPL_LOAD_FIT=y | |
1e4ed2d6 | 28 | # CONFIG_USE_SPL_FIT_GENERATOR is not set |
439321b2 | 29 | CONFIG_OF_SYSTEM_SETUP=y |
439321b2 | 30 | CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" |
439321b2 | 31 | CONFIG_BOARD_EARLY_INIT_F=y |
0817daa7 | 32 | CONFIG_BOARD_LATE_INIT=y |
439321b2 PF |
33 | CONFIG_SPL_BOARD_INIT=y |
34 | CONFIG_SPL_BOOTROM_SUPPORT=y | |
7635defa | 35 | CONFIG_SPL_SYS_MALLOC_SIMPLE=y |
439321b2 | 36 | CONFIG_SPL_SEPARATE_BSS=y |
f76750d1 TR |
37 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y |
38 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 | |
975e7cf3 | 39 | CONFIG_SPL_I2C=y |
933b2f09 | 40 | CONFIG_SPL_POWER=y |
078111b9 | 41 | CONFIG_SPL_WATCHDOG=y |
439321b2 PF |
42 | CONFIG_SYS_PROMPT="u-boot=> " |
43 | # CONFIG_CMD_EXPORTENV is not set | |
44 | # CONFIG_CMD_IMPORTENV is not set | |
45 | # CONFIG_CMD_CRC32 is not set | |
46 | CONFIG_CMD_CLK=y | |
47 | CONFIG_CMD_FUSE=y | |
48 | CONFIG_CMD_GPIO=y | |
49 | CONFIG_CMD_I2C=y | |
50 | CONFIG_CMD_MMC=y | |
51 | CONFIG_CMD_CACHE=y | |
52 | CONFIG_CMD_REGULATOR=y | |
439321b2 | 53 | CONFIG_CMD_EXT4_WRITE=y |
439321b2 PF |
54 | CONFIG_OF_CONTROL=y |
55 | CONFIG_SPL_OF_CONTROL=y | |
e91907a1 | 56 | CONFIG_ENV_OVERWRITE=y |
439321b2 PF |
57 | CONFIG_ENV_IS_IN_MMC=y |
58 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
7d080773 | 59 | CONFIG_SYS_MMC_ENV_DEV=1 |
439321b2 PF |
60 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
61 | CONFIG_SPL_DM=y | |
62 | CONFIG_CLK_COMPOSITE_CCF=y | |
63 | CONFIG_CLK_IMX8MP=y | |
64 | CONFIG_MXC_GPIO=y | |
65 | CONFIG_DM_PCA953X=y | |
66 | CONFIG_DM_I2C=y | |
a907dce8 | 67 | # CONFIG_SPL_DM_I2C is not set |
55dabcc8 | 68 | CONFIG_SPL_SYS_I2C_LEGACY=y |
439321b2 PF |
69 | CONFIG_LED=y |
70 | CONFIG_LED_GPIO=y | |
439321b2 PF |
71 | CONFIG_SUPPORT_EMMC_BOOT=y |
72 | CONFIG_MMC_IO_VOLTAGE=y | |
e601f0f9 AZ |
73 | CONFIG_MMC_UHS_SUPPORT=y |
74 | CONFIG_MMC_HS400_ES_SUPPORT=y | |
75 | CONFIG_MMC_HS400_SUPPORT=y | |
1ed68f92 | 76 | CONFIG_FSL_USDHC=y |
48b90f86 | 77 | CONFIG_PHY_REALTEK=y |
439321b2 | 78 | CONFIG_DM_ETH=y |
b65dc989 | 79 | CONFIG_DM_ETH_PHY=y |
48b90f86 PF |
80 | CONFIG_PHY_GIGE=y |
81 | CONFIG_DWC_ETH_QOS=y | |
b65dc989 | 82 | CONFIG_DWC_ETH_QOS_IMX=y |
48b90f86 PF |
83 | CONFIG_FEC_MXC=y |
84 | CONFIG_MII=y | |
439321b2 PF |
85 | CONFIG_PINCTRL=y |
86 | CONFIG_SPL_PINCTRL=y | |
87 | CONFIG_PINCTRL_IMX8M=y | |
9d8665b7 | 88 | CONFIG_SPL_POWER_LEGACY=y |
439321b2 PF |
89 | CONFIG_DM_REGULATOR=y |
90 | CONFIG_DM_REGULATOR_FIXED=y | |
91 | CONFIG_DM_REGULATOR_GPIO=y | |
9d8665b7 | 92 | CONFIG_SPL_POWER_I2C=y |
439321b2 PF |
93 | CONFIG_MXC_UART=y |
94 | CONFIG_SYSRESET=y | |
f24dea4e | 95 | CONFIG_SPL_SYSRESET=y |
439321b2 | 96 | CONFIG_SYSRESET_PSCI=y |
f24dea4e | 97 | CONFIG_SYSRESET_WATCHDOG=y |
f24dea4e | 98 | CONFIG_IMX_WATCHDOG=y |