projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| a2ac68fb CK |
1 | /* |
| 2 | * Copyright (C) 2013 Samsung Electronics | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | * | |
| 6 | * Configuration settings for the SAMSUNG Arndale board. | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef __CONFIG_ARNDALE_H | |
| 10 | #define __CONFIG_ARNDALE_H | |
| 11 | ||
| 12 | /* High Level Configuration Options */ | |
| 13 | #define CONFIG_SAMSUNG /* in a SAMSUNG core */ | |
| 14 | #define CONFIG_S5P /* S5P Family */ | |
| 15 | #define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ | |
| 16 | #define CONFIG_EXYNOS5250 | |
| 17 | ||
| 18 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
| 19 | ||
| 20 | #define CONFIG_SYS_GENERIC_BOARD | |
| 21 | #define CONFIG_ARCH_CPU_INIT | |
| 22 | #define CONFIG_DISPLAY_CPUINFO | |
| 23 | #define CONFIG_DISPLAY_BOARDINFO | |
| 24 | ||
| 25 | /* Enable fdt support for Exynos5250 */ | |
| 26 | #define CONFIG_ARCH_DEVICE_TREE exynos5250 | |
| 27 | #define CONFIG_OF_CONTROL | |
| 28 | #define CONFIG_OF_SEPARATE | |
| 29 | ||
| 30 | /* Allow tracing to be enabled */ | |
| 31 | #define CONFIG_TRACE | |
| 32 | #define CONFIG_CMD_TRACE | |
| 33 | #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) | |
| 34 | #define CONFIG_TRACE_EARLY_SIZE (8 << 20) | |
| 35 | #define CONFIG_TRACE_EARLY | |
| 36 | #define CONFIG_TRACE_EARLY_ADDR 0x50000000 | |
| 37 | ||
| 38 | /* Keep L2 Cache Disabled */ | |
| 39 | #define CONFIG_SYS_DCACHE_OFF | |
| 40 | ||
| 41 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
| 42 | #define CONFIG_SYS_TEXT_BASE 0x43E00000 | |
| 43 | ||
| 44 | /* input clock of PLL: SMDK5250 has 24MHz input clock */ | |
| 45 | #define CONFIG_SYS_CLK_FREQ 24000000 | |
| 46 | ||
| 47 | #define CONFIG_SETUP_MEMORY_TAGS | |
| 48 | #define CONFIG_CMDLINE_TAG | |
| 49 | #define CONFIG_INITRD_TAG | |
| 50 | #define CONFIG_CMDLINE_EDITING | |
| 51 | ||
| 52 | /* Power Down Modes */ | |
| 53 | #define S5P_CHECK_SLEEP 0x00000BAD | |
| 54 | #define S5P_CHECK_DIDLE 0xBAD00000 | |
| 55 | #define S5P_CHECK_LPA 0xABAD0000 | |
| 56 | ||
| 57 | /* Offset for inform registers */ | |
| 58 | #define INFORM0_OFFSET 0x800 | |
| 59 | #define INFORM1_OFFSET 0x804 | |
| 60 | ||
| 61 | /* Size of malloc() pool */ | |
| 62 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) | |
| 63 | ||
| 64 | /* select serial console configuration */ | |
| 65 | #define CONFIG_BAUDRATE 115200 | |
| 66 | #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 | |
| 67 | #define CONFIG_SILENT_CONSOLE | |
| 68 | ||
| 69 | /* Console configuration */ | |
| 70 | #define CONFIG_CONSOLE_MUX | |
| 71 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
| 72 | #define EXYNOS_DEVICE_SETTINGS \ | |
| 73 | "stdin=serial\0" \ | |
| 74 | "stdout=serial\0" \ | |
| 75 | "stderr=serial\0" | |
| 76 | ||
| 77 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 78 | EXYNOS_DEVICE_SETTINGS | |
| 79 | ||
| 80 | /* SD/MMC configuration */ | |
| 81 | #define CONFIG_GENERIC_MMC | |
| 82 | #define CONFIG_MMC | |
| 83 | #define CONFIG_SDHCI | |
| 84 | #define CONFIG_S5P_SDHCI | |
| 85 | #define CONFIG_DWMMC | |
| 86 | #define CONFIG_EXYNOS_DWMMC | |
| 87 | #define CONFIG_SUPPORT_EMMC_BOOT | |
| 2a7a210e | 88 | #define CONFIG_BOUNCE_BUFFER |
| a2ac68fb CK |
89 | |
| 90 | ||
| 91 | #define CONFIG_BOARD_EARLY_INIT_F | |
| 92 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
| 93 | ||
| 94 | /* PWM */ | |
| 95 | #define CONFIG_PWM | |
| 96 | ||
| 97 | /* allow to overwrite serial and ethaddr */ | |
| 98 | #define CONFIG_ENV_OVERWRITE | |
| 99 | ||
| 100 | /* Command definition*/ | |
| 101 | #include <config_cmd_default.h> | |
| 102 | ||
| 103 | #define CONFIG_CMD_PING | |
| 104 | #define CONFIG_CMD_ELF | |
| 105 | #define CONFIG_CMD_MMC | |
| 106 | #define CONFIG_CMD_EXT2 | |
| 107 | #define CONFIG_CMD_FAT | |
| 108 | #define CONFIG_CMD_NET | |
| 109 | #define CONFIG_CMD_HASH | |
| 110 | ||
| 111 | #define CONFIG_BOOTDELAY 3 | |
| 112 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
| 113 | ||
| 114 | /* USB */ | |
| 115 | #define CONFIG_CMD_USB | |
| 116 | #define CONFIG_USB_EHCI | |
| 117 | #define CONFIG_USB_EHCI_EXYNOS | |
| 118 | #define CONFIG_USB_STORAGE | |
| 119 | ||
| 7da76512 IS |
120 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 |
| 121 | #define CONFIG_USB_HOST_ETHER | |
| 122 | #define CONFIG_USB_ETHER_ASIX | |
| 123 | ||
| a2ac68fb | 124 | /* MMC SPL */ |
| e106bd9b | 125 | #define CONFIG_EXYNOS_SPL |
| a2ac68fb CK |
126 | #define CONFIG_SPL |
| 127 | #define COPY_BL2_FNPTR_ADDR 0x02020030 | |
| 128 | ||
| 129 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
| 130 | ||
| 131 | /* specific .lds file */ | |
| 132 | #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" | |
| 133 | #define CONFIG_SPL_TEXT_BASE 0x02023400 | |
| 134 | #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) | |
| 135 | ||
| 136 | #define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" | |
| 137 | ||
| 138 | /* Miscellaneous configurable options */ | |
| 139 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 140 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
| 141 | #define CONFIG_SYS_PROMPT "ARNDALE # " | |
| 142 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 143 | #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ | |
| 144 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 145 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" | |
| 146 | /* Boot Argument Buffer Size */ | |
| 147 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 148 | /* memtest works on */ | |
| 149 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
| 150 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) | |
| 151 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) | |
| 152 | ||
| a2ac68fb CK |
153 | #define CONFIG_RD_LVL |
| 154 | ||
| 155 | #define CONFIG_NR_DRAM_BANKS 8 | |
| 156 | #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ | |
| 157 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE | |
| 158 | #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE | |
| 159 | #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) | |
| 160 | #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE | |
| 161 | #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) | |
| 162 | #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE | |
| 163 | #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) | |
| 164 | #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE | |
| 165 | #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) | |
| 166 | #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE | |
| 167 | #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) | |
| 168 | #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE | |
| 169 | #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) | |
| 170 | #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE | |
| 171 | #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) | |
| 172 | #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE | |
| 173 | ||
| 174 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 | |
| 175 | ||
| 176 | /* FLASH and environment organization */ | |
| 177 | #define CONFIG_SYS_NO_FLASH | |
| 178 | #undef CONFIG_CMD_IMLS | |
| 179 | #define CONFIG_IDENT_STRING " for ARNDALE" | |
| 180 | ||
| 181 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
| 182 | ||
| 183 | #define CONFIG_ENV_IS_IN_MMC | |
| 184 | #define CONFIG_SECURE_BL1_ONLY | |
| 185 | ||
| 186 | /* Secure FW size configuration */ | |
| 187 | #ifdef CONFIG_SECURE_BL1_ONLY | |
| 188 | #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ | |
| 189 | #else | |
| 190 | #define CONFIG_SEC_FW_SIZE 0 | |
| 191 | #endif | |
| 192 | ||
| 193 | /* Configuration of BL1, BL2, ENV Blocks on mmc */ | |
| 194 | #define CONFIG_RES_BLOCK_SIZE (512) | |
| 195 | #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ | |
| 196 | #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ | |
| 197 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ | |
| 198 | ||
| 199 | #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) | |
| 200 | #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) | |
| 201 | #define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) | |
| 202 | ||
| 203 | /* U-boot copy size from boot Media to DRAM.*/ | |
| 204 | #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) | |
| 205 | #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) | |
| 206 | ||
| a2ac68fb CK |
207 | #define CONFIG_DOS_PARTITION |
| 208 | #define CONFIG_EFI_PARTITION | |
| 209 | #define CONFIG_CMD_PART | |
| 210 | #define CONFIG_PARTITION_UUIDS | |
| 211 | ||
| 212 | ||
| 213 | #define CONFIG_IRAM_STACK 0x02050000 | |
| 214 | ||
| 215 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK | |
| 216 | ||
| 217 | /* I2C */ | |
| 218 | #define CONFIG_SYS_I2C_INIT_BOARD | |
| 2d8f1e27 | 219 | #define CONFIG_SYS_I2C |
| a2ac68fb | 220 | #define CONFIG_CMD_I2C |
| 2d8f1e27 PW |
221 | #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ |
| 222 | #define CONFIG_SYS_I2C_S3C24X0 | |
| a2ac68fb | 223 | #define CONFIG_MAX_I2C_NUM 8 |
| 2d8f1e27 | 224 | #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 |
| a2ac68fb CK |
225 | #define CONFIG_I2C_EDID |
| 226 | ||
| 227 | /* PMIC */ | |
| 228 | #define CONFIG_PMIC | |
| 229 | #define CONFIG_PMIC_I2C | |
| 230 | #define CONFIG_PMIC_MAX77686 | |
| 231 | ||
| 232 | #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale | |
| 233 | ||
| 234 | /* Ethernet Controllor Driver */ | |
| 235 | #ifdef CONFIG_CMD_NET | |
| 236 | #define CONFIG_SMC911X | |
| 237 | #define CONFIG_SMC911X_BASE 0x5000000 | |
| 238 | #define CONFIG_SMC911X_16_BIT | |
| 239 | #define CONFIG_ENV_SROM_BANK 1 | |
| 240 | #endif /*CONFIG_CMD_NET*/ | |
| 241 | ||
| 242 | /* Enable PXE Support */ | |
| 243 | #ifdef CONFIG_CMD_NET | |
| 244 | #define CONFIG_CMD_PXE | |
| 245 | #define CONFIG_MENU | |
| 246 | #endif | |
| 247 | ||
| 248 | /* Enable devicetree support */ | |
| 249 | #define CONFIG_OF_LIBFDT | |
| 250 | ||
| 251 | /* Enable Time Command */ | |
| 252 | #define CONFIG_CMD_TIME | |
| 253 | ||
| 254 | #endif /* __CONFIG_H */ |