[J-u-boot.git] / include / configs / Total5200.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Check valid setting of revision define.
 * Total5100 and Total5200 Rev.1 are identical except for the processor.
 */
#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
#error CONFIG_TOTAL5200_REV must be 1 or 2
#endif

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
#define CONFIG_TOTAL5200	1	/* ... on Total5200 board */

/*
 * Valid values for CONFIG_SYS_TEXT_BASE are:
 * 0xFFF00000	boot high (standard configuration)
 * 0xFE000000	boot low
 * 0x00100000	boot from RAM (for testing only)
 */
#ifndef CONFIG_SYS_TEXT_BASE
#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Video console
 */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SED13806
#define CONFIG_VIDEO_SED13806_16BPP

#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
/* #define CONFIG_VIDEO_BMP_LOGO */
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN


/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_MII		1
#define CONFIG_EEPRO100		1
#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#define CONFIG_NS8382X		1

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI

#define CONFIG_CMD_BMP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB


#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)		/* Boot low */
#   define CONFIG_SYS_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	\
	"setenv stdout serial;setenv stderr serial;" \
	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/MPC5200/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#if CONFIG_TOTAL5200_REV==2
#   define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max num of flash banks */
#   define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START }
#else
#   define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks  */
#   define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
#endif
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#if CONFIG_TOTAL5200_REV==1
#   define CONFIG_SYS_FLASH_BASE	0xFE000000
#   define CONFIG_SYS_FLASH_SIZE	0x02000000
#elif CONFIG_TOTAL5200_REV==2
#   define CONFIG_SYS_FLASH_BASE	0xFA000000
#   define CONFIG_SYS_FLASH_SIZE	0x06000000
#endif /* CONFIG_TOTAL5200_REV */

#if defined(CONFIG_SYS_LOWBOOT)
#   define CONFIG_ENV_ADDR		0xFE040000
#else	/* CONFIG_SYS_LOWBOOT */
#   define CONFIG_ENV_ADDR		0xFFF40000
#endif	/* CONFIG_SYS_LOWBOOT */

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x40000
#define CONFIG_ENV_SECT_SIZE	0x40000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
#define CONFIG_SYS_MBAR		0xF0000000	/*   64 kB */
#define CONFIG_SYS_FPGA_BASE		0xF0010000	/*   64 kB */
#define CONFIG_SYS_CPLD_BASE		0xF0020000	/*   64 kB */
#define CONFIG_SYS_LCD_BASE		0xF1000000	/* 4096 kB */

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_SEVENWIRE
/* dummy, 7-wire FEC does not have phy address */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 *
 * CS1:   SDRAM CS1 disabled, gpio_wkup_6 enabled                0
 * Reserved                                                      0
 * ALTs:  CAN1/2 on PSC2, SPI on PSC3                            00
 * CS7:   Interrupt GPIO on PSC3_5                               0
 * CS8:   Interrupt GPIO on PSC3_4                               0
 * ATA:   reset default, changed in ATA driver                   00
 * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO       0
 * IRDA:  reset default, changed in IrDA driver                  000
 * ETHER: reset default, changed in Ethernet driver              0000
 * PCI_DIS: reset default, changed in PCI driver                 0
 * USB_SE: reset default, changed in USB driver                  0
 * USB:   reset default, changed in USB driver                   00
 * PSC3:  SPI and UART functionality without CD                  1100
 * Reserved                                                      0
 * PSC2:  CAN1/2                                                 001
 * Reserved                                                      0
 * PSC1:  reset default, changed in AC'97 driver                 000
 *
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x00000C10

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif


/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#if CONFIG_TOTAL5200_REV==1
#   define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#   define CONFIG_SYS_BOOTCS_SIZE	0x02000000	/* 32 MB */
#   define CONFIG_SYS_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
#   define CONFIG_SYS_CS0_START	CONFIG_SYS_FLASH_BASE
#   define CONFIG_SYS_CS0_SIZE		0x02000000	/* 32 MB */
#else
#   define CONFIG_SYS_BOOTCS_START	(CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE)
#   define CONFIG_SYS_BOOTCS_SIZE	0x02000000	/* 32 MB */
#   define CONFIG_SYS_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
#   define CONFIG_SYS_CS4_START	(CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE)
#   define CONFIG_SYS_CS4_SIZE		0x02000000	/* 32 MB */
#   define CONFIG_SYS_CS4_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
#   define CONFIG_SYS_CS5_START	CONFIG_SYS_FLASH_BASE
#   define CONFIG_SYS_CS5_SIZE		0x02000000	/* 32 MB */
#   define CONFIG_SYS_CS5_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
#endif

#define CONFIG_SYS_CS1_START		CONFIG_SYS_FPGA_BASE
#define CONFIG_SYS_CS1_SIZE		0x00010000	/* 64 kB */
#define CONFIG_SYS_CS1_CFG		0x0019FF00	/* 25WS, MX, AL, AA, CE, AS_25, DS_32 */

#define CONFIG_SYS_CS2_START		CONFIG_SYS_LCD_BASE
#define CONFIG_SYS_CS2_SIZE		0x00400000	/* 4096 kB */
#define CONFIG_SYS_CS2_CFG		0x0032FD0C	/* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */

#if CONFIG_TOTAL5200_REV==1
#   define CONFIG_SYS_CS3_START	CONFIG_SYS_CPLD_BASE
#   define CONFIG_SYS_CS3_SIZE		0x00010000	/* 64 kB */
#   define CONFIG_SYS_CS3_CFG		0x000ADF00	/* 10WS, MX, AL, CE, AS_25, DS_32 */
#else
#   define CONFIG_SYS_CS3_START	CONFIG_SYS_CPLD_BASE
#   define CONFIG_SYS_CS3_SIZE		0x00010000	/* 64 kB */
#   define CONFIG_SYS_CS3_CFG		0x000AD800	/* 10WS, MX, AL, CE, AS_24, DS_8 */
#endif

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_ATA_CS_ON_I2C2
#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CONFIG_SYS_ATA_STRIDE          4

#endif /* __CONFIG_H */
Commit	Line	Data
6c7a1408 WD	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, [email protected].
	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
6c7a1408 WD	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* Check valid setting of revision define.
	16	* Total5100 and Total5200 Rev.1 are identical except for the processor.
	17	*/
	18	#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
	19	#error CONFIG_TOTAL5200_REV must be 1 or 2
	20	#endif
	21
	22	/*
	23	* High Level Configuration Options
	24	* (easy to change)
	25	*/
	26
b2a6dfe4	27	#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
6c7a1408 WD	28	#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
6c7a1408 WD	29
2ae18241 WD	30	/*
	31	* Valid values for CONFIG_SYS_TEXT_BASE are:
	32	* 0xFFF00000 boot high (standard configuration)
	33	* 0xFE000000 boot low
	34	* 0x00100000 boot from RAM (for testing only)
	35	*/
	36	#ifndef CONFIG_SYS_TEXT_BASE
	37	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
	38	#endif
	39
6d0f6bcf	40	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
6c7a1408	41
31d82672 BB	42	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	43
6c7a1408 WD	44	/*
	45	* Serial console configuration
	46	*/
	47	#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
	48	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	49	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
6c7a1408	50
81050926 WD	51	/*
	52	* Video console
	53	*/
281e00a3	54	#define CONFIG_VIDEO
81050926 WD	55	#define CONFIG_VIDEO_SED13806
	56	#define CONFIG_VIDEO_SED13806_16BPP
	57
	58	#define CONFIG_CFB_CONSOLE
	59	#define CONFIG_VIDEO_LOGO
	60	/* #define CONFIG_VIDEO_BMP_LOGO */
	61	#define CONFIG_CONSOLE_EXTRA_INFO
	62	#define CONFIG_VGA_AS_SINGLE_DEVICE
	63	#define CONFIG_VIDEO_SW_CURSOR
	64	#define CONFIG_SPLASH_SCREEN
	65
6c7a1408	66
6c7a1408 WD	67	/*
	68	* PCI Mapping:
	69	* 0x40000000 - 0x4fffffff - PCI Memory
	70	* 0x50000000 - 0x50ffffff - PCI IO Space
	71	*/
	72	#define CONFIG_PCI 1
	73	#define CONFIG_PCI_PNP 1
	74	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	75	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
6c7a1408 WD	76
	77	#define CONFIG_PCI_MEM_BUS 0x40000000
	78	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	79	#define CONFIG_PCI_MEM_SIZE 0x10000000
	80
	81	#define CONFIG_PCI_IO_BUS 0x50000000
	82	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	83	#define CONFIG_PCI_IO_SIZE 0x01000000
	84
63ff004c	85	#define CONFIG_MII 1
6c7a1408	86	#define CONFIG_EEPRO100 1
6d0f6bcf	87	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
6c7a1408 WD	88	#define CONFIG_NS8382X 1
6c7a1408 WD	89
6c7a1408 WD	90	/* Partitions */
	91	#define CONFIG_MAC_PARTITION
	92	#define CONFIG_DOS_PARTITION
	93
	94	/* USB */
6c7a1408	95	#define CONFIG_USB_OHCI
6c7a1408	96	#define CONFIG_USB_STORAGE
d794cfef	97
6c7a1408	98
a1aa0bb5 JL	99	/*
	100	* BOOTP options
	101	*/
	102	#define CONFIG_BOOTP_BOOTFILESIZE
	103	#define CONFIG_BOOTP_BOOTPATH
	104	#define CONFIG_BOOTP_GATEWAY
	105	#define CONFIG_BOOTP_HOSTNAME
	106
	107
6c7a1408	108	/*
d794cfef	109	* Command line configuration.
6c7a1408	110	*/
d794cfef JL	111	#include <config_cmd_default.h>
d794cfef JL	112
fd428c05	113	#define CONFIG_CMD_PCI
d794cfef JL	114
	115	#define CONFIG_CMD_BMP
	116	#define CONFIG_CMD_EEPROM
	117	#define CONFIG_CMD_FAT
	118	#define CONFIG_CMD_I2C
	119	#define CONFIG_CMD_IDE
	120	#define CONFIG_CMD_PING
	121	#define CONFIG_CMD_USB
	122
6c7a1408	123
14d0a02a	124	#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
6d0f6bcf	125	# define CONFIG_SYS_LOWBOOT 1
6c7a1408 WD	126	#endif
	127
	128	/*
	129	* Autobooting
	130	*/
	131	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	132
81050926 WD	133	#define CONFIG_PREBOOT \
	134	"setenv stdout serial;setenv stderr serial;" \
	135	"echo;" \
32bf3d14	136	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
6c7a1408 WD	137	"echo"
	138
	139	#undef CONFIG_BOOTARGS
	140
	141	#define CONFIG_EXTRA_ENV_SETTINGS \
	142	"netdev=eth0\0" \
	143	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	144	"nfsroot=${serverip}:${rootpath}\0" \
6c7a1408	145	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	146	"addip=setenv bootargs ${bootargs} " \
	147	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	148	":${hostname}:${netdev}:off panic=1\0" \
6c7a1408	149	"flash_nfs=run nfsargs addip;" \
fe126d8b	150	"bootm ${kernel_addr}\0" \
6c7a1408	151	"flash_self=run ramargs addip;" \
fe126d8b WD	152	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	153	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
6c7a1408 WD	154	"rootpath=/opt/eldk/ppc_82xx\0" \
	155	"bootfile=/tftpboot/MPC5200/uImage\0" \
	156	""
	157
	158	#define CONFIG_BOOTCOMMAND "run flash_self"
	159
6c7a1408 WD	160	/*
	161	* IPB Bus clocking configuration.
	162	*/
6d0f6bcf	163	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
6c7a1408 WD	164
	165	/*
	166	* I2C configuration
	167	*/
	168	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	169	#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
6c7a1408	170
6d0f6bcf JCPV	171	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	172	#define CONFIG_SYS_I2C_SLAVE 0x7F
6c7a1408 WD	173
	174	/*
	175	* EEPROM configuration
	176	*/
6d0f6bcf JCPV	177	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	178	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	179	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	180	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
6c7a1408 WD	181
	182	/*
	183	* Flash configuration
	184	*/
6d0f6bcf	185	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	186	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6c7a1408	187	#if CONFIG_TOTAL5200_REV==2
6d0f6bcf JCPV	188	# define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
6d0f6bcf JCPV	189	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START }
6c7a1408	190	#else
6d0f6bcf JCPV	191	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
6d0f6bcf JCPV	192	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
6c7a1408	193	#endif
6d0f6bcf JCPV	194	#define CONFIG_SYS_FLASH_EMPTY_INFO
6d0f6bcf JCPV	195	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
6c7a1408 WD	196
6c7a1408 WD	197	#if CONFIG_TOTAL5200_REV==1
6d0f6bcf JCPV	198	# define CONFIG_SYS_FLASH_BASE 0xFE000000
6d0f6bcf JCPV	199	# define CONFIG_SYS_FLASH_SIZE 0x02000000
6c7a1408	200	#elif CONFIG_TOTAL5200_REV==2
6d0f6bcf JCPV	201	# define CONFIG_SYS_FLASH_BASE 0xFA000000
6d0f6bcf JCPV	202	# define CONFIG_SYS_FLASH_SIZE 0x06000000
6c7a1408 WD	203	#endif /* CONFIG_TOTAL5200_REV */
6c7a1408 WD	204
6d0f6bcf	205	#if defined(CONFIG_SYS_LOWBOOT)
0e8d1586	206	# define CONFIG_ENV_ADDR 0xFE040000
6d0f6bcf	207	#else /* CONFIG_SYS_LOWBOOT */
0e8d1586	208	# define CONFIG_ENV_ADDR 0xFFF40000
6d0f6bcf	209	#endif /* CONFIG_SYS_LOWBOOT */
6c7a1408 WD	210
	211	/*
	212	* Environment settings
	213	*/
5a1aceb0	214	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	215	#define CONFIG_ENV_SIZE 0x40000
0e8d1586 JCPV	216	#define CONFIG_ENV_SECT_SIZE 0x40000
6c7a1408 WD	217	#define CONFIG_ENV_OVERWRITE 1
	218
	219	/*
	220	* Memory map
	221	*/
6d0f6bcf JCPV	222	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	223	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
	224	#define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */
	225	#define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */
	226	#define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */
	227	#define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */
6c7a1408 WD	228
6c7a1408 WD	229	/* Use SRAM until RAM will be available */
6d0f6bcf	230	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	231	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
6c7a1408	232
25ddd1fb	233	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	234	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
6c7a1408	235
14d0a02a	236	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	237	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	238	# define CONFIG_SYS_RAMBOOT 1
6c7a1408 WD	239	#endif
6c7a1408 WD	240
6d0f6bcf JCPV	241	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	242	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	243	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
6c7a1408 WD	244
	245	/*
	246	* Ethernet configuration
	247	*/
	248	#define CONFIG_MPC5xxx_FEC 1
86321fc1	249	#define CONFIG_MPC5xxx_FEC_SEVENWIRE
6c7a1408 WD	250	/* dummy, 7-wire FEC does not have phy address */
	251	#define CONFIG_PHY_ADDR 0x00
	252
	253	/*
	254	* GPIO configuration
	255	*
	256	* CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0
	257	* Reserved 0
	258	* ALTs: CAN1/2 on PSC2, SPI on PSC3 00
	259	* CS7: Interrupt GPIO on PSC3_5 0
	260	* CS8: Interrupt GPIO on PSC3_4 0
	261	* ATA: reset default, changed in ATA driver 00
	262	* IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0
	263	* IRDA: reset default, changed in IrDA driver 000
	264	* ETHER: reset default, changed in Ethernet driver 0000
	265	* PCI_DIS: reset default, changed in PCI driver 0
	266	* USB_SE: reset default, changed in USB driver 0
	267	* USB: reset default, changed in USB driver 00
	268	* PSC3: SPI and UART functionality without CD 1100
	269	* Reserved 0
	270	* PSC2: CAN1/2 001
	271	* Reserved 0
	272	* PSC1: reset default, changed in AC'97 driver 000
	273	*
	274	*/
6d0f6bcf	275	#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10
6c7a1408 WD	276
	277	/*
	278	* Miscellaneous configurable options
	279	*/
6d0f6bcf	280	#define CONFIG_SYS_LONGHELP /* undef to save memory */
d794cfef	281	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	282	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
6c7a1408	283	#else
6d0f6bcf	284	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
6c7a1408	285	#endif
6d0f6bcf JCPV	286	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	287	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	288	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
6c7a1408	289
6d0f6bcf JCPV	290	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	291	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
6c7a1408	292
6d0f6bcf	293	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6c7a1408	294
6d0f6bcf	295	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
d794cfef	296	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	297	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
d794cfef JL	298	#endif
	299
	300
6c7a1408 WD	301	/*
	302	* Various low-level settings
	303	*/
6d0f6bcf JCPV	304	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	305	#define CONFIG_SYS_HID0_FINAL HID0_ICE
6c7a1408 WD	306
6c7a1408 WD	307	#if CONFIG_TOTAL5200_REV==1
6d0f6bcf JCPV	308	# define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	309	# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
	310	# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
	311	# define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	312	# define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */
6c7a1408	313	#else
6d0f6bcf JCPV	314	# define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE)
	315	# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
	316	# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
	317	# define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE)
	318	# define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */
	319	# define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
	320	# define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE
	321	# define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */
	322	# define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
6c7a1408 WD	323	#endif
6c7a1408 WD	324
6d0f6bcf JCPV	325	#define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE
	326	#define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */
	327	#define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
6c7a1408	328
6d0f6bcf JCPV	329	#define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE
	330	#define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */
	331	#define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
6c7a1408 WD	332
6c7a1408 WD	333	#if CONFIG_TOTAL5200_REV==1
6d0f6bcf JCPV	334	# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
	335	# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
	336	# define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */
6c7a1408	337	#else
6d0f6bcf JCPV	338	# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
	339	# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
	340	# define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */
6c7a1408 WD	341	#endif
6c7a1408 WD	342
6d0f6bcf JCPV	343	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	344	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
6c7a1408 WD	345
	346	/*-----------------------------------------------------------------------
	347	* USB stuff
	348	*-----------------------------------------------------------------------
	349	*/
	350	#define CONFIG_USB_CLOCK 0x0001BBBB
	351	#define CONFIG_USB_CONFIG 0x00001000
	352
	353	/*-----------------------------------------------------------------------
	354	* IDE/ATA stuff Supports IDE harddisk
	355	*-----------------------------------------------------------------------
	356	*/
	357
	358	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	359
	360	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	361	#undef CONFIG_IDE_LED /* LED for ide not supported */
	362
	363	#define CONFIG_IDE_RESET /* reset for ide supported */
	364	#define CONFIG_IDE_PREINIT
	365
6a397ef0	366	#define CONFIG_SYS_ATA_CS_ON_I2C2
6d0f6bcf JCPV	367	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	368	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
6c7a1408	369
6d0f6bcf	370	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
6c7a1408	371
6d0f6bcf	372	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
6c7a1408 WD	373
6c7a1408 WD	374	/* Offset for data I/O */
6d0f6bcf	375	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
6c7a1408 WD	376
6c7a1408 WD	377	/* Offset for normal register accesses */
6d0f6bcf	378	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
6c7a1408 WD	379
6c7a1408 WD	380	/* Offset for alternate registers */
6d0f6bcf	381	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
6c7a1408 WD	382
6c7a1408 WD	383	/* Interval between registers */
6d0f6bcf	384	#define CONFIG_SYS_ATA_STRIDE 4
6c7a1408 WD	385
6c7a1408 WD	386	#endif /* __CONFIG_H */