[J-u-boot.git] / include / configs / P5020DS.h

/*
 * Copyright 2009-2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * P5020 DS board configuration file
 * Also supports P5010 DS
 */
#define CONFIG_P5020DS
#define CONFIG_PHYS_64BIT
#define CONFIG_PPC_P5020

#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */

#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_SYS_DPAA_RMAN

#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1			/* SRIO port 1 */
#define CONFIG_SRIO2			/* SRIO port 2 */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */

#include "corenet_ds.h"
Commit	Line	Data
e02aea61 KG	1	/*
	2	* Copyright 2009-2011 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
e02aea61 KG	5	*/
	6
	7	/*
	8	* P5020 DS board configuration file
3e978f5d	9	* Also supports P5010 DS
e02aea61 KG	10	*/
	11	#define CONFIG_P5020DS
	12	#define CONFIG_PHYS_64BIT
	13	#define CONFIG_PPC_P5020
	14
c6d33901 KG	15	#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
	16
	17	#define CONFIG_MMC
	18	#define CONFIG_NAND_FSL_ELBC
9760b274	19	#define CONFIG_FSL_SATA_V2
c6d33901	20	#define CONFIG_PCIE3
e02aea61	21	#define CONFIG_PCIE4
6b3a8d00	22	#define CONFIG_SYS_FSL_RAID_ENGINE
4d28db8a	23	#define CONFIG_SYS_DPAA_RMAN
e02aea61	24
11860d88 TT	25	#define CONFIG_SYS_SRIO
	26	#define CONFIG_SRIO1 /* SRIO port 1 */
	27	#define CONFIG_SRIO2 /* SRIO port 2 */
c8b28152	28	#define CONFIG_SRIO_PCIE_BOOT_MASTER
e02aea61 KG	29	#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
	30
	31	#include "corenet_ds.h"