[J-u-boot.git] / include / configs / KAREF.h

/*
 * (C) Copyright 2004 Sandburst Corporation
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/************************************************************************
 * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
 *		    design.
 ***********************************************************************/

/*
 * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
 *
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_KAREF	     1		/* Board is Kamino Ref Variant */
#define CONFIG_440GX		  1	     /* Specifc GX support	*/
#define CONFIG_440		  1	     /* ... PPC440 family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
#define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
#define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFF80000

#undef	CONFIG_SYS_DRAM_TEST			     /* Disable-takes long time!*/
#define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/

#define CONFIG_VERY_BIG_RAM 1
#define CONFIG_VERSION_VARIABLE

#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
#define CONFIG_SYS_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
#define CONFIG_SYS_MONITOR_BASE       0xfff80000    /* start of monitor	*/
#define CONFIG_SYS_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
#define CONFIG_SYS_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
#define CONFIG_SYS_PCI_BASE	       0xd0000000    /* internal PCI regs	*/

#define CONFIG_SYS_NVRAM_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
#define CONFIG_SYS_KAREF_FPGA_BASE   (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
#define CONFIG_SYS_OFEM_FPGA_BASE    (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
#define CONFIG_SYS_BME32_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
#define CONFIG_SYS_GPIO_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)

/* Here for completeness */
#define CONFIG_SYS_OFEMAC_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_TEMP_STACK_OCM    1
#define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_SIZE      0x2000	     /* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

#define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
#define CONFIG_SYS_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#define CONFIG_BAUDRATE	      9600

#define CONFIG_SYS_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * NVRAM/RTC
 *
 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
 * The DS1743 code assumes this condition (i.e. -- it assumes the base
 * address for the RTC registers is:
 *
 *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
 *
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
#define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_FLASH_BANKS   1		     /* number of banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT    8		     /* sectors per device	*/

#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
#define CONFIG_SYS_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM     1		     /* Use SPD EEPROM for setup*/
#define SPD_EEPROM_ADDRESS    {0x53}	     /* SPD i2c spd addresses	*/

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_PPC4XX_CH1
#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#define CONFIG_ENV_IS_IN_NVRAM   1		     /* Environment uses NVRAM	*/
#undef	CONFIG_ENV_IS_IN_FLASH		     /* ... not in flash	*/
#undef	CONFIG_ENV_IS_IN_EEPROM		     /* ... not in EEPROM	*/
#define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/

#define CONFIG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
#define CONFIG_ENV_ADDR	      (CONFIG_SYS_NVRAM_BASE_ADDR)

#define CONFIG_BOOTDELAY      5		    /* 5 second autoboot */

#define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/

/*-----------------------------------------------------------------------
 * Networking
 *----------------------------------------------------------------------*/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII	      1		     /* MII PHY management	*/
#define CONFIG_PHY_ADDR	      0xff	     /* no phy on EMAC0		*/
#define CONFIG_PHY1_ADDR      0xff	     /* no phy on EMAC1		*/
#define CONFIG_PHY2_ADDR      0x08	     /* PHY addr, MGMT, EMAC2	*/
#define CONFIG_PHY3_ADDR      0x18	     /* PHY addr, LCL, EMAC3	*/
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_PHY_RESET      1              /* reset phy upon startup  */
#define CONFIG_CIS8201_PHY    1		     /* RGMII mode for Cicada	*/
#define CONFIG_CIS8201_SHORT_ETCH 1	     /* Use short etch mode	*/
#define CONFIG_PHY_GIGE	      1		     /* GbE speed/duplex detect */
#define CONFIG_PHY_RESET_DELAY 1000
#define CONFIG_NETMASK	      255.255.0.0
#define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
#define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
#define CONFIG_SYS_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_PING
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT


/* Include NetConsole support */
#define CONFIG_NETCONSOLE

/* Include auto complete with tabs */
#define CONFIG_AUTO_COMPLETE 1
#define CONFIG_SYS_ALT_MEMTEST	     1	     /* use real memory test	 */

#define CONFIG_SYS_LONGHELP			     /* undef to save memory	*/
#define CONFIG_SYS_PROMPT	      "KaRefDes=> "  /* Monitor Command Prompt	*/

#define CONFIG_SYS_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/


/*-----------------------------------------------------------------------
 * Console Buffer
 *----------------------------------------------------------------------*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	      1024	     /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	      256	     /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
					     /* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS	      16	     /* max number of cmd args	*/
#define CONFIG_SYS_BARGSIZE	      CONFIG_SYS_CBSIZE     /* Boot Arg Buffer Size	*/

/*-----------------------------------------------------------------------
 * Memory Test
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MEMTEST_START     0x0400000	     /* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/

/*-----------------------------------------------------------------------
 * Compact Flash (in true IDE mode)
 *----------------------------------------------------------------------*/
#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/

#define CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CONFIG_SYS_ATA_BASE_ADDR	0xF0000000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */

#define CONFIG_SYS_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
					    to get to the correct offset */
#define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/

/*-----------------------------------------------------------------------
 * PCI
 *----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI			     /* include pci support	*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
#define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
#define CONFIG_SYS_PCI_TARGBASE      (CONFIG_SYS_PCI_MEMBASE)

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT		     /* let board init pci target*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE  230400	     /* kgdb serial port baud	*/
#endif

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 *----------------------------------------------------------------------*/
#undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
#define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
#define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */

#endif	/* __CONFIG_H */
Commit	Line	Data
b79316f2 SR	1	/*
	2	* (C) Copyright 2004 Sandburst Corporation
	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
b79316f2 SR	5	*/
	6
	7	/************************************************************************
	8	* KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
3d078ce6	9	* design.
b79316f2 SR	10	***********************************************************************/
	11
	12	/*
	13	* $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
	14	*
	15	*/
	16
	17	#ifndef __CONFIG_H
	18	#define __CONFIG_H
	19
	20	/*-----------------------------------------------------------------------
	21	* High Level Configuration Options
	22	----------------------------------------------------------------------/
3d078ce6 WD	23	#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
3d078ce6 WD	24	#define CONFIG_440GX 1 /* Specifc GX support */
efa35cf1	25	#define CONFIG_440 1 /* ... PPC440 family */
b79316f2	26	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
3d078ce6 WD	27	#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
3d078ce6 WD	28	#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
2ae18241 WD	29
	30	#define CONFIG_SYS_TEXT_BASE 0xFFF80000
	31
6d0f6bcf	32	#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/
3d078ce6	33	#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
b79316f2 SR	34
	35	#define CONFIG_VERY_BIG_RAM 1
	36	#define CONFIG_VERSION_VARIABLE
	37
	38	#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
	39
	40	/*-----------------------------------------------------------------------
	41	* Base addresses -- Note these are effective addresses where the
	42	* actual resources get mapped (not physical addresses)
	43	----------------------------------------------------------------------/
6d0f6bcf JCPV	44	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	45	#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
	46	#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */
	47	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
6d0f6bcf JCPV	48	#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
	49	#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
	50
	51	#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
	52	#define CONFIG_SYS_KAREF_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
	53	#define CONFIG_SYS_OFEM_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
	54	#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
	55	#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
b79316f2 SR	56
b79316f2 SR	57	/* Here for completeness */
6d0f6bcf	58	#define CONFIG_SYS_OFEMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)
b79316f2 SR	59
	60	/*-----------------------------------------------------------------------
	61	* Initial RAM & stack pointer (placed in internal SRAM)
	62	----------------------------------------------------------------------/
6d0f6bcf JCPV	63	#define CONFIG_SYS_TEMP_STACK_OCM 1
	64	#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
	65	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
553f0982	66	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
b79316f2	67
25ddd1fb	68	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
800eb096	69	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
b79316f2	70
6d0f6bcf JCPV	71	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
6d0f6bcf JCPV	72	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
b79316f2 SR	73
	74	/*-----------------------------------------------------------------------
	75	* Serial Port
	76	----------------------------------------------------------------------/
550650dd SR	77	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	78	#define CONFIG_SYS_NS16550
	79	#define CONFIG_SYS_NS16550_SERIAL
	80	#define CONFIG_SYS_NS16550_REG_SIZE 1
	81	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
b79316f2 SR	82	#define CONFIG_BAUDRATE 9600
b79316f2 SR	83
6d0f6bcf	84	#define CONFIG_SYS_BAUDRATE_TABLE \
b79316f2 SR	85	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	86
	87	/*-----------------------------------------------------------------------
	88	* NVRAM/RTC
	89	*
	90	* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
	91	* The DS1743 code assumes this condition (i.e. -- it assumes the base
	92	* address for the RTC registers is:
	93	*
6d0f6bcf	94	* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
b79316f2 SR	95	*
b79316f2 SR	96	----------------------------------------------------------------------/
6d0f6bcf	97	#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
3d078ce6	98	#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
b79316f2 SR	99
	100	/*-----------------------------------------------------------------------
	101	* FLASH related
	102	----------------------------------------------------------------------/
6d0f6bcf JCPV	103	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
6d0f6bcf JCPV	104	#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
b79316f2	105
6d0f6bcf JCPV	106	#undef CONFIG_SYS_FLASH_CHECKSUM
	107	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
	108	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
b79316f2 SR	109
	110	/*-----------------------------------------------------------------------
	111	* DDR SDRAM
	112	----------------------------------------------------------------------/
3d078ce6 WD	113	#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
3d078ce6 WD	114	#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
b79316f2 SR	115
	116	/*-----------------------------------------------------------------------
	117	* I2C
	118	----------------------------------------------------------------------/
880540de DE	119	#define CONFIG_SYS_I2C
	120	#define CONFIG_SYS_I2C_PPC4XX
	121	#define CONFIG_SYS_I2C_PPC4XX_CH0
	122	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	123	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
	124	#define CONFIG_SYS_I2C_PPC4XX_CH1
	125	#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
	126	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
	127	#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
b79316f2 SR	128
	129	/*-----------------------------------------------------------------------
	130	* Environment
	131	----------------------------------------------------------------------/
9314cee6	132	#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
5a1aceb0	133	#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */
bb1f8b4f	134	#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
3d078ce6	135	#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
b79316f2	136
0e8d1586	137	#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */
6d0f6bcf	138	#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR)
b79316f2	139
3d078ce6	140	#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
b79316f2	141
3d078ce6	142	#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
6d0f6bcf	143	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
b79316f2 SR	144
	145	/*-----------------------------------------------------------------------
	146	* Networking
	147	----------------------------------------------------------------------/
96e21f86	148	#define CONFIG_PPC4xx_EMAC
3d078ce6	149	#define CONFIG_MII 1 /* MII PHY management */
3d078ce6 WD	150	#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
	151	#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
	152	#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
	153	#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
b79316f2 SR	154	#define CONFIG_HAS_ETH0
	155	#define CONFIG_HAS_ETH1
	156	#define CONFIG_HAS_ETH2
	157	#define CONFIG_HAS_ETH3
d6c61aab	158	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
3d078ce6 WD	159	#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
	160	#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
	161	#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
b79316f2	162	#define CONFIG_PHY_RESET_DELAY 1000
3d078ce6 WD	163	#define CONFIG_NETMASK 255.255.0.0
	164	#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
	165	#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
6d0f6bcf	166	#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
b79316f2 SR	167
b79316f2 SR	168
659e2f67 JL	169	/*
	170	* BOOTP options
	171	*/
	172	#define CONFIG_BOOTP_BOOTFILESIZE
	173	#define CONFIG_BOOTP_BOOTPATH
	174	#define CONFIG_BOOTP_GATEWAY
	175	#define CONFIG_BOOTP_HOSTNAME
	176
	177
348f258f JL	178	/*
	179	* Command line configuration.
	180	*/
	181	#include <config_cmd_default.h>
	182
	183	#define CONFIG_CMD_PCI
	184	#define CONFIG_CMD_IRQ
	185	#define CONFIG_CMD_I2C
	186	#define CONFIG_CMD_DHCP
	187	#define CONFIG_CMD_DATE
	188	#define CONFIG_CMD_BEDBUG
	189	#define CONFIG_CMD_PING
	190	#define CONFIG_CMD_DIAG
	191	#define CONFIG_CMD_MII
	192	#define CONFIG_CMD_NET
	193	#define CONFIG_CMD_ELF
	194	#define CONFIG_CMD_IDE
	195	#define CONFIG_CMD_FAT
	196
b79316f2 SR	197
	198	/* Include NetConsole support */
	199	#define CONFIG_NETCONSOLE
	200
	201	/* Include auto complete with tabs */
	202	#define CONFIG_AUTO_COMPLETE 1
6d0f6bcf	203	#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
b79316f2	204
6d0f6bcf JCPV	205	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	206	#define CONFIG_SYS_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
b79316f2	207
6d0f6bcf	208	#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */
b79316f2 SR	209
	210
	211	/*-----------------------------------------------------------------------
	212	* Console Buffer
	213	----------------------------------------------------------------------/
348f258f	214	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	215	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
b79316f2	216	#else
6d0f6bcf	217	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
b79316f2	218	#endif
6d0f6bcf	219	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
3d078ce6	220	/* Print Buffer Size */
6d0f6bcf JCPV	221	#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
6d0f6bcf JCPV	222	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
b79316f2 SR	223
	224	/*-----------------------------------------------------------------------
	225	* Memory Test
	226	----------------------------------------------------------------------/
6d0f6bcf JCPV	227	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	228	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
b79316f2 SR	229
	230	/*-----------------------------------------------------------------------
	231	* Compact Flash (in true IDE mode)
	232	----------------------------------------------------------------------/
	233	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	234	#undef CONFIG_IDE_LED /* no led for ide supported */
	235
3d078ce6	236	#define CONFIG_IDE_RESET /* reset for ide supported */
6d0f6bcf JCPV	237	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
6d0f6bcf JCPV	238	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS1) / max. 1 drives per IDE bus */
b79316f2	239
6d0f6bcf JCPV	240	#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000
	241	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	242	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
	243	#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
	244	#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
b79316f2	245
6d0f6bcf	246	#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride
3d078ce6 WD	247	to get to the correct offset */
3d078ce6 WD	248	#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
b79316f2 SR	249
	250	/*-----------------------------------------------------------------------
	251	* PCI
	252	----------------------------------------------------------------------/
	253	/* General PCI */
3d078ce6	254	#define CONFIG_PCI /* include pci support */
842033e6	255	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
3d078ce6 WD	256	#define CONFIG_PCI_PNP /* do pci plug-and-play */
3d078ce6 WD	257	#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
6d0f6bcf	258	#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE)
b79316f2 SR	259
b79316f2 SR	260	/* Board-specific PCI */
6d0f6bcf	261	#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/
b79316f2	262
6d0f6bcf JCPV	263	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
6d0f6bcf JCPV	264	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
b79316f2 SR	265
	266	/*
	267	* For booting Linux, the board info and command line data
	268	* have to be in the first 8 MB of memory, since this is
	269	* the maximum mapped by the Linux kernel during initialization.
	270	*/
6d0f6bcf	271	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
b79316f2	272
348f258f	273	#if defined(CONFIG_CMD_KGDB)
3d078ce6	274	#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
b79316f2 SR	275	#endif
	276
	277	/*-----------------------------------------------------------------------
	278	* Miscellaneous configurable options
	279	----------------------------------------------------------------------/
3d078ce6	280	#undef CONFIG_WATCHDOG /* watchdog disabled */
6d0f6bcf JCPV	281	#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */
6d0f6bcf JCPV	282	#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */
b79316f2	283
b79316f2	284	#endif /* __CONFIG_H */