[J-u-boot.git] / board / cds / mpc8548cds / mpc8548cds.c

/*
 * Copyright 2004, 2007 Freescale Semiconductor.
 *
 * (C) Copyright 2002 Scott McNutt <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <spd.h>
#include <miiphy.h>

#include "../common/cadmus.h"
#include "../common/eeprom.h"
#include "../common/via.h"

#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif

DECLARE_GLOBAL_DATA_PTR;

extern long int spd_sdram(void);

void local_bus_init(void);
void sdram_init(void);

int board_early_init_f (void)
{
	return 0;
}

int checkboard (void)
{
	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;

	/* PCI slot in USER bits CSR[6:7] by convention. */
	uint pci_slot = get_pci_slot ();

	uint cpu_board_rev = get_cpu_board_revision ();

	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
		get_board_version (), pci_slot);

	printf ("CPU Board Revision %d.%d (0x%04x)\n",
		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	/*
	 * Fix CPU2 errata: A core hang possible while executing a
	 * msync instruction and a snoopable transaction from an I/O
	 * master tagged to make quick forward progress is present.
	 */
	ecm->eebpcr |= (1 << 16);

	/*
	 * Hack TSEC 3 and 4 IO voltages.
	 */
	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */

	ecm->eedr = 0xffffffff;		/* clear ecm errors */
	ecm->eeer = 0xffffffff;		/* enable ecm errors */
	return 0;
}

long int
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

#if defined(CONFIG_DDR_DLL)
	{
		/*
		 * Work around to stabilize DDR DLL MSYNC_IN.
		 * Errata DDR9 seems to have been fixed.
		 * This is now the workaround for Errata DDR11:
		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
		 */

		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);

		gur->ddrdllcr = 0x81000000;
		asm("sync;isync;msync");
		udelay(200);
	}
#endif
	dram_size = spd_sdram();

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif
	/*
	 * SDRAM Initialization
	 */
	sdram_init();

	puts("    DDR: ");
	return dram_size;
}

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = &immap->im_lbc;

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);
	clkdiv = (lbc->lcrr & 0x0f) * 2;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	gur->lbiuiplldcr1 = 0x00078080;
	if (clkdiv == 16) {
		gur->lbiuiplldcr0 = 0x7c0f1bf0;
	} else if (clkdiv == 8) {
		gur->lbiuiplldcr0 = 0x6c0f1bf0;
	} else if (clkdiv == 4) {
		gur->lbiuiplldcr0 = 0x5c0f1bf0;
	}

	lbc->lcrr |= 0x00030000;

	asm("sync;isync;msync");

	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
}

/*
 * Initialize SDRAM memory on the Local Bus.
 */
void
sdram_init(void)
{
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)

	uint idx;
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
	uint cpu_board_rev;
	uint lsdmr_common;

	puts("    SDRAM: ");

	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	lbc->or2 = CFG_OR2_PRELIM;
	asm("msync");

	lbc->br2 = CFG_BR2_PRELIM;
	asm("msync");

	lbc->lbcr = CFG_LBC_LBCR;
	asm("msync");


	lbc->lsrt = CFG_LBC_LSRT;
	lbc->mrtpr = CFG_LBC_MRTPR;
	asm("msync");

	/*
	 * MPC8548 uses "new" 15-16 style addressing.
	 */
	cpu_board_rev = get_cpu_board_revision();
	lsdmr_common = CFG_LBC_LSDMR_COMMON;
	lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;

	/*
	 * Issue PRECHARGE ALL command.
	 */
	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue 8 AUTO REFRESH commands.
	 */
	for (idx = 0; idx < 8; idx++) {
		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
		asm("sync;msync");
		*sdram_addr = 0xff;
		ppcDcbf((unsigned long) sdram_addr);
		udelay(100);
	}

	/*
	 * Issue 8 MODE-set command.
	 */
	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue NORMAL OP command.
	 */
	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(200);    /* Overkill. Must wait > 200 bus cycles */

#endif	/* enable SDRAM init */
}

#if defined(CFG_DRAM_TEST)
int
testdram(void)
{
	uint *pstart = (uint *) CFG_MEMTEST_START;
	uint *pend = (uint *) CFG_MEMTEST_END;
	uint *p;

	printf("Testing DRAM from 0x%08x to 0x%08x\n",
	       CFG_MEMTEST_START,
	       CFG_MEMTEST_END);

	printf("DRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test passed.\n");
	return 0;
}
#endif

#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
/* For some reason the Tundra PCI bridge shows up on itself as a
 * different device.  Work around that by refusing to configure it.
 */
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }

static struct pci_config_table pci_mpc85xxcds_config_table[] = {
	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
		mpc85xx_config_via_usbide, {0,0,0}},
	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
		mpc85xx_config_via_usb, {0,0,0}},
	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
		mpc85xx_config_via_usb2, {0,0,0}},
	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
		mpc85xx_config_via_power, {0,0,0}},
	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
		mpc85xx_config_via_ac97, {0,0,0}},
	{},
};

static struct pci_controller pci1_hose = {
	config_table: pci_mpc85xxcds_config_table};
#endif	/* CONFIG_PCI */

#ifdef CONFIG_PCI2
static struct pci_controller pci2_hose;
#endif	/* CONFIG_PCI2 */

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif	/* CONFIG_PCIE1 */

int first_free_busno=0;

void
pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;


#ifdef CONFIG_PCI1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pci1_hose;
	struct pci_config_table *table;

	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */

	uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);

	uint pci_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */

	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
		printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter"
			);


		/* inbound */
		pci_set_region(hose->regions + 0,
			       CFG_PCI_MEMORY_BUS,
			       CFG_PCI_MEMORY_PHYS,
			       CFG_PCI_MEMORY_SIZE,
			       PCI_REGION_MEM | PCI_REGION_MEMORY);


		/* outbound memory */
		pci_set_region(hose->regions + 1,
			       CFG_PCI1_MEM_BASE,
			       CFG_PCI1_MEM_PHYS,
			       CFG_PCI1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(hose->regions + 2,
			       CFG_PCI1_IO_BASE,
			       CFG_PCI1_IO_PHYS,
			       CFG_PCI1_IO_SIZE,
			       PCI_REGION_IO);
		hose->region_count = 3;

		/* relocate config table pointers */
		hose->config_table = \
			(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
		for (table = hose->config_table; table && table->vendor; table++)
			table->config_device += gd->reloc_off;

		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		first_free_busno=hose->last_busno+1;
		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
#ifdef CONFIG_PCIX_CHECK
		if (!(gur->pordevsr & PORDEVSR_PCI)) {
			/* PCI-X init */
			if (CONFIG_SYS_CLK_FREQ < 66000000)
				printf("PCI-X will only work at 66 MHz\n");

			reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
				| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
			pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
		}
#endif
	} else {
		printf ("    PCI: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif

#ifdef CONFIG_PCI2
{
	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
	if (pci_dual) {
		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
			pci2_clk_sel ? "sync" : "async");
	} else {
		printf ("    PCI2: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
#endif /* CONFIG_PCI2 */

#ifdef CONFIG_PCIE1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pcie1_hose;
	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);

	int pcie_configured  = io_sel >= 1;

	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE connected to slot as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);

		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		pci_set_region(hose->regions + 0,
			       CFG_PCI_MEMORY_BUS,
			       CFG_PCI_MEMORY_PHYS,
			       CFG_PCI_MEMORY_SIZE,
			       PCI_REGION_MEM | PCI_REGION_MEMORY);

		/* outbound memory */
		pci_set_region(hose->regions + 1,
			       CFG_PCIE1_MEM_BASE,
			       CFG_PCIE1_MEM_PHYS,
			       CFG_PCIE1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(hose->regions + 2,
			       CFG_PCIE1_IO_BASE,
			       CFG_PCIE1_IO_PHYS,
			       CFG_PCIE1_IO_SIZE,
			       PCI_REGION_IO);

		hose->region_count = 3;

		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);

		first_free_busno=hose->last_busno+1;

	} else {
		printf ("    PCIE: disabled\n");
	}
 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif

}

int last_stage_init(void)
{
	unsigned short temp;

	/* Change the resistors for the PHY */
	/* This is needed to get the RGMII working for the 1.3+
	 * CDS cards */
	if (get_board_version() ==  0x13) {
		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 29, 18);

		miiphy_read(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 30, &temp);

		temp = (temp & 0xf03f);
		temp |= 2 << 9;		/* 36 ohm */
		temp |= 2 << 6;		/* 39 ohm */

		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 30, temp);

		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 29, 3);

		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 30, 0x8000);
	}

	return 0;
}


#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_pci_setup(void *blob, bd_t *bd)
{
	u32 *p;
	int len;


#ifdef CONFIG_PCI1
	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
	if (p != NULL) {
		p[0] = 0;
		p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
		debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
	}
#endif

#ifdef CONFIG_PCIE1
	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
	if (p != NULL) {
		p[0] = 0;
		p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
		debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
	}
#endif
}
#endif
Commit	Line	Data
d9b94f28	1	/*
f2cff6b1	2	* Copyright 2004, 2007 Freescale Semiconductor.
d9b94f28 JL	3	*
	4	* (C) Copyright 2002 Scott McNutt <[email protected]>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <pci.h>
	27	#include <asm/processor.h>
	28	#include <asm/immap_85xx.h>
f2cff6b1	29	#include <asm/immap_fsl_pci.h>
d9b94f28	30	#include <spd.h>
09f3e09e	31	#include <miiphy.h>
d9b94f28 JL	32
	33	#include "../common/cadmus.h"
	34	#include "../common/eeprom.h"
bf1dfffd	35	#include "../common/via.h"
d9b94f28	36
f2cff6b1 ES	37	#if defined(CONFIG_OF_FLAT_TREE)
	38	#include <ft_build.h>
	39	#endif
d9b94f28 JL	40	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	41	extern void ddr_enable_ecc(unsigned int dram_size);
	42	#endif
	43
f2cff6b1 ES	44	DECLARE_GLOBAL_DATA_PTR;
f2cff6b1 ES	45
d9b94f28 JL	46	extern long int spd_sdram(void);
	47
	48	void local_bus_init(void);
	49	void sdram_init(void);
	50
	51	int board_early_init_f (void)
	52	{
	53	return 0;
	54	}
	55
	56	int checkboard (void)
	57	{
	58	volatile immap_t immap = (immap_t ) CFG_CCSRBAR;
f59b55a5	59	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
7337b237	60	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
d9b94f28 JL	61
	62	/* PCI slot in USER bits CSR[6:7] by convention. */
	63	uint pci_slot = get_pci_slot ();
	64
d9b94f28 JL	65	uint cpu_board_rev = get_cpu_board_revision ();
	66
	67	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
	68	get_board_version (), pci_slot);
	69
	70	printf ("CPU Board Revision %d.%d (0x%04x)\n",
	71	MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
	72	MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
d9b94f28 JL	73	/*
	74	* Initialize local bus.
	75	*/
	76	local_bus_init ();
	77
7337b237 ZR	78	/*
	79	* Fix CPU2 errata: A core hang possible while executing a
	80	* msync instruction and a snoopable transaction from an I/O
	81	* master tagged to make quick forward progress is present.
	82	*/
	83	ecm->eebpcr \|= (1 << 16);
d9b94f28 JL	84
	85	/*
	86	* Hack TSEC 3 and 4 IO voltages.
	87	*/
	88	gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
	89
f2cff6b1 ES	90	ecm->eedr = 0xffffffff; /* clear ecm errors */
f2cff6b1 ES	91	ecm->eeer = 0xffffffff; /* enable ecm errors */
d9b94f28 JL	92	return 0;
	93	}
	94
	95	long int
	96	initdram(int board_type)
	97	{
	98	long dram_size = 0;
d9b94f28 JL	99
	100	puts("Initializing\n");
	101
	102	#if defined(CONFIG_DDR_DLL)
	103	{
	104	/*
	105	* Work around to stabilize DDR DLL MSYNC_IN.
	106	* Errata DDR9 seems to have been fixed.
	107	* This is now the workaround for Errata DDR11:
	108	* Override DLL = 1, Course Adj = 1, Tap Select = 0
	109	*/
	110
f59b55a5	111	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
d9b94f28 JL	112
	113	gur->ddrdllcr = 0x81000000;
	114	asm("sync;isync;msync");
	115	udelay(200);
	116	}
	117	#endif
	118	dram_size = spd_sdram();
	119
	120	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	121	/*
	122	* Initialize and enable DDR ECC.
	123	*/
	124	ddr_enable_ecc(dram_size);
	125	#endif
	126	/*
	127	* SDRAM Initialization
	128	*/
	129	sdram_init();
	130
	131	puts(" DDR: ");
	132	return dram_size;
	133	}
	134
	135	/*
	136	* Initialize Local Bus
	137	*/
	138	void
	139	local_bus_init(void)
	140	{
	141	volatile immap_t immap = (immap_t )CFG_IMMR;
f59b55a5	142	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
d9b94f28 JL	143	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
	144
	145	uint clkdiv;
	146	uint lbc_hz;
	147	sys_info_t sysinfo;
	148
	149	get_sys_info(&sysinfo);
	150	clkdiv = (lbc->lcrr & 0x0f) * 2;
	151	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
	152
	153	gur->lbiuiplldcr1 = 0x00078080;
	154	if (clkdiv == 16) {
	155	gur->lbiuiplldcr0 = 0x7c0f1bf0;
	156	} else if (clkdiv == 8) {
	157	gur->lbiuiplldcr0 = 0x6c0f1bf0;
	158	} else if (clkdiv == 4) {
	159	gur->lbiuiplldcr0 = 0x5c0f1bf0;
	160	}
	161
	162	lbc->lcrr \|= 0x00030000;
	163
	164	asm("sync;isync;msync");
f2cff6b1 ES	165
	166	lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	167	lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
d9b94f28 JL	168	}
	169
	170	/*
	171	* Initialize SDRAM memory on the Local Bus.
	172	*/
	173	void
	174	sdram_init(void)
	175	{
	176	#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
	177
	178	uint idx;
	179	volatile immap_t immap = (immap_t )CFG_IMMR;
	180	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
	181	uint sdram_addr = (uint )CFG_LBC_SDRAM_BASE;
	182	uint cpu_board_rev;
	183	uint lsdmr_common;
	184
	185	puts(" SDRAM: ");
	186
	187	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
	188
	189	/*
	190	* Setup SDRAM Base and Option Registers
	191	*/
	192	lbc->or2 = CFG_OR2_PRELIM;
	193	asm("msync");
	194
	195	lbc->br2 = CFG_BR2_PRELIM;
	196	asm("msync");
	197
	198	lbc->lbcr = CFG_LBC_LBCR;
	199	asm("msync");
	200
	201
	202	lbc->lsrt = CFG_LBC_LSRT;
	203	lbc->mrtpr = CFG_LBC_MRTPR;
	204	asm("msync");
	205
	206	/*
	207	* MPC8548 uses "new" 15-16 style addressing.
	208	*/
	209	cpu_board_rev = get_cpu_board_revision();
	210	lsdmr_common = CFG_LBC_LSDMR_COMMON;
	211	lsdmr_common \|= CFG_LBC_LSDMR_BSMA1516;
	212
	213	/*
	214	* Issue PRECHARGE ALL command.
	215	*/
	216	lbc->lsdmr = lsdmr_common \| CFG_LBC_LSDMR_OP_PCHALL;
	217	asm("sync;msync");
	218	*sdram_addr = 0xff;
	219	ppcDcbf((unsigned long) sdram_addr);
	220	udelay(100);
	221
	222	/*
	223	* Issue 8 AUTO REFRESH commands.
	224	*/
	225	for (idx = 0; idx < 8; idx++) {
	226	lbc->lsdmr = lsdmr_common \| CFG_LBC_LSDMR_OP_ARFRSH;
	227	asm("sync;msync");
	228	*sdram_addr = 0xff;
	229	ppcDcbf((unsigned long) sdram_addr);
	230	udelay(100);
	231	}
232
233	/*
234	* Issue 8 MODE-set command.
235	*/
236	lbc->lsdmr = lsdmr_common \| CFG_LBC_LSDMR_OP_MRW;
237	asm("sync;msync");
238	*sdram_addr = 0xff;
239	ppcDcbf((unsigned long) sdram_addr);
240	udelay(100);
241
242	/*
243	* Issue NORMAL OP command.
244	*/
245	lbc->lsdmr = lsdmr_common \| CFG_LBC_LSDMR_OP_NORMAL;
246	asm("sync;msync");
247	*sdram_addr = 0xff;
248	ppcDcbf((unsigned long) sdram_addr);
249	udelay(200); /* Overkill. Must wait > 200 bus cycles */
250
251	#endif /* enable SDRAM init */
252	}
253
254	#if defined(CFG_DRAM_TEST)
255	int
256	testdram(void)
257	{
258	uint pstart = (uint ) CFG_MEMTEST_START;
259	uint pend = (uint ) CFG_MEMTEST_END;
260	uint *p;
261
262	printf("Testing DRAM from 0x%08x to 0x%08x\n",
263	CFG_MEMTEST_START,
264	CFG_MEMTEST_END);
265
266	printf("DRAM test phase 1:\n");
267	for (p = pstart; p < pend; p++)
268	*p = 0xaaaaaaaa;
269
270	for (p = pstart; p < pend; p++) {
271	if (*p != 0xaaaaaaaa) {
272	printf ("DRAM test fails at: %08x\n", (uint) p);
273	return 1;
274	}
275	}
276
277	printf("DRAM test phase 2:\n");
278	for (p = pstart; p < pend; p++)
279	*p = 0x55555555;
280
281	for (p = pstart; p < pend; p++) {
282	if (*p != 0x55555555) {
283	printf ("DRAM test fails at: %08x\n", (uint) p);
284	return 1;
285	}
286	}
287
288	printf("DRAM test passed.\n");
289	return 0;
290	}
291	#endif
292
f2cff6b1	293	#if defined(CONFIG_PCI) \|\| defined(CONFIG_PCI1)
bf1dfffd MM	294	/* For some reason the Tundra PCI bridge shows up on itself as a
bf1dfffd MM	295	* different device. Work around that by refusing to configure it.
d9b94f28	296	*/
bf1dfffd	297	void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
d9b94f28	298
d9b94f28	299	static struct pci_config_table pci_mpc85xxcds_config_table[] = {
bf1dfffd	300	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
7f3f2bd2 RV	301	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
7f3f2bd2 RV	302	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
ffa621a0	303	mpc85xx_config_via_usbide, {0,0,0}},
7f3f2bd2 RV	304	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
	305	mpc85xx_config_via_usb, {0,0,0}},
	306	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
	307	mpc85xx_config_via_usb2, {0,0,0}},
	308	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
ffa621a0	309	mpc85xx_config_via_power, {0,0,0}},
7f3f2bd2 RV	310	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
7f3f2bd2 RV	311	mpc85xx_config_via_ac97, {0,0,0}},
ffa621a0	312	{},
d9b94f28	313	};
d9b94f28	314
f2cff6b1 ES	315	static struct pci_controller pci1_hose = {
f2cff6b1 ES	316	config_table: pci_mpc85xxcds_config_table};
d9b94f28 JL	317	#endif /* CONFIG_PCI */
d9b94f28 JL	318
f2cff6b1 ES	319	#ifdef CONFIG_PCI2
	320	static struct pci_controller pci2_hose;
	321	#endif /* CONFIG_PCI2 */
	322
	323	#ifdef CONFIG_PCIE1
	324	static struct pci_controller pcie1_hose;
	325	#endif /* CONFIG_PCIE1 */
	326
	327	int first_free_busno=0;
	328
d9b94f28 JL	329	void
	330	pci_init_board(void)
	331	{
f59b55a5	332	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
f2cff6b1 ES	333	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	334	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	335
	336
	337	#ifdef CONFIG_PCI1
	338	{
	339	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CFG_PCI1_ADDR;
	340	extern void fsl_pci_init(struct pci_controller *hose);
	341	struct pci_controller *hose = &pci1_hose;
	342	struct pci_config_table *table;
	343
	344	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
	345	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
	346	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
	347
	348	uint pci_agent = (host_agent == 3) \|\| (host_agent == 4 ) \|\| (host_agent == 6);
	349
	350	uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
	351
	352	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
	353	printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
	354	(pci_32) ? 32 : 64,
	355	(pci_speed == 33333000) ? "33" :
	356	(pci_speed == 66666000) ? "66" : "unknown",
	357	pci_clk_sel ? "sync" : "async",
	358	pci_agent ? "agent" : "host",
	359	pci_arb ? "arbiter" : "external-arbiter"
	360	);
	361
	362
4bf4abb8	363	/* inbound */
f2cff6b1	364	pci_set_region(hose->regions + 0,
4bf4abb8 ES	365	CFG_PCI_MEMORY_BUS,
	366	CFG_PCI_MEMORY_PHYS,
	367	CFG_PCI_MEMORY_SIZE,
	368	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	369
	370
	371	/* outbound memory */
	372	pci_set_region(hose->regions + 1,
f2cff6b1 ES	373	CFG_PCI1_MEM_BASE,
	374	CFG_PCI1_MEM_PHYS,
	375	CFG_PCI1_MEM_SIZE,
	376	PCI_REGION_MEM);
	377
	378	/* outbound io */
4bf4abb8	379	pci_set_region(hose->regions + 2,
f2cff6b1 ES	380	CFG_PCI1_IO_BASE,
	381	CFG_PCI1_IO_PHYS,
	382	CFG_PCI1_IO_SIZE,
	383	PCI_REGION_IO);
4bf4abb8	384	hose->region_count = 3;
f2cff6b1 ES	385
	386	/* relocate config table pointers */
	387	hose->config_table = \
	388	(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
	389	for (table = hose->config_table; table && table->vendor; table++)
	390	table->config_device += gd->reloc_off;
	391
	392	hose->first_busno=first_free_busno;
	393	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	394
	395	fsl_pci_init(hose);
	396	first_free_busno=hose->last_busno+1;
	397	printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
	398	#ifdef CONFIG_PCIX_CHECK
	399	if (!(gur->pordevsr & PORDEVSR_PCI)) {
	400	/* PCI-X init */
	401	if (CONFIG_SYS_CLK_FREQ < 66000000)
	402	printf("PCI-X will only work at 66 MHz\n");
	403
	404	reg16 = PCI_X_CMD_MAX_SPLIT \| PCI_X_CMD_MAX_READ
	405	\| PCI_X_CMD_ERO \| PCI_X_CMD_DPERR_E;
	406	pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
	407	}
d9b94f28	408	#endif
f2cff6b1 ES	409	} else {
	410	printf (" PCI: disabled\n");
	411	}
	412	}
	413	#else
	414	gur->devdisr \|= MPC85xx_DEVDISR_PCI1; /* disable */
	415	#endif
	416
	417	#ifdef CONFIG_PCI2
	418	{
	419	uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
	420	uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
	421	if (pci_dual) {
	422	printf (" PCI2: 32 bit, 66 MHz, %s\n",
	423	pci2_clk_sel ? "sync" : "async");
	424	} else {
	425	printf (" PCI2: disabled\n");
	426	}
	427	}
	428	#else
	429	gur->devdisr \|= MPC85xx_DEVDISR_PCI2; /* disable */
	430	#endif /* CONFIG_PCI2 */
	431
	432	#ifdef CONFIG_PCIE1
	433	{
	434	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CFG_PCIE1_ADDR;
	435	extern void fsl_pci_init(struct pci_controller *hose);
	436	struct pci_controller *hose = &pcie1_hose;
	437	int pcie_ep = (host_agent == 0) \|\| (host_agent == 2 ) \|\| (host_agent == 3);
	438
	439	int pcie_configured = io_sel >= 1;
	440
	441	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
	442	printf ("\n PCIE connected to slot as %s (base address %x)",
	443	pcie_ep ? "End Point" : "Root Complex",
	444	(uint)pci);
	445
	446	if (pci->pme_msg_det) {
	447	pci->pme_msg_det = 0xffffffff;
	448	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	449	}
	450	printf ("\n");
	451
	452	/* inbound */
	453	pci_set_region(hose->regions + 0,
	454	CFG_PCI_MEMORY_BUS,
	455	CFG_PCI_MEMORY_PHYS,
	456	CFG_PCI_MEMORY_SIZE,
	457	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	458
	459	/* outbound memory */
	460	pci_set_region(hose->regions + 1,
	461	CFG_PCIE1_MEM_BASE,
	462	CFG_PCIE1_MEM_PHYS,
	463	CFG_PCIE1_MEM_SIZE,
	464	PCI_REGION_MEM);
	465
	466	/* outbound io */
	467	pci_set_region(hose->regions + 2,
	468	CFG_PCIE1_IO_BASE,
	469	CFG_PCIE1_IO_PHYS,
	470	CFG_PCIE1_IO_SIZE,
	471	PCI_REGION_IO);
	472
473	hose->region_count = 3;
474
475	hose->first_busno=first_free_busno;
476	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
477
478	fsl_pci_init(hose);
479	printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
480
481	first_free_busno=hose->last_busno+1;
482
483	} else {
484	printf (" PCIE: disabled\n");
485	}
486	}
487	#else
488	gur->devdisr \|= MPC85xx_DEVDISR_PCIE; /* disable */
489	#endif
490
d9b94f28	491	}
09f3e09e AF	492
	493	int last_stage_init(void)
	494	{
f5012827	495	unsigned short temp;
09f3e09e AF	496
	497	/* Change the resistors for the PHY */
	498	/* This is needed to get the RGMII working for the 1.3+
	499	* CDS cards */
	500	if (get_board_version() == 0x13) {
255a3577	501	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	502	TSEC1_PHY_ADDR, 29, 18);
09f3e09e AF	503
255a3577	504	miiphy_read(CONFIG_TSEC1_NAME,
09f3e09e AF	505	TSEC1_PHY_ADDR, 30, &temp);
	506
	507	temp = (temp & 0xf03f);
	508	temp \|= 2 << 9; /* 36 ohm */
	509	temp \|= 2 << 6; /* 39 ohm */
	510
255a3577	511	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	512	TSEC1_PHY_ADDR, 30, temp);
09f3e09e AF	513
255a3577	514	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	515	TSEC1_PHY_ADDR, 29, 3);
09f3e09e AF	516
255a3577	517	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	518	TSEC1_PHY_ADDR, 30, 0x8000);
	519	}
	520
	521	return 0;
	522	}
f2cff6b1 ES	523
	524
	525	#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
	526	void
	527	ft_pci_setup(void blob, bd_t bd)
	528	{
	529	u32 *p;
	530	int len;
	531
	532
	533	#ifdef CONFIG_PCI1
	534	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
	535	if (p != NULL) {
	536	p[0] = 0;
	537	p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
	538	debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
	539	}
	540	#endif
	541
	542	#ifdef CONFIG_PCIE1
f75e89e9	543	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
f2cff6b1 ES	544	if (p != NULL) {
	545	p[0] = 0;
	546	p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
	547	debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
	548	}
	549	#endif
	550	}
	551	#endif