]> Git Repo - J-u-boot.git/blame - arch/powerpc/include/asm/immap_83xx.h
projects / J-u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
83xx/85xx/86xx: LBC register cleanup
[J-u-boot.git] / arch / powerpc / include / asm / immap_83xx.h
CommitLineData
f046ccd1 1/*
b9e186fc 2 * Copyright 2004-2009 Freescale Semiconductor, Inc.
f6eda7f8
DL		 3 *
4 * MPC83xx Internal Memory Map
5 *
e080313c
DL		 6 * Contributors:
7 * Dave Liu <[email protected]>
8 * Tanya Jiang <[email protected]>
9 * Mandy Lavi <[email protected]>
10 * Eran Liberty <[email protected]>
f6eda7f8
DL		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
e080313c 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
f6eda7f8
DL		 20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
de1d0a69 26 *
f046ccd1 27 */
f6eda7f8
DL		 28#ifndef __IMMAP_83xx__
29#define __IMMAP_83xx__
f046ccd1
EL		 30
31#include <asm/types.h>
be5e6181 32#include <asm/fsl_i2c.h>
04a9e118 33#include <asm/mpc8xxx_spi.h>
4e190b03 34#include <asm/fsl_lbc.h>
e94e460c 35#include <asm/fsl_dma.h>
f046ccd1 36
de1d0a69 37/*
e080313c 38 * Local Access Window
f046ccd1 39 */
f6eda7f8 40typedef struct law83xx {
b701652a 41 u32 bar; /* LBIU local access window base address register */
b701652a 42 u32 ar; /* LBIU local access window attribute register */
f6eda7f8 43} law83xx_t;
f046ccd1 44
de1d0a69 45/*
e080313c 46 * System configuration registers
f046ccd1 47 */
f6eda7f8 48typedef struct sysconf83xx {
b701652a 49 u32 immrbar; /* Internal memory map base address register */
f046ccd1 50 u8 res0[0x04];
b701652a 51 u32 altcbar; /* Alternate configuration base address register */
f046ccd1 52 u8 res1[0x14];
b701652a 53 law83xx_t lblaw[4]; /* LBIU local access window */
f046ccd1 54 u8 res2[0x20];
b701652a 55 law83xx_t pcilaw[2]; /* PCI local access window */
fd6646c0
AV		 56 u8 res3[0x10];
57 law83xx_t pcielaw[2]; /* PCI Express local access window */
58 u8 res4[0x10];
b701652a 59 law83xx_t ddrlaw[2]; /* DDR local access window */
fd6646c0 60 u8 res5[0x50];
b701652a
DL		 61 u32 sgprl; /* System General Purpose Register Low */
62 u32 sgprh; /* System General Purpose Register High */
63 u32 spridr; /* System Part and Revision ID Register */
fd6646c0 64 u8 res6[0x04];
b701652a 65 u32 spcr; /* System Priority Configuration Register */
e080313c
DL		 66 u32 sicrl; /* System I/O Configuration Register Low */
67 u32 sicrh; /* System I/O Configuration Register High */
fd6646c0 68 u8 res7[0x04];
002d27ca
NS		 69 u32 sidcr0; /* System I/O Delay Configuration Register 0 */
70 u32 sidcr1; /* System I/O Delay Configuration Register 1 */
24c3aca3
DL		 71 u32 ddrcdr; /* DDR Control Driver Register */
72 u32 ddrdsr; /* DDR Debug Status Register */
03051c3d 73 u32 obir; /* Output Buffer Impedance Register */
fd6646c0
AV		 74 u8 res8[0xC];
75 u32 pecr1; /* PCI Express control register 1 */
7c619ddc
IY		 76#ifdef CONFIG_MPC8308
77 u32 sdhccr; /* eSDHC Control Registers for MPC8308 */
78#else
fd6646c0 79 u32 pecr2; /* PCI Express control register 2 */
7c619ddc 80#endif
fd6646c0 81 u8 res9[0xB8];
f6eda7f8 82} sysconf83xx_t;
f046ccd1 83
de1d0a69 84/*
f046ccd1
EL		 85 * Watch Dog Timer (WDT) Registers
86 */
f6eda7f8 87typedef struct wdt83xx {
de1d0a69 88 u8 res0[4];
b701652a
DL		 89 u32 swcrr; /* System watchdog control register */
90 u32 swcnr; /* System watchdog count register */
de1d0a69 91 u8 res1[2];
b701652a 92 u16 swsrr; /* System watchdog service register */
f046ccd1 93 u8 res2[0xF0];
f6eda7f8 94} wdt83xx_t;
de1d0a69 95
f046ccd1
EL		 96/*
97 * RTC/PIT Module Registers
98 */
f6eda7f8 99typedef struct rtclk83xx {
b701652a 100 u32 cnr; /* control register */
b701652a 101 u32 ldr; /* load register */
b701652a 102 u32 psr; /* prescale register */
e080313c 103 u32 ctr; /* counter value field register */
b701652a 104 u32 evr; /* event register */
b701652a 105 u32 alr; /* alarm register */
f046ccd1 106 u8 res0[0xE8];
f6eda7f8 107} rtclk83xx_t;
f046ccd1
EL		 108
109/*
e080313c 110 * Global timer module
f046ccd1 111 */
f6eda7f8 112typedef struct gtm83xx {
e080313c 113 u8 cfr1; /* Timer1/2 Configuration */
b701652a 114 u8 res0[3];
e080313c 115 u8 cfr2; /* Timer3/4 Configuration */
b701652a 116 u8 res1[10];
e080313c
DL		 117 u16 mdr1; /* Timer1 Mode Register */
118 u16 mdr2; /* Timer2 Mode Register */
119 u16 rfr1; /* Timer1 Reference Register */
120 u16 rfr2; /* Timer2 Reference Register */
121 u16 cpr1; /* Timer1 Capture Register */
122 u16 cpr2; /* Timer2 Capture Register */
123 u16 cnr1; /* Timer1 Counter Register */
124 u16 cnr2; /* Timer2 Counter Register */
125 u16 mdr3; /* Timer3 Mode Register */
126 u16 mdr4; /* Timer4 Mode Register */
127 u16 rfr3; /* Timer3 Reference Register */
128 u16 rfr4; /* Timer4 Reference Register */
129 u16 cpr3; /* Timer3 Capture Register */
130 u16 cpr4; /* Timer4 Capture Register */
131 u16 cnr3; /* Timer3 Counter Register */
132 u16 cnr4; /* Timer4 Counter Register */
133 u16 evr1; /* Timer1 Event Register */
134 u16 evr2; /* Timer2 Event Register */
135 u16 evr3; /* Timer3 Event Register */
136 u16 evr4; /* Timer4 Event Register */
137 u16 psr1; /* Timer1 Prescaler Register */
138 u16 psr2; /* Timer2 Prescaler Register */
139 u16 psr3; /* Timer3 Prescaler Register */
140 u16 psr4; /* Timer4 Prescaler Register */
b701652a 141 u8 res[0xC0];
f6eda7f8 142} gtm83xx_t;
f046ccd1
EL		 143
144/*
145 * Integrated Programmable Interrupt Controller
146 */
f6eda7f8 147typedef struct ipic83xx {
e080313c
DL		 148 u32 sicfr; /* System Global Interrupt Configuration Register */
149 u32 sivcr; /* System Global Interrupt Vector Register */
150 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
151 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
152 u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
b701652a 153 u8 res0[8];
e080313c
DL		 154 u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
155 u32 simsr_h; /* System Internal Interrupt Mask Register - High */
156 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
b701652a 157 u8 res1[4];
e080313c
DL		 158 u32 sepnr; /* System External Interrupt Pending Register */
159 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
160 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
161 u32 semsr; /* System External Interrupt Mask Register */
162 u32 secnr; /* System External Interrupt Control Register */
163 u32 sersr; /* System Error Status Register */
164 u32 sermr; /* System Error Mask Register */
165 u32 sercr; /* System Error Control Register */
b701652a 166 u8 res2[4];
e080313c
DL		 167 u32 sifcr_h; /* System Internal Interrupt Force Register - High */
168 u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
169 u32 sefcr; /* System External Interrupt Force Register */
170 u32 serfr; /* System Error Force Register */
b701652a 171 u32 scvcr; /* System Critical Interrupt Vector Register */
b701652a 172 u32 smvcr; /* System Management Interrupt Vector Register */
b701652a 173 u8 res3[0x98];
f6eda7f8 174} ipic83xx_t;
f046ccd1
EL		 175
176/*
177 * System Arbiter Registers
178 */
f6eda7f8 179typedef struct arbiter83xx {
b701652a 180 u32 acr; /* Arbiter Configuration Register */
b701652a 181 u32 atr; /* Arbiter Timers Register */
f046ccd1 182 u8 res[4];
e080313c
DL		 183 u32 aer; /* Arbiter Event Register */
184 u32 aidr; /* Arbiter Interrupt Definition Register */
185 u32 amr; /* Arbiter Mask Register */
b701652a 186 u32 aeatr; /* Arbiter Event Attributes Register */
b701652a 187 u32 aeadr; /* Arbiter Event Address Register */
e080313c 188 u32 aerr; /* Arbiter Event Response Register */
f046ccd1 189 u8 res1[0xDC];
f6eda7f8 190} arbiter83xx_t;
f046ccd1
EL		 191
192/*
193 * Reset Module
194 */
f6eda7f8 195typedef struct reset83xx {
e080313c
DL		 196 u32 rcwl; /* Reset Configuration Word Low Register */
197 u32 rcwh; /* Reset Configuration Word High Register */
b701652a 198 u8 res0[8];
e080313c
DL		 199 u32 rsr; /* Reset Status Register */
200 u32 rmr; /* Reset Mode Register */
201 u32 rpr; /* Reset protection Register */
202 u32 rcr; /* Reset Control Register */
203 u32 rcer; /* Reset Control Enable Register */
b701652a 204 u8 res1[0xDC];
f6eda7f8 205} reset83xx_t;
de1d0a69 206
e080313c
DL		 207/*
208 * Clock Module
209 */
f6eda7f8 210typedef struct clk83xx {
e080313c
DL		 211 u32 spmr; /* system PLL mode Register */
212 u32 occr; /* output clock control Register */
213 u32 sccr; /* system clock control Register */
b701652a 214 u8 res0[0xF4];
f6eda7f8 215} clk83xx_t;
f046ccd1
EL		 216
217/*
218 * Power Management Control Module
219 */
f6eda7f8 220typedef struct pmc83xx {
e080313c
DL		 221 u32 pmccr; /* PMC Configuration Register */
222 u32 pmcer; /* PMC Event Register */
223 u32 pmcmr; /* PMC Mask Register */
d87c57b2
SW		 224 u32 pmccr1; /* PMC Configuration Register 1 */
225 u32 pmccr2; /* PMC Configuration Register 2 */
226 u8 res0[0xEC];
f6eda7f8 227} pmc83xx_t;
f046ccd1
EL		 228
229/*
e080313c 230 * General purpose I/O module
f046ccd1 231 */
f6eda7f8 232typedef struct gpio83xx {
b701652a
DL		 233 u32 dir; /* direction register */
234 u32 odr; /* open drain register */
235 u32 dat; /* data register */
236 u32 ier; /* interrupt event register */
237 u32 imr; /* interrupt mask register */
238 u32 icr; /* external interrupt control register */
f046ccd1 239 u8 res0[0xE8];
f6eda7f8 240} gpio83xx_t;
b701652a 241
b701652a
DL		 242/*
243 * QE Ports Interrupts Registers
244 */
245typedef struct qepi83xx {
246 u8 res0[0xC];
247 u32 qepier; /* QE Ports Interrupt Event Register */
b701652a 248 u32 qepimr; /* QE Ports Interrupt Mask Register */
b701652a 249 u32 qepicr; /* QE Ports Interrupt Control Register */
b701652a
DL		 250 u8 res1[0xE8];
251} qepi83xx_t;
252
253/*
e080313c 254 * QE Parallel I/O Ports
b701652a
DL		 255 */
256typedef struct gpio_n {
257 u32 podr; /* Open Drain Register */
258 u32 pdat; /* Data Register */
259 u32 dir1; /* direction register 1 */
260 u32 dir2; /* direction register 2 */
261 u32 ppar1; /* Pin Assignment Register 1 */
262 u32 ppar2; /* Pin Assignment Register 2 */
263} gpio_n_t;
264
e080313c 265typedef struct qegpio83xx {
b701652a
DL		 266 gpio_n_t ioport[0x7];
267 u8 res0[0x358];
e080313c 268} qepio83xx_t;
b701652a
DL		 269
270/*
271 * QE Secondary Bus Access Windows
272 */
b701652a
DL		 273typedef struct qesba83xx {
274 u32 lbmcsar; /* Local bus memory controller start address */
b701652a 275 u32 sdmcsar; /* Secondary DDR memory controller start address */
b701652a
DL		 276 u8 res0[0x38];
277 u32 lbmcear; /* Local bus memory controller end address */
b701652a 278 u32 sdmcear; /* Secondary DDR memory controller end address */
b701652a 279 u8 res1[0x38];
e080313c 280 u32 lbmcar; /* Local bus memory controller attributes */
b701652a 281 u32 sdmcar; /* Secondary DDR memory controller attributes */
e080313c 282 u8 res2[0x378];
b701652a 283} qesba83xx_t;
f046ccd1 284
de1d0a69 285/*
f046ccd1
EL		 286 * DDR Memory Controller Memory Map
287 */
b701652a 288typedef struct ddr_cs_bnds {
de1d0a69 289 u32 csbnds;
b701652a 290 u8 res0[4];
f046ccd1
EL		 291} ddr_cs_bnds_t;
292
f6eda7f8 293typedef struct ddr83xx {
e080313c 294 ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
de1d0a69 295 u8 res0[0x60];
e080313c 296 u32 cs_config[4]; /* Chip Select x Configuration */
24c3aca3
DL		 297 u8 res1[0x70];
298 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
299 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
e080313c
DL		 300 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
301 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
302 u32 sdram_cfg; /* SDRAM Control Configuration */
24c3aca3 303 u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
e080313c 304 u32 sdram_mode; /* SDRAM Mode Configuration */
24c3aca3
DL		 305 u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
306 u32 sdram_md_cntl; /* SDRAM Mode Control */
e080313c 307 u32 sdram_interval; /* SDRAM Interval Configuration */
24c3aca3
DL		 308 u32 ddr_data_init; /* SDRAM Data Initialization */
309 u8 res2[4];
310 u32 sdram_clk_cntl; /* SDRAM Clock Control */
311 u8 res3[0x14];
312 u32 ddr_init_addr; /* DDR training initialization address */
313 u32 ddr_init_ext_addr; /* DDR training initialization extended address */
314 u8 res4[0xAA8];
315 u32 ddr_ip_rev1; /* DDR IP block revision 1 */
316 u32 ddr_ip_rev2; /* DDR IP block revision 2 */
317 u8 res5[0x200];
e080313c
DL		 318 u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
319 u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
320 u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
24c3aca3 321 u8 res6[0x14];
e080313c
DL		 322 u32 capture_data_hi; /* Memory Data Path Read Capture High */
323 u32 capture_data_lo; /* Memory Data Path Read Capture Low */
324 u32 capture_ecc; /* Memory Data Path Read Capture ECC */
24c3aca3 325 u8 res7[0x14];
e080313c
DL		 326 u32 err_detect; /* Memory Error Detect */
327 u32 err_disable; /* Memory Error Disable */
328 u32 err_int_en; /* Memory Error Interrupt Enable */
329 u32 capture_attributes; /* Memory Error Attributes Capture */
330 u32 capture_address; /* Memory Error Address Capture */
331 u32 capture_ext_address;/* Memory Error Extended Address Capture */
332 u32 err_sbe; /* Memory Single-Bit ECC Error Management */
24c3aca3 333 u8 res8[0xA4];
f046ccd1 334 u32 debug_reg;
24c3aca3 335 u8 res9[0xFC];
f6eda7f8 336} ddr83xx_t;
f046ccd1 337
f046ccd1
EL		 338/*
339 * DUART
340 */
b701652a 341typedef struct duart83xx {
e080313c
DL		 342 u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
343 u8 uier_udmb; /* combined register for UIER and UDMB */
344 u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
345 u8 ulcr; /* line control register */
346 u8 umcr; /* MODEM control register */
347 u8 ulsr; /* line status register */
348 u8 umsr; /* MODEM status register */
349 u8 uscr; /* scratch register */
de1d0a69 350 u8 res0[8];
e080313c 351 u8 udsr; /* DMA status register */
de1d0a69
JL		 352 u8 res1[3];
353 u8 res2[0xEC];
f6eda7f8 354} duart83xx_t;
f046ccd1 355
61f25155
MB		 356/*
357 * DMA/Messaging Unit
358 */
f6eda7f8 359typedef struct dma83xx {
b701652a
DL		 360 u32 res0[0xC]; /* 0x0-0x29 reseverd */
361 u32 omisr; /* 0x30 Outbound message interrupt status register */
362 u32 omimr; /* 0x34 Outbound message interrupt mask register */
363 u32 res1[0x6]; /* 0x38-0x49 reserved */
b701652a
DL		 364 u32 imr0; /* 0x50 Inbound message register 0 */
365 u32 imr1; /* 0x54 Inbound message register 1 */
366 u32 omr0; /* 0x58 Outbound message register 0 */
367 u32 omr1; /* 0x5C Outbound message register 1 */
b701652a
DL		 368 u32 odr; /* 0x60 Outbound doorbell register */
369 u32 res2; /* 0x64-0x67 reserved */
370 u32 idr; /* 0x68 Inbound doorbell register */
371 u32 res3[0x5]; /* 0x6C-0x79 reserved */
b701652a
DL		 372 u32 imisr; /* 0x80 Inbound message interrupt status register */
373 u32 imimr; /* 0x84 Inbound message interrupt mask register */
374 u32 res4[0x1E]; /* 0x88-0x99 reserved */
e94e460c 375 struct fsl_dma dma[4];
f6eda7f8 376} dma83xx_t;
f046ccd1
EL		 377
378/*
379 * PCI Software Configuration Registers
380 */
f6eda7f8 381typedef struct pciconf83xx {
b701652a 382 u32 config_address;
f046ccd1
EL		 383 u32 config_data;
384 u32 int_ack;
b701652a 385 u8 res[116];
f6eda7f8 386} pciconf83xx_t;
f046ccd1
EL		 387
388/*
389 * PCI Outbound Translation Register
390 */
391typedef struct pci_outbound_window {
b701652a
DL		 392 u32 potar;
393 u8 res0[4];
394 u32 pobar;
395 u8 res1[4];
396 u32 pocmr;
397 u8 res2[4];
f6eda7f8 398} pot83xx_t;
b701652a 399
f046ccd1
EL		 400/*
401 * Sequencer
de1d0a69 402 */
f6eda7f8 403typedef struct ios83xx {
b701652a 404 pot83xx_t pot[6];
b701652a
DL		 405 u8 res0[0x60];
406 u32 pmcr;
407 u8 res1[4];
408 u32 dtcr;
409 u8 res2[4];
f6eda7f8 410} ios83xx_t;
f046ccd1
EL		 411
412/*
413 * PCI Controller Control and Status Registers
414 */
f6eda7f8 415typedef struct pcictrl83xx {
b701652a 416 u32 esr;
b701652a 417 u32 ecdr;
f046ccd1 418 u32 eer;
b701652a 419 u32 eatcr;
b701652a
DL		 420 u32 eacr;
421 u32 eeacr;
b701652a
DL		 422 u32 edlcr;
423 u32 edhcr;
b701652a
DL		 424 u32 gcr;
425 u32 ecr;
426 u32 gsr;
427 u8 res0[12];
428 u32 pitar2;
429 u8 res1[4];
430 u32 pibar2;
431 u32 piebar2;
432 u32 piwar2;
433 u8 res2[4];
434 u32 pitar1;
435 u8 res3[4];
436 u32 pibar1;
437 u32 piebar1;
438 u32 piwar1;
439 u8 res4[4];
440 u32 pitar0;
441 u8 res5[4];
442 u32 pibar0;
443 u8 res6[4];
444 u32 piwar0;
445 u8 res7[132];
f6eda7f8 446} pcictrl83xx_t;
f046ccd1
EL		 447
448/*
de1d0a69 449 * USB
f046ccd1 450 */
f6eda7f8 451typedef struct usb83xx {
d87c57b2 452 u8 fixme[0x1000];
f6eda7f8 453} usb83xx_t;
f046ccd1
EL		 454
455/*
456 * TSEC
457 */
f6eda7f8 458typedef struct tsec83xx {
f046ccd1 459 u8 fixme[0x1000];
f6eda7f8 460} tsec83xx_t;
f046ccd1
EL		 461
462/*
463 * Security
464 */
f6eda7f8 465typedef struct security83xx {
f046ccd1 466 u8 fixme[0x10000];
f6eda7f8 467} security83xx_t;
f046ccd1 468
03051c3d
DL		 469/*
470 * PCI Express
471 */
fd6646c0
AV		 472struct pex_inbound_window {
473 u32 ar;
474 u32 tar;
475 u32 barl;
476 u32 barh;
477};
478
479struct pex_outbound_window {
480 u32 ar;
481 u32 bar;
482 u32 tarl;
483 u32 tarh;
484};
485
486struct pex_csb_bridge {
487 u32 pex_csb_ver;
488 u32 pex_csb_cab;
489 u32 pex_csb_ctrl;
490 u8 res0[8];
491 u32 pex_dms_dstmr;
492 u8 res1[4];
493 u32 pex_cbs_stat;
494 u8 res2[0x20];
495 u32 pex_csb_obctrl;
496 u32 pex_csb_obstat;
497 u8 res3[0x98];
498 u32 pex_csb_ibctrl;
499 u32 pex_csb_ibstat;
500 u8 res4[0xb8];
501 u32 pex_wdma_ctrl;
502 u32 pex_wdma_addr;
503 u32 pex_wdma_stat;
504 u8 res5[0x94];
505 u32 pex_rdma_ctrl;
506 u32 pex_rdma_addr;
507 u32 pex_rdma_stat;
508 u8 res6[0xd4];
509 u32 pex_ombcr;
510 u32 pex_ombdr;
511 u8 res7[0x38];
512 u32 pex_imbcr;
513 u32 pex_imbdr;
514 u8 res8[0x38];
515 u32 pex_int_enb;
516 u32 pex_int_stat;
517 u32 pex_int_apio_vec1;
518 u32 pex_int_apio_vec2;
519 u8 res9[0x10];
520 u32 pex_int_ppio_vec1;
521 u32 pex_int_ppio_vec2;
522 u32 pex_int_wdma_vec1;
523 u32 pex_int_wdma_vec2;
524 u32 pex_int_rdma_vec1;
525 u32 pex_int_rdma_vec2;
526 u32 pex_int_misc_vec;
527 u8 res10[4];
528 u32 pex_int_axi_pio_enb;
529 u32 pex_int_axi_wdma_enb;
530 u32 pex_int_axi_rdma_enb;
531 u32 pex_int_axi_misc_enb;
532 u32 pex_int_axi_pio_stat;
533 u32 pex_int_axi_wdma_stat;
534 u32 pex_int_axi_rdma_stat;
535 u32 pex_int_axi_misc_stat;
536 u8 res11[0xa0];
537 struct pex_outbound_window pex_outbound_win[4];
538 u8 res12[0x100];
539 u32 pex_epiwtar0;
540 u32 pex_epiwtar1;
541 u32 pex_epiwtar2;
542 u32 pex_epiwtar3;
543 u8 res13[0x70];
544 struct pex_inbound_window pex_inbound_win[4];
545};
546
03051c3d 547typedef struct pex83xx {
fd6646c0
AV		 548 u8 pex_cfg_header[0x404];
549 u32 pex_ltssm_stat;
550 u8 res0[0x30];
551 u32 pex_ack_replay_timeout;
552 u8 res1[4];
553 u32 pex_gclk_ratio;
554 u8 res2[0xc];
555 u32 pex_pm_timer;
556 u32 pex_pme_timeout;
557 u8 res3[4];
558 u32 pex_aspm_req_timer;
559 u8 res4[0x18];
560 u32 pex_ssvid_update;
561 u8 res5[0x34];
562 u32 pex_cfg_ready;
563 u8 res6[0x24];
564 u32 pex_bar_sizel;
565 u8 res7[4];
566 u32 pex_bar_sel;
567 u8 res8[0x20];
568 u32 pex_bar_pf;
569 u8 res9[0x88];
570 u32 pex_pme_to_ack_tor;
571 u8 res10[0xc];
572 u32 pex_ss_intr_mask;
573 u8 res11[0x25c];
574 struct pex_csb_bridge bridge;
575 u8 res12[0x160];
03051c3d
DL		 576} pex83xx_t;
577
578/*
579 * SATA
580 */
581typedef struct sata83xx {
582 u8 fixme[0x1000];
583} sata83xx_t;
584
585/*
586 * eSDHC
587 */
588typedef struct sdhc83xx {
589 u8 fixme[0x1000];
590} sdhc83xx_t;
591
592/*
593 * SerDes
594 */
595typedef struct serdes83xx {
7c619ddc
IY		 596 u32 srdscr0;
597 u32 srdscr1;
598 u32 srdscr2;
599 u32 srdscr3;
600 u32 srdscr4;
601 u8 res0[0xc];
602 u32 srdsrstctl;
603 u8 res1[0xdc];
03051c3d
DL		 604} serdes83xx_t;
605
606/*
607 * On Chip ROM
608 */
609typedef struct rom83xx {
610 u8 mem[0x10000];
611} rom83xx_t;
612
555da617
DL		 613/*
614 * TDM
615 */
616typedef struct tdm83xx {
617 u8 fixme[0x200];
618} tdm83xx_t;
619
620/*
621 * TDM DMAC
622 */
623typedef struct tdmdmac83xx {
624 u8 fixme[0x2000];
625} tdmdmac83xx_t;
626
2c7920af 627#if defined(CONFIG_MPC834x)
e080313c
DL		 628typedef struct immap {
629 sysconf83xx_t sysconf; /* System configuration */
630 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
631 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
632 rtclk83xx_t pit; /* Periodic Interval Timer */
633 gtm83xx_t gtm[2]; /* Global Timers Module */
634 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
635 arbiter83xx_t arbiter; /* System Arbiter Registers */
636 reset83xx_t reset; /* Reset Module */
637 clk83xx_t clk; /* System Clock Module */
638 pmc83xx_t pmc; /* Power Management Control Module */
639 gpio83xx_t gpio[2]; /* General purpose I/O module */
640 u8 res0[0x200];
641 u8 dll_ddr[0x100];
642 u8 dll_lbc[0x100];
643 u8 res1[0xE00];
644 ddr83xx_t ddr; /* DDR Memory Controller Memory */
645 fsl_i2c_t i2c[2]; /* I2C Controllers */
646 u8 res2[0x1300];
647 duart83xx_t duart[2]; /* DUART */
648 u8 res3[0x900];
f51cdaf1 649 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
e080313c 650 u8 res4[0x1000];
04a9e118 651 spi8xxx_t spi; /* Serial Peripheral Interface */
e080313c
DL		 652 dma83xx_t dma; /* DMA */
653 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
654 ios83xx_t ios; /* Sequencer */
655 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
656 u8 res5[0x19900];
d87c57b2
SW		 657 usb83xx_t usb[2];
658 tsec83xx_t tsec[2];
659 u8 res6[0xA000];
660 security83xx_t security;
661 u8 res7[0xC0000];
662} immap_t;
663
d89e1c36
VG		 664#ifdef CONFIG_HAS_FSL_MPH_USB
665#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x22000 /* use the MPH controller */
666#else
667#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 /* use the DR controller */
668#endif
669
555da617 670#elif defined(CONFIG_MPC8313)
d87c57b2
SW		 671typedef struct immap {
672 sysconf83xx_t sysconf; /* System configuration */
673 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
674 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
675 rtclk83xx_t pit; /* Periodic Interval Timer */
676 gtm83xx_t gtm[2]; /* Global Timers Module */
677 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
678 arbiter83xx_t arbiter; /* System Arbiter Registers */
679 reset83xx_t reset; /* Reset Module */
680 clk83xx_t clk; /* System Clock Module */
681 pmc83xx_t pmc; /* Power Management Control Module */
682 gpio83xx_t gpio[1]; /* General purpose I/O module */
683 u8 res0[0x1300];
684 ddr83xx_t ddr; /* DDR Memory Controller Memory */
685 fsl_i2c_t i2c[2]; /* I2C Controllers */
686 u8 res1[0x1300];
687 duart83xx_t duart[2]; /* DUART */
688 u8 res2[0x900];
f51cdaf1 689 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
d87c57b2 690 u8 res3[0x1000];
04a9e118 691 spi8xxx_t spi; /* Serial Peripheral Interface */
d87c57b2
SW		 692 dma83xx_t dma; /* DMA */
693 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
694 u8 res4[0x80];
695 ios83xx_t ios; /* Sequencer */
696 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
697 u8 res5[0x1aa00];
698 usb83xx_t usb[1];
e080313c
DL		 699 tsec83xx_t tsec[2];
700 u8 res6[0xA000];
701 security83xx_t security;
702 u8 res7[0xC0000];
703} immap_t;
b701652a 704
7c619ddc 705#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
555da617
DL		 706typedef struct immap {
707 sysconf83xx_t sysconf; /* System configuration */
708 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
709 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
710 rtclk83xx_t pit; /* Periodic Interval Timer */
711 gtm83xx_t gtm[2]; /* Global Timers Module */
712 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
713 arbiter83xx_t arbiter; /* System Arbiter Registers */
714 reset83xx_t reset; /* Reset Module */
715 clk83xx_t clk; /* System Clock Module */
716 pmc83xx_t pmc; /* Power Management Control Module */
717 gpio83xx_t gpio[1]; /* General purpose I/O module */
718 u8 res0[0x1300];
719 ddr83xx_t ddr; /* DDR Memory Controller Memory */
720 fsl_i2c_t i2c[2]; /* I2C Controllers */
721 u8 res1[0x1300];
722 duart83xx_t duart[2]; /* DUART */
723 u8 res2[0x900];
f51cdaf1 724 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
555da617 725 u8 res3[0x1000];
04a9e118 726 spi8xxx_t spi; /* Serial Peripheral Interface */
555da617
DL		 727 dma83xx_t dma; /* DMA */
728 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
729 u8 res4[0x80];
730 ios83xx_t ios; /* Sequencer */
731 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
732 u8 res5[0xa00];
733 pex83xx_t pciexp[2]; /* PCI Express Controller */
734 u8 res6[0xb000];
735 tdm83xx_t tdm; /* TDM Controller */
736 u8 res7[0x1e00];
737 sata83xx_t sata[2]; /* SATA Controller */
738 u8 res8[0x9000];
739 usb83xx_t usb[1]; /* USB DR Controller */
740 tsec83xx_t tsec[2];
741 u8 res9[0x6000];
742 tdmdmac83xx_t tdmdmac; /* TDM DMAC */
743 u8 res10[0x2000];
744 security83xx_t security;
745 u8 res11[0xA3000];
746 serdes83xx_t serdes[1]; /* SerDes Registers */
747 u8 res12[0x1CF00];
748} immap_t;
749
2c7920af 750#elif defined(CONFIG_MPC837x)
03051c3d
DL		 751typedef struct immap {
752 sysconf83xx_t sysconf; /* System configuration */
753 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
754 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
755 rtclk83xx_t pit; /* Periodic Interval Timer */
756 gtm83xx_t gtm[2]; /* Global Timers Module */
757 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
758 arbiter83xx_t arbiter; /* System Arbiter Registers */
759 reset83xx_t reset; /* Reset Module */
760 clk83xx_t clk; /* System Clock Module */
761 pmc83xx_t pmc; /* Power Management Control Module */
762 gpio83xx_t gpio[2]; /* General purpose I/O module */
763 u8 res0[0x1200];
764 ddr83xx_t ddr; /* DDR Memory Controller Memory */
765 fsl_i2c_t i2c[2]; /* I2C Controllers */
766 u8 res1[0x1300];
767 duart83xx_t duart[2]; /* DUART */
768 u8 res2[0x900];
f51cdaf1 769 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
03051c3d 770 u8 res3[0x1000];
04a9e118 771 spi8xxx_t spi; /* Serial Peripheral Interface */
03051c3d
DL		 772 dma83xx_t dma; /* DMA */
773 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
774 u8 res4[0x80];
775 ios83xx_t ios; /* Sequencer */
776 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
777 u8 res5[0xa00];
778 pex83xx_t pciexp[2]; /* PCI Express Controller */
779 u8 res6[0xd000];
780 sata83xx_t sata[4]; /* SATA Controller */
781 u8 res7[0x7000];
782 usb83xx_t usb[1]; /* USB DR Controller */
783 tsec83xx_t tsec[2];
784 u8 res8[0x8000];
785 sdhc83xx_t sdhc; /* SDHC Controller */
786 u8 res9[0x1000];
787 security83xx_t security;
788 u8 res10[0xA3000];
789 serdes83xx_t serdes[2]; /* SerDes Registers */
790 u8 res11[0xCE00];
791 rom83xx_t rom; /* On Chip ROM */
792} immap_t;
793
e080313c 794#elif defined(CONFIG_MPC8360)
f046ccd1 795typedef struct immap {
e080313c
DL		 796 sysconf83xx_t sysconf; /* System configuration */
797 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
798 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
799 rtclk83xx_t pit; /* Periodic Interval Timer */
800 u8 res0[0x200];
801 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
802 arbiter83xx_t arbiter; /* System Arbiter Registers */
803 reset83xx_t reset; /* Reset Module */
804 clk83xx_t clk; /* System Clock Module */
805 pmc83xx_t pmc; /* Power Management Control Module */
806 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
807 u8 res1[0x300];
808 u8 dll_ddr[0x100];
809 u8 dll_lbc[0x100];
810 u8 res2[0x200];
811 qepio83xx_t qepio; /* QE Parallel I/O ports */
812 qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
813 u8 res3[0x400];
814 ddr83xx_t ddr; /* DDR Memory Controller Memory */
815 fsl_i2c_t i2c[2]; /* I2C Controllers */
816 u8 res4[0x1300];
817 duart83xx_t duart[2]; /* DUART */
818 u8 res5[0x900];
f51cdaf1 819 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
e080313c
DL		 820 u8 res6[0x2000];
821 dma83xx_t dma; /* DMA */
822 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
823 u8 res7[128];
824 ios83xx_t ios; /* Sequencer (IOS) */
825 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
826 u8 res8[0x4A00];
827 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
828 u8 res9[0x22000];
829 security83xx_t security;
830 u8 res10[0xC0000];
831 u8 qe[0x100000]; /* QE block */
f046ccd1 832} immap_t;
24c3aca3 833
2c7920af 834#elif defined(CONFIG_MPC832x)
24c3aca3
DL		 835typedef struct immap {
836 sysconf83xx_t sysconf; /* System configuration */
837 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
838 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
839 rtclk83xx_t pit; /* Periodic Interval Timer */
840 gtm83xx_t gtm[2]; /* Global Timers Module */
841 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
842 arbiter83xx_t arbiter; /* System Arbiter Registers */
843 reset83xx_t reset; /* Reset Module */
844 clk83xx_t clk; /* System Clock Module */
845 pmc83xx_t pmc; /* Power Management Control Module */
846 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
847 u8 res0[0x300];
848 u8 dll_ddr[0x100];
849 u8 dll_lbc[0x100];
850 u8 res1[0x200];
851 qepio83xx_t qepio; /* QE Parallel I/O ports */
852 u8 res2[0x800];
853 ddr83xx_t ddr; /* DDR Memory Controller Memory */
854 fsl_i2c_t i2c[2]; /* I2C Controllers */
855 u8 res3[0x1300];
856 duart83xx_t duart[2]; /* DUART */
857 u8 res4[0x900];
f51cdaf1 858 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
24c3aca3
DL		 859 u8 res5[0x2000];
860 dma83xx_t dma; /* DMA */
861 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
862 u8 res6[128];
863 ios83xx_t ios; /* Sequencer (IOS) */
864 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
865 u8 res7[0x27A00];
866 security83xx_t security;
867 u8 res8[0xC0000];
868 u8 qe[0x100000]; /* QE block */
869} immap_t;
e080313c 870#endif
f046ccd1 871
e94e460c
PT		 872#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
873#define CONFIG_SYS_MPC83xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
e1ac387f
AF		 874#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
875#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
d89e1c36
VG		 876
877#ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
878#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
879#endif
4ef01010
VM		 880#define CONFIG_SYS_MPC83xx_USB_ADDR \
881 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
f51cdaf1 882#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
b9e186fc
SG		 883
884#define CONFIG_SYS_TSEC1_OFFSET 0x24000
3ad89c4e 885#define CONFIG_SYS_MDIO1_OFFSET 0x24000
b9e186fc
SG		 886
887#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
888#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
b701652a 889#endif /* __IMMAP_83xx__ */
Empty description
This page took 0.316672 seconds and 4 git commands to generate.