[J-u-boot.git] / include / fm_eth.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2009-2012 Freescale Semiconductor, Inc.
 * Copyright 2019 NXP
 */

#ifndef __FM_ETH_H__
#define __FM_ETH_H__

#include <phy.h>
#include <asm/types.h>

enum fm_port {
	FM1_DTSEC1,
	FM1_DTSEC2,
	FM1_DTSEC3,
	FM1_DTSEC4,
	FM1_DTSEC5,
	FM1_DTSEC6,
	FM1_DTSEC9,
	FM1_DTSEC10,
	FM1_10GEC1,
	FM1_10GEC2,
	FM1_10GEC3,
	FM1_10GEC4,
	FM2_DTSEC1,
	FM2_DTSEC2,
	FM2_DTSEC3,
	FM2_DTSEC4,
	FM2_DTSEC5,
	FM2_DTSEC6,
	FM2_DTSEC9,
	FM2_DTSEC10,
	FM2_10GEC1,
	FM2_10GEC2,
	NUM_FM_PORTS,
};

enum fm_eth_type {
	FM_ETH_1G_E,
	FM_ETH_10G_E,
};

/* Historically, on FMan v3 platforms, the first MDIO bus has been used for
 * Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the
 * TGEC name).
 *
 * On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus,
 * and no TGEC ports are present on-board.
 */
#ifdef CONFIG_SYS_FMAN_V3
#ifdef CONFIG_TARGET_LS1046AFRWY
#define CFG_SYS_FM1_DTSEC_MDIO_ADDR	(CFG_SYS_FSL_FM1_ADDR + 0xfd000)
#else
#define CFG_SYS_FM1_DTSEC_MDIO_ADDR	(CFG_SYS_FSL_FM1_ADDR + 0xfc000)
#endif
#define CFG_SYS_FM1_TGEC_MDIO_ADDR	(CFG_SYS_FSL_FM1_ADDR + 0xfd000)
#if (CFG_SYS_NUM_FMAN == 2)
#define CFG_SYS_FM2_DTSEC_MDIO_ADDR	(CFG_SYS_FSL_FM2_ADDR + 0xfc000)
#define CFG_SYS_FM2_TGEC_MDIO_ADDR	(CFG_SYS_FSL_FM2_ADDR + 0xfd000)
#endif
#else
#define CFG_SYS_FM1_DTSEC1_MDIO_ADDR	(CFG_SYS_FSL_FM1_ADDR + 0xe1120)
#define CFG_SYS_FM1_TGEC_MDIO_ADDR	(CFG_SYS_FSL_FM1_ADDR + 0xf1000)
#endif

#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
#define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"

/* Fman ethernet info struct */
#define FM_ETH_INFO_INITIALIZER(idx, pregs) \
	.fm		= idx,						\
	.phy_regs	= (void *)pregs,				\
	.enet_if	= PHY_INTERFACE_MODE_NA,			\

#ifdef CONFIG_SYS_FMAN_V3
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
{									\
	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_DTSEC_MDIO_ADDR)	\
	.index		= idx,						\
	.num		= n - 1,					\
	.type		= FM_ETH_1G_E,					\
	.port		= FM##idx##_DTSEC##n,				\
	.rx_port_id	= RX_PORT_1G_BASE + n - 1,			\
	.tx_port_id	= TX_PORT_1G_BASE + n - 1,			\
	.compat_offset	= CFG_SYS_FSL_FM##idx##_OFFSET +		\
				offsetof(struct ccsr_fman, memac[n-1]),\
}

#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{									\
	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_TGEC_MDIO_ADDR)	\
	.index		= idx,						\
	.num		= n - 1,					\
	.type		= FM_ETH_10G_E,					\
	.port		= FM##idx##_10GEC##n,				\
	.rx_port_id	= RX_PORT_10G_BASE2 + n - 1,			\
	.tx_port_id	= TX_PORT_10G_BASE2 + n - 1,			\
	.compat_offset	= CFG_SYS_FSL_FM##idx##_OFFSET +		\
				 offsetof(struct ccsr_fman, memac[n-1]),\
}
#else
#if (CFG_SYS_NUM_FMAN == 2)
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{									\
	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM2_TGEC_MDIO_ADDR)	\
	.index		= idx,						\
	.num		= n - 1,					\
	.type		= FM_ETH_10G_E,					\
	.port		= FM##idx##_10GEC##n,				\
	.rx_port_id	= RX_PORT_10G_BASE + n - 1,			\
	.tx_port_id	= TX_PORT_10G_BASE + n - 1,			\
	.compat_offset	= CFG_SYS_FSL_FM##idx##_OFFSET +		\
				offsetof(struct ccsr_fman, memac[n-1+8]),\
}
#else
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{									\
	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_TGEC_MDIO_ADDR)	\
	.index		= idx,						\
	.num		= n - 1,					\
	.type		= FM_ETH_10G_E,					\
	.port		= FM##idx##_10GEC##n,				\
	.rx_port_id	= RX_PORT_10G_BASE + n - 1,			\
	.tx_port_id	= TX_PORT_10G_BASE + n - 1,			\
	.compat_offset	= CFG_SYS_FSL_FM##idx##_OFFSET +		\
				offsetof(struct ccsr_fman, memac[n-1+8]),\
}
#endif
#endif

#if (CFG_SYS_NUM_FM1_10GEC >= 3)
#define FM_TGEC_INFO_INITIALIZER2(idx, n) \
{									\
	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_TGEC_MDIO_ADDR)	\
	.index		= idx,						\
	.num		= n - 1,					\
	.type		= FM_ETH_10G_E,					\
	.port		= FM##idx##_10GEC##n,				\
	.rx_port_id	= RX_PORT_10G_BASE2 + n - 3,			\
	.tx_port_id	= TX_PORT_10G_BASE2 + n - 3,			\
	.compat_offset	= CFG_SYS_FSL_FM##idx##_OFFSET +		\
				offsetof(struct ccsr_fman, memac[n-1-2]),\
}
#endif

#else
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
{									\
	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_DTSEC1_MDIO_ADDR)	\
	.index		= idx,						\
	.num		= n - 1,					\
	.type		= FM_ETH_1G_E,					\
	.port		= FM##idx##_DTSEC##n,				\
	.rx_port_id	= RX_PORT_1G_BASE + n - 1,			\
	.tx_port_id	= TX_PORT_1G_BASE + n - 1,			\
	.compat_offset	= CFG_SYS_FSL_FM##idx##_OFFSET +		\
				offsetof(struct ccsr_fman, mac_1g[n-1]),\
}

#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{									\
	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_TGEC_MDIO_ADDR)	\
	.index		= idx,						\
	.num		= n - 1,					\
	.type		= FM_ETH_10G_E,					\
	.port		= FM##idx##_10GEC##n,				\
	.rx_port_id	= RX_PORT_10G_BASE + n - 1,			\
	.tx_port_id	= TX_PORT_10G_BASE + n - 1,			\
	.compat_offset	= CFG_SYS_FSL_FM##idx##_OFFSET +		\
				offsetof(struct ccsr_fman, mac_10g[n-1]),\
}
#endif
struct fm_eth_info {
	u8 enabled;
	u8 fm;
	u8 num;
	u8 phy_addr;
	int index;
	u16 rx_port_id;
	u16 tx_port_id;
	enum fm_port port;
	enum fm_eth_type type;
	void *phy_regs;
	phy_interface_t enet_if;
	u32 compat_offset;
	struct mii_dev *bus;
};

struct tgec_mdio_info {
	struct tgec_mdio_controller *regs;
	char *name;
};

struct memac_mdio_info {
	struct memac_mdio_controller *regs;
	char *name;
};

int fm_tgec_mdio_init(struct bd_info *bis, struct tgec_mdio_info *info);
int fm_memac_mdio_init(struct bd_info *bis, struct memac_mdio_info *info);

void fman_enet_init(void);
void fdt_fixup_fman_ethernet(void *fdt);
phy_interface_t fm_info_get_enet_if(enum fm_port port);
void fm_info_set_phy_address(enum fm_port port, int address);
int fm_info_get_phy_address(enum fm_port port);
void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
void fm_disable_port(enum fm_port port);
void fm_enable_port(enum fm_port port);
void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
		unsigned int port_num, int phy_base_addr);
int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
		unsigned int port_num, unsigned regnum);

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
c916d7c9	2	/*
111fd19e	3	* Copyright 2009-2012 Freescale Semiconductor, Inc.
d90c7ac7	4	* Copyright 2019 NXP
c916d7c9 KG	5	*/
	6
	7	#ifndef __FM_ETH_H__
	8	#define __FM_ETH_H__
	9
93f26f13	10	#include <phy.h>
c916d7c9	11	#include <asm/types.h>
c916d7c9 KG	12
	13	enum fm_port {
	14	FM1_DTSEC1,
	15	FM1_DTSEC2,
	16	FM1_DTSEC3,
	17	FM1_DTSEC4,
	18	FM1_DTSEC5,
9e758758 YS	19	FM1_DTSEC6,
	20	FM1_DTSEC9,
	21	FM1_DTSEC10,
c916d7c9	22	FM1_10GEC1,
9e758758	23	FM1_10GEC2,
82a55c1e SL	24	FM1_10GEC3,
82a55c1e SL	25	FM1_10GEC4,
c916d7c9 KG	26	FM2_DTSEC1,
	27	FM2_DTSEC2,
	28	FM2_DTSEC3,
	29	FM2_DTSEC4,
99abf7de	30	FM2_DTSEC5,
9e758758 YS	31	FM2_DTSEC6,
	32	FM2_DTSEC9,
	33	FM2_DTSEC10,
c916d7c9	34	FM2_10GEC1,
9e758758	35	FM2_10GEC2,
c916d7c9 KG	36	NUM_FM_PORTS,
	37	};
	38
	39	enum fm_eth_type {
	40	FM_ETH_1G_E,
	41	FM_ETH_10G_E,
	42	};
	43
d90c7ac7 VS	44	/* Historically, on FMan v3 platforms, the first MDIO bus has been used for
	45	* Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the
	46	* TGEC name).
	47	*
	48	* On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus,
	49	* and no TGEC ports are present on-board.
	50	*/
111fd19e	51	#ifdef CONFIG_SYS_FMAN_V3
d90c7ac7	52	#ifdef CONFIG_TARGET_LS1046AFRWY
6e7df1d1	53	#define CFG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000)
d90c7ac7	54	#else
6e7df1d1	55	#define CFG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfc000)
d90c7ac7	56	#endif
6e7df1d1	57	#define CFG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000)
cdc5ed8f	58	#if (CFG_SYS_NUM_FMAN == 2)
6e7df1d1 TR	59	#define CFG_SYS_FM2_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfc000)
6e7df1d1 TR	60	#define CFG_SYS_FM2_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfd000)
23e1acaf	61	#endif
111fd19e	62	#else
6e7df1d1 TR	63	#define CFG_SYS_FM1_DTSEC1_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xe1120)
6e7df1d1 TR	64	#define CFG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xf1000)
111fd19e	65	#endif
c916d7c9 KG	66
	67	#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
	68	#define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
	69
	70	/* Fman ethernet info struct */
	71	#define FM_ETH_INFO_INITIALIZER(idx, pregs) \
	72	.fm = idx, \
	73	.phy_regs = (void *)pregs, \
ffb0f6f4	74	.enet_if = PHY_INTERFACE_MODE_NA, \
c916d7c9	75
111fd19e RZ	76	#ifdef CONFIG_SYS_FMAN_V3
	77	#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
	78	{ \
6e7df1d1	79	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_DTSEC_MDIO_ADDR) \
111fd19e RZ	80	.index = idx, \
	81	.num = n - 1, \
	82	.type = FM_ETH_1G_E, \
	83	.port = FM##idx##_DTSEC##n, \
	84	.rx_port_id = RX_PORT_1G_BASE + n - 1, \
	85	.tx_port_id = TX_PORT_1G_BASE + n - 1, \
6cc04547	86	.compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
111fd19e RZ	87	offsetof(struct ccsr_fman, memac[n-1]),\
	88	}
	89
cc19c25e SL	90	#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
	91	#define FM_TGEC_INFO_INITIALIZER(idx, n) \
	92	{ \
6e7df1d1	93	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_TGEC_MDIO_ADDR) \
cc19c25e SL	94	.index = idx, \
	95	.num = n - 1, \
	96	.type = FM_ETH_10G_E, \
	97	.port = FM##idx##_10GEC##n, \
	98	.rx_port_id = RX_PORT_10G_BASE2 + n - 1, \
	99	.tx_port_id = TX_PORT_10G_BASE2 + n - 1, \
6cc04547	100	.compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
cc19c25e SL	101	offsetof(struct ccsr_fman, memac[n-1]),\
	102	}
	103	#else
cdc5ed8f	104	#if (CFG_SYS_NUM_FMAN == 2)
111fd19e RZ	105	#define FM_TGEC_INFO_INITIALIZER(idx, n) \
111fd19e RZ	106	{ \
6e7df1d1	107	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM2_TGEC_MDIO_ADDR) \
111fd19e RZ	108	.index = idx, \
	109	.num = n - 1, \
	110	.type = FM_ETH_10G_E, \
	111	.port = FM##idx##_10GEC##n, \
	112	.rx_port_id = RX_PORT_10G_BASE + n - 1, \
	113	.tx_port_id = TX_PORT_10G_BASE + n - 1, \
6cc04547	114	.compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
944b6ccf	115	offsetof(struct ccsr_fman, memac[n-1+8]),\
111fd19e	116	}
23e1acaf SX	117	#else
	118	#define FM_TGEC_INFO_INITIALIZER(idx, n) \
	119	{ \
6e7df1d1	120	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_TGEC_MDIO_ADDR) \
23e1acaf SX	121	.index = idx, \
	122	.num = n - 1, \
	123	.type = FM_ETH_10G_E, \
	124	.port = FM##idx##_10GEC##n, \
	125	.rx_port_id = RX_PORT_10G_BASE + n - 1, \
	126	.tx_port_id = TX_PORT_10G_BASE + n - 1, \
6cc04547	127	.compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
23e1acaf SX	128	offsetof(struct ccsr_fman, memac[n-1+8]),\
	129	}
	130	#endif
cc19c25e	131	#endif
82a55c1e	132
cdc5ed8f	133	#if (CFG_SYS_NUM_FM1_10GEC >= 3)
82a55c1e SL	134	#define FM_TGEC_INFO_INITIALIZER2(idx, n) \
82a55c1e SL	135	{ \
6e7df1d1	136	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_TGEC_MDIO_ADDR) \
82a55c1e SL	137	.index = idx, \
	138	.num = n - 1, \
	139	.type = FM_ETH_10G_E, \
	140	.port = FM##idx##_10GEC##n, \
	141	.rx_port_id = RX_PORT_10G_BASE2 + n - 3, \
	142	.tx_port_id = TX_PORT_10G_BASE2 + n - 3, \
6cc04547	143	.compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
82a55c1e SL	144	offsetof(struct ccsr_fman, memac[n-1-2]),\
	145	}
	146	#endif
	147
111fd19e	148	#else
c916d7c9 KG	149	#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
c916d7c9 KG	150	{ \
6e7df1d1	151	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_DTSEC1_MDIO_ADDR) \
c916d7c9 KG	152	.index = idx, \
	153	.num = n - 1, \
	154	.type = FM_ETH_1G_E, \
	155	.port = FM##idx##_DTSEC##n, \
	156	.rx_port_id = RX_PORT_1G_BASE + n - 1, \
	157	.tx_port_id = TX_PORT_1G_BASE + n - 1, \
6cc04547	158	.compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
c916d7c9 KG	159	offsetof(struct ccsr_fman, mac_1g[n-1]),\
	160	}
	161
	162	#define FM_TGEC_INFO_INITIALIZER(idx, n) \
	163	{ \
6e7df1d1	164	FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_TGEC_MDIO_ADDR) \
c916d7c9 KG	165	.index = idx, \
	166	.num = n - 1, \
	167	.type = FM_ETH_10G_E, \
	168	.port = FM##idx##_10GEC##n, \
	169	.rx_port_id = RX_PORT_10G_BASE + n - 1, \
	170	.tx_port_id = TX_PORT_10G_BASE + n - 1, \
6cc04547	171	.compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
c916d7c9 KG	172	offsetof(struct ccsr_fman, mac_10g[n-1]),\
c916d7c9 KG	173	}
111fd19e	174	#endif
c916d7c9 KG	175	struct fm_eth_info {
	176	u8 enabled;
	177	u8 fm;
	178	u8 num;
	179	u8 phy_addr;
	180	int index;
	181	u16 rx_port_id;
	182	u16 tx_port_id;
	183	enum fm_port port;
	184	enum fm_eth_type type;
	185	void *phy_regs;
	186	phy_interface_t enet_if;
	187	u32 compat_offset;
	188	struct mii_dev *bus;
	189	};
	190
	191	struct tgec_mdio_info {
	192	struct tgec_mdio_controller *regs;
	193	char *name;
	194	};
	195
111fd19e RZ	196	struct memac_mdio_info {
	197	struct memac_mdio_controller *regs;
	198	char *name;
	199	};
	200
b75d8dc5 MY	201	int fm_tgec_mdio_init(struct bd_info bis, struct tgec_mdio_info info);
b75d8dc5 MY	202	int fm_memac_mdio_init(struct bd_info bis, struct memac_mdio_info info);
111fd19e	203
c916d7c9 KG	204	void fman_enet_init(void);
	205	void fdt_fixup_fman_ethernet(void *fdt);
	206	phy_interface_t fm_info_get_enet_if(enum fm_port port);
	207	void fm_info_set_phy_address(enum fm_port port, int address);
ae2291fb	208	int fm_info_get_phy_address(enum fm_port port);
c916d7c9	209	void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
69a85242	210	void fm_disable_port(enum fm_port port);
f51d3b71	211	void fm_enable_port(enum fm_port port);
ffee1dde ZQ	212	void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
	213	unsigned int port_num, int phy_base_addr);
	214	int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
	215	unsigned int port_num, unsigned regnum);
c916d7c9 KG	216
c916d7c9 KG	217	#endif