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717b5aad WD |
1 | /* |
2 | * NS16550 Serial Port | |
a47a12be | 3 | * originally from linux source (arch/powerpc/boot/ns16550.h) |
200779e3 DZ |
4 | * |
5 | * Cleanup and unification | |
6 | * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH | |
7 | * | |
717b5aad | 8 | * modified slightly to |
6d0f6bcf | 9 | * have addresses as offsets from CONFIG_SYS_ISA_BASE |
717b5aad WD |
10 | * added a few more definitions |
11 | * added prototypes for ns16550.c | |
12 | * reduced no of com ports to 2 | |
13 | * modifications (c) Rob Taylor, Flying Pig Systems. 2000. | |
b87dfd28 | 14 | * |
f5e0d039 HS |
15 | * added support for port on 64-bit bus |
16 | * by Richard Danter ([email protected]), (C) 2005 Wind River Systems | |
717b5aad WD |
17 | */ |
18 | ||
453c0d75 DZ |
19 | /* |
20 | * Note that the following macro magic uses the fact that the compiler | |
21 | * will not allocate storage for arrays of size 0 | |
22 | */ | |
23 | ||
79df1208 DA |
24 | #include <linux/types.h> |
25 | ||
12e431b2 SG |
26 | #ifdef CONFIG_DM_SERIAL |
27 | /* | |
28 | * For driver model we always use one byte per register, and sort out the | |
29 | * differences in the driver | |
30 | */ | |
31 | #define CONFIG_SYS_NS16550_REG_SIZE (-1) | |
32 | #endif | |
33 | ||
62cbde4c SG |
34 | #ifdef CONFIG_NS16550_DYNAMIC |
35 | #define UART_REG(x) unsigned char x | |
36 | #else | |
453c0d75 | 37 | #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) |
717b5aad | 38 | #error "Please define NS16550 registers size." |
90914008 | 39 | #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL) |
79df1208 | 40 | #define UART_REG(x) u32 x |
453c0d75 DZ |
41 | #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) |
42 | #define UART_REG(x) \ | |
43 | unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ | |
44 | unsigned char x; | |
45 | #elif (CONFIG_SYS_NS16550_REG_SIZE < 0) | |
46 | #define UART_REG(x) \ | |
47 | unsigned char x; \ | |
48 | unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; | |
717b5aad | 49 | #endif |
62cbde4c SG |
50 | #endif /* CONFIG_NS16550_DYNAMIC */ |
51 | ||
52 | enum ns16550_flags { | |
53 | NS16550_FLAG_IO = 1 << 0, /* Use I/O access (else mem-mapped) */ | |
54 | NS16550_FLAG_ENDIAN = 1 << 1, /* Use out_le/be_32() */ | |
55 | NS16550_FLAG_BE = 1 << 2, /* Big-endian access (else little) */ | |
56 | }; | |
717b5aad | 57 | |
12e431b2 SG |
58 | /** |
59 | * struct ns16550_platdata - information about a NS16550 port | |
60 | * | |
61 | * @base: Base register address | |
62cbde4c | 62 | * @reg_width: IO accesses size of registers (in bytes, 1 or 4) |
12e431b2 | 63 | * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) |
62cbde4c | 64 | * @reg_offset: Offset to start of registers (normally 0) |
12e431b2 | 65 | * @clock: UART base clock speed in Hz |
62cbde4c SG |
66 | * @fcr: Offset of FCR register (normally UART_FCR_DEFVAL) |
67 | * @flags: A few flags (enum ns16550_flags) | |
4e8de068 | 68 | * @bdf: PCI slot/function (pci_dev_t) |
12e431b2 SG |
69 | */ |
70 | struct ns16550_platdata { | |
167efe01 | 71 | unsigned long base; |
4e720779 | 72 | int reg_width; |
12e431b2 | 73 | int reg_shift; |
59b35ddd | 74 | int reg_offset; |
0af76162 | 75 | int clock; |
65f83802 | 76 | u32 fcr; |
62cbde4c | 77 | int flags; |
4e8de068 SG |
78 | #if defined(CONFIG_PCI) && defined(CONFIG_SPL) |
79 | int bdf; | |
80 | #endif | |
12e431b2 SG |
81 | }; |
82 | ||
83 | struct udevice; | |
84 | ||
453c0d75 DZ |
85 | struct NS16550 { |
86 | UART_REG(rbr); /* 0 */ | |
87 | UART_REG(ier); /* 1 */ | |
88 | UART_REG(fcr); /* 2 */ | |
89 | UART_REG(lcr); /* 3 */ | |
90 | UART_REG(mcr); /* 4 */ | |
91 | UART_REG(lsr); /* 5 */ | |
92 | UART_REG(msr); /* 6 */ | |
93 | UART_REG(spr); /* 7 */ | |
99b603e7 MK |
94 | #ifdef CONFIG_SOC_DA8XX |
95 | UART_REG(reg8); /* 8 */ | |
96 | UART_REG(reg9); /* 9 */ | |
97 | UART_REG(revid1); /* A */ | |
98 | UART_REG(revid2); /* B */ | |
99 | UART_REG(pwr_mgmt); /* C */ | |
100 | UART_REG(mdr1); /* D */ | |
101 | #else | |
453c0d75 DZ |
102 | UART_REG(mdr1); /* 8 */ |
103 | UART_REG(reg9); /* 9 */ | |
104 | UART_REG(regA); /* A */ | |
105 | UART_REG(regB); /* B */ | |
106 | UART_REG(regC); /* C */ | |
107 | UART_REG(regD); /* D */ | |
108 | UART_REG(regE); /* E */ | |
109 | UART_REG(uasr); /* F */ | |
110 | UART_REG(scr); /* 10*/ | |
111 | UART_REG(ssr); /* 11*/ | |
99b603e7 | 112 | #endif |
12e431b2 SG |
113 | #ifdef CONFIG_DM_SERIAL |
114 | struct ns16550_platdata *plat; | |
115 | #endif | |
453c0d75 DZ |
116 | }; |
117 | ||
717b5aad WD |
118 | #define thr rbr |
119 | #define iir fcr | |
120 | #define dll rbr | |
121 | #define dlm ier | |
122 | ||
f8df9d0d | 123 | typedef struct NS16550 *NS16550_t; |
717b5aad | 124 | |
200779e3 DZ |
125 | /* |
126 | * These are the definitions for the FIFO Control Register | |
127 | */ | |
f8df9d0d | 128 | #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ |
200779e3 DZ |
129 | #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ |
130 | #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ | |
131 | #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ | |
132 | #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ | |
133 | #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ | |
134 | #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ | |
135 | #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ | |
136 | #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ | |
137 | ||
138 | #define UART_FCR_RXSR 0x02 /* Receiver soft reset */ | |
139 | #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ | |
140 | ||
0b060eef MV |
141 | /* Ingenic JZ47xx specific UART-enable bit. */ |
142 | #define UART_FCR_UME 0x10 | |
143 | ||
17fa0326 HS |
144 | /* Clear & enable FIFOs */ |
145 | #define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \ | |
146 | UART_FCR_RXSR | \ | |
147 | UART_FCR_TXSR) | |
148 | ||
200779e3 DZ |
149 | /* |
150 | * These are the definitions for the Modem Control Register | |
151 | */ | |
152 | #define UART_MCR_DTR 0x01 /* DTR */ | |
153 | #define UART_MCR_RTS 0x02 /* RTS */ | |
154 | #define UART_MCR_OUT1 0x04 /* Out 1 */ | |
155 | #define UART_MCR_OUT2 0x08 /* Out 2 */ | |
156 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ | |
d57dee57 | 157 | #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ |
200779e3 DZ |
158 | |
159 | #define UART_MCR_DMA_EN 0x04 | |
160 | #define UART_MCR_TX_DFR 0x08 | |
161 | ||
162 | /* | |
163 | * These are the definitions for the Line Control Register | |
164 | * | |
165 | * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting | |
166 | * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. | |
167 | */ | |
168 | #define UART_LCR_WLS_MSK 0x03 /* character length select mask */ | |
169 | #define UART_LCR_WLS_5 0x00 /* 5 bit character length */ | |
170 | #define UART_LCR_WLS_6 0x01 /* 6 bit character length */ | |
171 | #define UART_LCR_WLS_7 0x02 /* 7 bit character length */ | |
172 | #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ | |
f8df9d0d | 173 | #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ |
200779e3 DZ |
174 | #define UART_LCR_PEN 0x08 /* Parity eneble */ |
175 | #define UART_LCR_EPS 0x10 /* Even Parity Select */ | |
176 | #define UART_LCR_STKP 0x20 /* Stick Parity */ | |
177 | #define UART_LCR_SBRK 0x40 /* Set Break */ | |
178 | #define UART_LCR_BKSE 0x80 /* Bank select enable */ | |
179 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ | |
180 | ||
181 | /* | |
182 | * These are the definitions for the Line Status Register | |
183 | */ | |
184 | #define UART_LSR_DR 0x01 /* Data ready */ | |
185 | #define UART_LSR_OE 0x02 /* Overrun */ | |
186 | #define UART_LSR_PE 0x04 /* Parity error */ | |
187 | #define UART_LSR_FE 0x08 /* Framing error */ | |
188 | #define UART_LSR_BI 0x10 /* Break */ | |
189 | #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ | |
190 | #define UART_LSR_TEMT 0x40 /* Xmitter empty */ | |
191 | #define UART_LSR_ERR 0x80 /* Error */ | |
192 | ||
193 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ | |
194 | #define UART_MSR_RI 0x40 /* Ring Indicator */ | |
195 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ | |
196 | #define UART_MSR_CTS 0x10 /* Clear to Send */ | |
197 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ | |
198 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ | |
199 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ | |
200 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ | |
201 | ||
202 | /* | |
203 | * These are the definitions for the Interrupt Identification Register | |
204 | */ | |
205 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
206 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
207 | ||
208 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
209 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
210 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
211 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
212 | ||
213 | /* | |
214 | * These are the definitions for the Interrupt Enable Register | |
215 | */ | |
216 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
217 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
218 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
219 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
220 | ||
717b5aad | 221 | /* useful defaults for LCR */ |
200779e3 | 222 | #define UART_LCR_8N1 0x03 |
717b5aad | 223 | |
f8df9d0d SG |
224 | void NS16550_init(NS16550_t com_port, int baud_divisor); |
225 | void NS16550_putc(NS16550_t com_port, char c); | |
226 | char NS16550_getc(NS16550_t com_port); | |
227 | int NS16550_tstc(NS16550_t com_port); | |
228 | void NS16550_reinit(NS16550_t com_port, int baud_divisor); | |
fa54eb12 SG |
229 | |
230 | /** | |
231 | * ns16550_calc_divisor() - calculate the divisor given clock and baud rate | |
232 | * | |
233 | * Given the UART input clock and required baudrate, calculate the divisor | |
234 | * that should be used. | |
235 | * | |
236 | * @port: UART port | |
237 | * @clock: UART input clock speed in Hz | |
238 | * @baudrate: Required baud rate | |
239 | * @return baud rate divisor that should be used | |
240 | */ | |
241 | int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate); | |
12e431b2 SG |
242 | |
243 | /** | |
244 | * ns16550_serial_ofdata_to_platdata() - convert DT to platform data | |
245 | * | |
246 | * Decode a device tree node for an ns16550 device. This includes the | |
247 | * register base address and register shift properties. The caller must set | |
248 | * up the clock frequency. | |
249 | * | |
250 | * @dev: dev to decode platform data for | |
251 | * @return: 0 if OK, -EINVAL on error | |
252 | */ | |
253 | int ns16550_serial_ofdata_to_platdata(struct udevice *dev); | |
254 | ||
255 | /** | |
256 | * ns16550_serial_probe() - probe a serial port | |
257 | * | |
258 | * This sets up the serial port ready for use, except for the baud rate | |
259 | * @return 0, or -ve on error | |
260 | */ | |
261 | int ns16550_serial_probe(struct udevice *dev); | |
262 | ||
263 | /** | |
264 | * struct ns16550_serial_ops - ns16550 serial operations | |
265 | * | |
266 | * These should be used by the client driver for the driver's 'ops' member | |
267 | */ | |
268 | extern const struct dm_serial_ops ns16550_serial_ops; |