projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 062ef1a6 | 1 | /* |
| f4c3917a | 2 | + * Copyright 2014 Freescale Semiconductor, Inc. |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | + */ | |
| 062ef1a6 PJ |
6 | |
| 7 | #ifndef __CONFIG_H | |
| 8 | #define __CONFIG_H | |
| 9 | ||
| 10 | /* | |
| f4c3917a | 11 | * T104x RDB board configuration file |
| 062ef1a6 | 12 | */ |
| 9f074e67 PK |
13 | #include <asm/config_mpc85xx.h> |
| 14 | ||
| 062ef1a6 | 15 | #ifdef CONFIG_RAMBOOT_PBL |
| aa36c84e SG |
16 | |
| 17 | #ifndef CONFIG_SECURE_BOOT | |
| 18c01445 | 18 | #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg |
| aa36c84e SG |
19 | #else |
| 20 | #define CONFIG_SYS_FSL_PBL_PBI \ | |
| 21 | $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg | |
| 22 | #endif | |
| 23 | ||
| 18c01445 PK |
24 | #define CONFIG_SPL_FLUSH_IMAGE |
| 25 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 18c01445 PK |
26 | #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 |
| 27 | #define CONFIG_SPL_PAD_TO 0x40000 | |
| 28 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
| 29 | #ifdef CONFIG_SPL_BUILD | |
| 30 | #define CONFIG_SPL_SKIP_RELOCATE | |
| 31 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 32 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
| 18c01445 PK |
33 | #endif |
| 34 | #define RESET_VECTOR_OFFSET 0x27FFC | |
| 35 | #define BOOT_PAGE_OFFSET 0x27000 | |
| 36 | ||
| 37 | #ifdef CONFIG_NAND | |
| aa36c84e SG |
38 | #ifdef CONFIG_SECURE_BOOT |
| 39 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) | |
| 40 | /* | |
| 41 | * HDR would be appended at end of image and copied to DDR along | |
| 42 | * with U-Boot image. | |
| 43 | */ | |
| 44 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ | |
| 45 | CONFIG_U_BOOT_HDR_SIZE) | |
| 46 | #else | |
| 18c01445 | 47 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
| aa36c84e | 48 | #endif |
| ce249d95 TY |
49 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 |
| 50 | #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 | |
| 18c01445 PK |
51 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) |
| 52 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
| 6fcddd09 | 53 | #ifdef CONFIG_TARGET_T1040RDB |
| ec90ac73 ZQ |
54 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 55 | $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg | |
| 56 | #endif | |
| 55ed8ae3 | 57 | #ifdef CONFIG_TARGET_T1042RDB_PI |
| ec90ac73 ZQ |
58 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 59 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg | |
| 60 | #endif | |
| 0167369c | 61 | #ifdef CONFIG_TARGET_T1042RDB |
| ec90ac73 ZQ |
62 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 63 | $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg | |
| 64 | #endif | |
| a016735c | 65 | #ifdef CONFIG_TARGET_T1040D4RDB |
| ec90ac73 ZQ |
66 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 67 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg | |
| 68 | #endif | |
| 319ed24a | 69 | #ifdef CONFIG_TARGET_T1042D4RDB |
| ec90ac73 ZQ |
70 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 71 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg | |
| 72 | #endif | |
| 18c01445 PK |
73 | #define CONFIG_SPL_NAND_BOOT |
| 74 | #endif | |
| 75 | ||
| 76 | #ifdef CONFIG_SPIFLASH | |
| ce249d95 | 77 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
| 18c01445 PK |
78 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| 79 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) | |
| ce249d95 TY |
80 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) |
| 81 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) | |
| 18c01445 PK |
82 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) |
| 83 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
| 84 | #ifndef CONFIG_SPL_BUILD | |
| 85 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 86 | #endif | |
| 6fcddd09 | 87 | #ifdef CONFIG_TARGET_T1040RDB |
| ec90ac73 ZQ |
88 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 89 | $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg | |
| 90 | #endif | |
| 55ed8ae3 | 91 | #ifdef CONFIG_TARGET_T1042RDB_PI |
| ec90ac73 ZQ |
92 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 93 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg | |
| 94 | #endif | |
| 0167369c | 95 | #ifdef CONFIG_TARGET_T1042RDB |
| ec90ac73 ZQ |
96 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 97 | $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg | |
| 98 | #endif | |
| a016735c | 99 | #ifdef CONFIG_TARGET_T1040D4RDB |
| ec90ac73 ZQ |
100 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 101 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg | |
| 102 | #endif | |
| 319ed24a | 103 | #ifdef CONFIG_TARGET_T1042D4RDB |
| ec90ac73 ZQ |
104 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 105 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg | |
| 106 | #endif | |
| 18c01445 PK |
107 | #define CONFIG_SPL_SPI_BOOT |
| 108 | #endif | |
| 109 | ||
| 110 | #ifdef CONFIG_SDCARD | |
| ce249d95 | 111 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
| 18c01445 PK |
112 | #define CONFIG_SPL_MMC_MINIMAL |
| 113 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) | |
| ce249d95 TY |
114 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) |
| 115 | #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) | |
| 18c01445 PK |
116 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) |
| 117 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
| 118 | #ifndef CONFIG_SPL_BUILD | |
| 119 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 120 | #endif | |
| 6fcddd09 | 121 | #ifdef CONFIG_TARGET_T1040RDB |
| ec90ac73 ZQ |
122 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 123 | $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg | |
| 124 | #endif | |
| 55ed8ae3 | 125 | #ifdef CONFIG_TARGET_T1042RDB_PI |
| ec90ac73 ZQ |
126 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 127 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg | |
| 128 | #endif | |
| 0167369c | 129 | #ifdef CONFIG_TARGET_T1042RDB |
| ec90ac73 ZQ |
130 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 131 | $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg | |
| 132 | #endif | |
| a016735c | 133 | #ifdef CONFIG_TARGET_T1040D4RDB |
| ec90ac73 ZQ |
134 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 135 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg | |
| 136 | #endif | |
| 319ed24a | 137 | #ifdef CONFIG_TARGET_T1042D4RDB |
| ec90ac73 ZQ |
138 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 139 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg | |
| 140 | #endif | |
| 18c01445 PK |
141 | #define CONFIG_SPL_MMC_BOOT |
| 142 | #endif | |
| 143 | ||
| 062ef1a6 PJ |
144 | #endif |
| 145 | ||
| 146 | /* High Level Configuration Options */ | |
| 062ef1a6 | 147 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
| 062ef1a6 PJ |
148 | #define CONFIG_MP /* support multiple processors */ |
| 149 | ||
| 5303a3de TY |
150 | /* support deep sleep */ |
| 151 | #define CONFIG_DEEP_SLEEP | |
| 5303a3de | 152 | |
| 062ef1a6 PJ |
153 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 154 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 155 | #endif | |
| 156 | ||
| 157 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
| 51370d56 | 158 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
| 062ef1a6 | 159 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| b38eaec5 RD |
160 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 161 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
| 162 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
| 163 | #define CONFIG_PCIE4 /* PCIE controller 4 */ | |
| 062ef1a6 PJ |
164 | |
| 165 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
| 166 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
| 167 | ||
| 062ef1a6 PJ |
168 | #define CONFIG_ENV_OVERWRITE |
| 169 | ||
| e856bdcf | 170 | #ifdef CONFIG_MTD_NOR_FLASH |
| 062ef1a6 PJ |
171 | #define CONFIG_FLASH_CFI_DRIVER |
| 172 | #define CONFIG_SYS_FLASH_CFI | |
| 173 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 174 | #endif | |
| 175 | ||
| 062ef1a6 PJ |
176 | #if defined(CONFIG_SPIFLASH) |
| 177 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 062ef1a6 PJ |
178 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| 179 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 180 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 181 | #elif defined(CONFIG_SDCARD) | |
| 182 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 062ef1a6 PJ |
183 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 184 | #define CONFIG_ENV_SIZE 0x2000 | |
| 18c01445 | 185 | #define CONFIG_ENV_OFFSET (512 * 0x800) |
| 062ef1a6 | 186 | #elif defined(CONFIG_NAND) |
| aa36c84e SG |
187 | #ifdef CONFIG_SECURE_BOOT |
| 188 | #define CONFIG_RAMBOOT_NAND | |
| 189 | #define CONFIG_BOOTSCRIPT_COPY_RAM | |
| 190 | #endif | |
| 062ef1a6 | 191 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| 18c01445 | 192 | #define CONFIG_ENV_SIZE 0x2000 |
| e222b1f3 | 193 | #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 062ef1a6 | 194 | #else |
| 062ef1a6 PJ |
195 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 196 | #define CONFIG_ENV_SIZE 0x2000 | |
| 197 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 198 | #endif | |
| 062ef1a6 PJ |
199 | |
| 200 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
| 201 | #define CONFIG_DDR_CLK_FREQ 66666666 | |
| 202 | ||
| 203 | /* | |
| 204 | * These can be toggled for performance analysis, otherwise use default. | |
| 205 | */ | |
| 206 | #define CONFIG_SYS_CACHE_STASHING | |
| 207 | #define CONFIG_BACKSIDE_L2_CACHE | |
| 208 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
| 209 | #define CONFIG_BTB /* toggle branch predition */ | |
| 210 | #define CONFIG_DDR_ECC | |
| 211 | #ifdef CONFIG_DDR_ECC | |
| 212 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 213 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 214 | #endif | |
| 215 | ||
| 216 | #define CONFIG_ENABLE_36BIT_PHYS | |
| 217 | ||
| 218 | #define CONFIG_ADDR_MAP | |
| 219 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
| 220 | ||
| 221 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
| 222 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| 223 | #define CONFIG_SYS_ALT_MEMTEST | |
| 062ef1a6 PJ |
224 | |
| 225 | /* | |
| 226 | * Config the L3 Cache as L3 SRAM | |
| 227 | */ | |
| 228 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 | |
| aa36c84e SG |
229 | /* |
| 230 | * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence | |
| 231 | * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address | |
| 232 | * (CONFIG_SYS_INIT_L3_VADDR) will be different. | |
| 233 | */ | |
| 234 | #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 | |
| 18c01445 | 235 | #define CONFIG_SYS_L3_SIZE 256 << 10 |
| aa36c84e | 236 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) |
| 18c01445 PK |
237 | #ifdef CONFIG_RAMBOOT_PBL |
| 238 | #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) | |
| 239 | #endif | |
| 240 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) | |
| 241 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) | |
| 242 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) | |
| 243 | #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) | |
| 062ef1a6 PJ |
244 | |
| 245 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
| 246 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
| 247 | ||
| 248 | /* | |
| 249 | * DDR Setup | |
| 250 | */ | |
| 251 | #define CONFIG_VERY_BIG_RAM | |
| 252 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 253 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 254 | ||
| 062ef1a6 | 255 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 96ac18c9 | 256 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| 062ef1a6 PJ |
257 | |
| 258 | #define CONFIG_DDR_SPD | |
| 062ef1a6 PJ |
259 | |
| 260 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
| 261 | #define SPD_EEPROM_ADDRESS 0x51 | |
| 262 | ||
| 263 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
| 264 | ||
| 265 | /* | |
| 266 | * IFC Definitions | |
| 267 | */ | |
| 268 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 | |
| 269 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
| 270 | ||
| 271 | #define CONFIG_SYS_NOR_CSPR_EXT (0xf) | |
| 272 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ | |
| 273 | CSPR_PORT_SIZE_16 | \ | |
| 274 | CSPR_MSEL_NOR | \ | |
| 275 | CSPR_V) | |
| 276 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
| 377ffcfa SS |
277 | |
| 278 | /* | |
| 279 | * TDM Definition | |
| 280 | */ | |
| 281 | #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 | |
| 282 | ||
| 062ef1a6 PJ |
283 | /* NOR Flash Timing Params */ |
| 284 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
| 285 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
| 286 | FTIM0_NOR_TEADC(0x5) | \ | |
| 287 | FTIM0_NOR_TEAHC(0x5)) | |
| 288 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
| 289 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
| 290 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
| 291 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
| 292 | FTIM2_NOR_TCH(0x4) | \ | |
| 293 | FTIM2_NOR_TWPH(0x0E) | \ | |
| 294 | FTIM2_NOR_TWP(0x1c)) | |
| 295 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
| 296 | ||
| 297 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 298 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 299 | ||
| 300 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 301 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 302 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 303 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 304 | ||
| 305 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 306 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
| 307 | ||
| 308 | /* CPLD on IFC */ | |
| 55153d6c PK |
309 | #define CPLD_LBMAP_MASK 0x3F |
| 310 | #define CPLD_BANK_SEL_MASK 0x07 | |
| 311 | #define CPLD_BANK_OVERRIDE 0x40 | |
| 312 | #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ | |
| 313 | #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ | |
| 314 | #define CPLD_LBMAP_RESET 0xFF | |
| 315 | #define CPLD_LBMAP_SHIFT 0x03 | |
| 4b6067ae | 316 | |
| 55ed8ae3 | 317 | #if defined(CONFIG_TARGET_T1042RDB_PI) |
| cf8ddacf | 318 | #define CPLD_DIU_SEL_DFP 0x80 |
| 319ed24a | 319 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
| 4b6067ae PJ |
320 | #define CPLD_DIU_SEL_DFP 0xc0 |
| 321 | #endif | |
| 322 | ||
| a016735c | 323 | #if defined(CONFIG_TARGET_T1040D4RDB) |
| 4b6067ae PJ |
324 | #define CPLD_INT_MASK_ALL 0xFF |
| 325 | #define CPLD_INT_MASK_THERM 0x80 | |
| 326 | #define CPLD_INT_MASK_DVI_DFP 0x40 | |
| 327 | #define CPLD_INT_MASK_QSGMII1 0x20 | |
| 328 | #define CPLD_INT_MASK_QSGMII2 0x10 | |
| 329 | #define CPLD_INT_MASK_SGMI1 0x08 | |
| 330 | #define CPLD_INT_MASK_SGMI2 0x04 | |
| 331 | #define CPLD_INT_MASK_TDMR1 0x02 | |
| 332 | #define CPLD_INT_MASK_TDMR2 0x01 | |
| cf8ddacf | 333 | #endif |
| 55153d6c | 334 | |
| 062ef1a6 PJ |
335 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 |
| 336 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) | |
| 9b444be3 | 337 | #define CONFIG_SYS_CSPR2_EXT (0xf) |
| 062ef1a6 PJ |
338 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ |
| 339 | | CSPR_PORT_SIZE_8 \ | |
| 340 | | CSPR_MSEL_GPCM \ | |
| 341 | | CSPR_V) | |
| 342 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) | |
| 343 | #define CONFIG_SYS_CSOR2 0x0 | |
| 344 | /* CPLD Timing parameters for IFC CS2 */ | |
| 345 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 346 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 347 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 348 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
| 349 | FTIM1_GPCM_TRAD(0x1f)) | |
| 350 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
| de519163 | 351 | FTIM2_GPCM_TCH(0x8) | \ |
| 062ef1a6 PJ |
352 | FTIM2_GPCM_TWP(0x1f)) |
| 353 | #define CONFIG_SYS_CS2_FTIM3 0x0 | |
| 354 | ||
| 355 | /* NAND Flash on IFC */ | |
| 356 | #define CONFIG_NAND_FSL_IFC | |
| 357 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 358 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
| 359 | ||
| 360 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
| 361 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 362 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
| 363 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 364 | | CSPR_V) | |
| 365 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| 366 | ||
| 367 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 368 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 369 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 370 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
| 371 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
| 372 | | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ | |
| 373 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
| 374 | ||
| 375 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 376 | ||
| 377 | /* ONFI NAND Flash mode0 Timing Params */ | |
| 378 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
| 379 | FTIM0_NAND_TWP(0x18) | \ | |
| 380 | FTIM0_NAND_TWCHT(0x07) | \ | |
| 381 | FTIM0_NAND_TWH(0x0a)) | |
| 382 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
| 383 | FTIM1_NAND_TWBE(0x39) | \ | |
| 384 | FTIM1_NAND_TRR(0x0e) | \ | |
| 385 | FTIM1_NAND_TRP(0x18)) | |
| 386 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
| 387 | FTIM2_NAND_TREH(0x0a) | \ | |
| 388 | FTIM2_NAND_TWHRE(0x1e)) | |
| 389 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 390 | ||
| 391 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
| 392 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 393 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 062ef1a6 PJ |
394 | |
| 395 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
| 396 | ||
| 397 | #if defined(CONFIG_NAND) | |
| 398 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 399 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 400 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 401 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 402 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 403 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 404 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 405 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 406 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT | |
| 407 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
| 408 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 409 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 410 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 411 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 412 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 413 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 414 | #else | |
| 415 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT | |
| 416 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR | |
| 417 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 418 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 419 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 420 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 421 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 422 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 423 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 424 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
| 425 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
| 426 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
| 427 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 428 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 429 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 430 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 431 | #endif | |
| 432 | ||
| 18c01445 PK |
433 | #ifdef CONFIG_SPL_BUILD |
| 434 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
| 435 | #else | |
| 436 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 437 | #endif | |
| 062ef1a6 PJ |
438 | |
| 439 | #if defined(CONFIG_RAMBOOT_PBL) | |
| 440 | #define CONFIG_SYS_RAMBOOT | |
| 441 | #endif | |
| 442 | ||
| 9f074e67 PK |
443 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 |
| 444 | #if defined(CONFIG_NAND) | |
| 445 | #define CONFIG_A008044_WORKAROUND | |
| 446 | #endif | |
| 447 | #endif | |
| 448 | ||
| 062ef1a6 PJ |
449 | #define CONFIG_BOARD_EARLY_INIT_R |
| 450 | #define CONFIG_MISC_INIT_R | |
| 451 | ||
| 452 | #define CONFIG_HWCONFIG | |
| 453 | ||
| 454 | /* define to use L1 as initial stack */ | |
| 455 | #define CONFIG_L1_INIT_RAM | |
| 456 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 457 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
| 458 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
| b3142e2c | 459 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
| 062ef1a6 PJ |
460 | /* The assembler doesn't like typecast */ |
| 461 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
| 462 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
| 463 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
| 464 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
| 465 | ||
| 466 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 467 | GENERATED_GBL_DATA_SIZE) | |
| 468 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 469 | ||
| 9307cbab | 470 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 062ef1a6 PJ |
471 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
| 472 | ||
| 473 | /* Serial Port - controlled on board with jumper J8 | |
| 474 | * open - index 2 | |
| 475 | * shorted - index 1 | |
| 476 | */ | |
| 477 | #define CONFIG_CONS_INDEX 1 | |
| 062ef1a6 PJ |
478 | #define CONFIG_SYS_NS16550_SERIAL |
| 479 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 480 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
| 481 | ||
| 482 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 483 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 484 | ||
| 485 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
| 486 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
| 487 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
| 488 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
| 062ef1a6 | 489 | |
| 319ed24a | 490 | #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) |
| cf8ddacf JJ |
491 | /* Video */ |
| 492 | #define CONFIG_FSL_DIU_FB | |
| 493 | ||
| 494 | #ifdef CONFIG_FSL_DIU_FB | |
| 495 | #define CONFIG_FSL_DIU_CH7301 | |
| 496 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) | |
| cf8ddacf JJ |
497 | #define CONFIG_VIDEO_LOGO |
| 498 | #define CONFIG_VIDEO_BMP_LOGO | |
| 499 | #endif | |
| 500 | #endif | |
| 501 | ||
| 062ef1a6 PJ |
502 | /* I2C */ |
| 503 | #define CONFIG_SYS_I2C | |
| 504 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ | |
| 505 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ | |
| b0d97cd2 SL |
506 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| 507 | #define CONFIG_SYS_FSL_I2C3_SPEED 400000 | |
| 508 | #define CONFIG_SYS_FSL_I2C4_SPEED 400000 | |
| 062ef1a6 | 509 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 062ef1a6 | 510 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| b0d97cd2 SL |
511 | #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F |
| 512 | #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F | |
| 062ef1a6 | 513 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
| b0d97cd2 SL |
514 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
| 515 | #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 | |
| 516 | #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 | |
| 062ef1a6 PJ |
517 | |
| 518 | /* I2C bus multiplexer */ | |
| 519 | #define I2C_MUX_PCA_ADDR 0x70 | |
| 520 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| f4c3917a | 521 | |
| 78e56995 YS |
522 | #if defined(CONFIG_TARGET_T1042RDB_PI) || \ |
| 523 | defined(CONFIG_TARGET_T1040D4RDB) || \ | |
| 524 | defined(CONFIG_TARGET_T1042D4RDB) | |
| cf8ddacf JJ |
525 | /* LDI/DVI Encoder for display */ |
| 526 | #define CONFIG_SYS_I2C_LDI_ADDR 0x38 | |
| 527 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 | |
| 528 | ||
| f4c3917a | 529 | /* |
| 530 | * RTC configuration | |
| 531 | */ | |
| 532 | #define RTC | |
| 533 | #define CONFIG_RTC_DS1337 1 | |
| 534 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 062ef1a6 | 535 | |
| f4c3917a | 536 | /*DVI encoder*/ |
| 537 | #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 | |
| 538 | #endif | |
| 062ef1a6 PJ |
539 | |
| 540 | /* | |
| 541 | * eSPI - Enhanced SPI | |
| 542 | */ | |
| 7172de33 | 543 | #define CONFIG_SPI_FLASH_BAR |
| 062ef1a6 PJ |
544 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| 545 | #define CONFIG_SF_DEFAULT_MODE 0 | |
| 9b444be3 PJ |
546 | #define CONFIG_ENV_SPI_BUS 0 |
| 547 | #define CONFIG_ENV_SPI_CS 0 | |
| 548 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
| 549 | #define CONFIG_ENV_SPI_MODE 0 | |
| 062ef1a6 PJ |
550 | |
| 551 | /* | |
| 552 | * General PCI | |
| 553 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 554 | */ | |
| 555 | ||
| 556 | #ifdef CONFIG_PCI | |
| 557 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
| 558 | #ifdef CONFIG_PCIE1 | |
| 559 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
| 560 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
| 561 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
| 562 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
| 563 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
| 564 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 565 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
| 566 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
| 567 | #endif | |
| 568 | ||
| 569 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
| 570 | #ifdef CONFIG_PCIE2 | |
| 571 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 | |
| 572 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
| 573 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull | |
| 574 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
| 575 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
| 576 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| 577 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
| 578 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
| 579 | #endif | |
| 580 | ||
| 581 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
| 582 | #ifdef CONFIG_PCIE3 | |
| 583 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 | |
| 584 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
| 585 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
| 586 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
| 587 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
| 588 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
| 589 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
| 590 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
| 591 | #endif | |
| 592 | ||
| 593 | /* controller 4, Base address 203000 */ | |
| 594 | #ifdef CONFIG_PCIE4 | |
| 595 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 | |
| 596 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
| 597 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull | |
| 598 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ | |
| 599 | #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 | |
| 600 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
| 601 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
| 602 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
| 603 | #endif | |
| 604 | ||
| 062ef1a6 | 605 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 062ef1a6 PJ |
606 | #endif /* CONFIG_PCI */ |
| 607 | ||
| 608 | /* SATA */ | |
| 609 | #define CONFIG_FSL_SATA_V2 | |
| 610 | #ifdef CONFIG_FSL_SATA_V2 | |
| 062ef1a6 PJ |
611 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
| 612 | #define CONFIG_SATA1 | |
| 613 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 614 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 615 | ||
| 616 | #define CONFIG_LBA48 | |
| 062ef1a6 PJ |
617 | #endif |
| 618 | ||
| 619 | /* | |
| 620 | * USB | |
| 621 | */ | |
| 622 | #define CONFIG_HAS_FSL_DR_USB | |
| 623 | ||
| 624 | #ifdef CONFIG_HAS_FSL_DR_USB | |
| 8850c5d5 | 625 | #ifdef CONFIG_USB_EHCI_HCD |
| 062ef1a6 PJ |
626 | #define CONFIG_USB_EHCI_FSL |
| 627 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| e6a727ff | 628 | #define CONFIG_EHCI_DESC_BIG_ENDIAN |
| 062ef1a6 PJ |
629 | #endif |
| 630 | #endif | |
| 631 | ||
| 062ef1a6 PJ |
632 | #ifdef CONFIG_MMC |
| 633 | #define CONFIG_FSL_ESDHC | |
| 634 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
| 062ef1a6 PJ |
635 | #endif |
| 636 | ||
| 637 | /* Qman/Bman */ | |
| 638 | #ifndef CONFIG_NOBQFMAN | |
| 2a8b3422 | 639 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
| 062ef1a6 PJ |
640 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
| 641 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
| 642 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
643 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 644 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
| 645 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
| 646 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 647 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
| 648 | CONFIG_SYS_BMAN_CENA_SIZE) | |
| 649 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 650 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
| 2a8b3422 | 651 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
| 062ef1a6 PJ |
652 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
| 653 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
| 654 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
655 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
| 656 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
| 657 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
| 658 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 659 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
| 660 | CONFIG_SYS_QMAN_CENA_SIZE) | |
| 661 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 662 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
| 062ef1a6 PJ |
663 | |
| 664 | #define CONFIG_SYS_DPAA_FMAN | |
| 665 | #define CONFIG_SYS_DPAA_PME | |
| 666 | ||
| 59ff5d33 ZQ |
667 | #define CONFIG_QE |
| 668 | #define CONFIG_U_QE | |
| 669 | ||
| 062ef1a6 PJ |
670 | /* Default address of microcode for the Linux Fman driver */ |
| 671 | #if defined(CONFIG_SPIFLASH) | |
| 672 | /* | |
| 673 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
| 674 | * env, so we got 0x110000. | |
| 675 | */ | |
| 676 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
| dcf1d774 | 677 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
| 062ef1a6 PJ |
678 | #elif defined(CONFIG_SDCARD) |
| 679 | /* | |
| 680 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
| 18c01445 PK |
681 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
| 682 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. | |
| 062ef1a6 PJ |
683 | */ |
| 684 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
| 18c01445 | 685 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
| 062ef1a6 PJ |
686 | #elif defined(CONFIG_NAND) |
| 687 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
| 18c01445 | 688 | #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 062ef1a6 PJ |
689 | #else |
| 690 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
| dcf1d774 | 691 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
| 18c01445 PK |
692 | #endif |
| 693 | ||
| 18c01445 PK |
694 | #if defined(CONFIG_SPIFLASH) |
| 695 | #define CONFIG_SYS_QE_FW_ADDR 0x130000 | |
| 696 | #elif defined(CONFIG_SDCARD) | |
| 697 | #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) | |
| 698 | #elif defined(CONFIG_NAND) | |
| 699 | #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
| 700 | #else | |
| 59ff5d33 | 701 | #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 |
| 062ef1a6 | 702 | #endif |
| 18c01445 | 703 | |
| 062ef1a6 PJ |
704 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
| 705 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
| 706 | #endif /* CONFIG_NOBQFMAN */ | |
| 707 | ||
| 708 | #ifdef CONFIG_SYS_DPAA_FMAN | |
| 709 | #define CONFIG_FMAN_ENET | |
| 710 | #define CONFIG_PHY_VITESSE | |
| 711 | #define CONFIG_PHY_REALTEK | |
| 712 | #endif | |
| 713 | ||
| 714 | #ifdef CONFIG_FMAN_ENET | |
| 0167369c | 715 | #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) |
| 4b6067ae | 716 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 |
| a016735c | 717 | #elif defined(CONFIG_TARGET_T1040D4RDB) |
| 94af6842 | 718 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 |
| 319ed24a | 719 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
| 4b6067ae PJ |
720 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 |
| 721 | #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 | |
| 722 | #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 | |
| 723 | #endif | |
| 724 | ||
| 78e56995 | 725 | #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) |
| 4b6067ae PJ |
726 | #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 |
| 727 | #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 | |
| 728 | #else | |
| 729 | #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 | |
| 730 | #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 | |
| f4c3917a | 731 | #endif |
| 062ef1a6 | 732 | |
| db4a1767 | 733 | /* Enable VSC9953 L2 Switch driver on T1040 SoC */ |
| 6fcddd09 | 734 | #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) |
| db4a1767 | 735 | #define CONFIG_VSC9953 |
| 6fcddd09 | 736 | #ifdef CONFIG_TARGET_T1040RDB |
| db4a1767 CC |
737 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 |
| 738 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 | |
| 4b6067ae PJ |
739 | #else |
| 740 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 | |
| 741 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c | |
| 742 | #endif | |
| db4a1767 CC |
743 | #endif |
| 744 | ||
| 062ef1a6 | 745 | #define CONFIG_MII /* MII PHY management */ |
| 714fd406 | 746 | #define CONFIG_ETHPRIME "FM1@DTSEC4" |
| 062ef1a6 PJ |
747 | #endif |
| 748 | ||
| 749 | /* | |
| 750 | * Environment | |
| 751 | */ | |
| 752 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 753 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 754 | ||
| 062ef1a6 PJ |
755 | /* |
| 756 | * Miscellaneous configurable options | |
| 757 | */ | |
| 758 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 759 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 760 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
| 761 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 062ef1a6 PJ |
762 | |
| 763 | /* | |
| 764 | * For booting Linux, the board info and command line data | |
| 765 | * have to be in the first 64 MB of memory, since this is | |
| 766 | * the maximum mapped by the Linux kernel during initialization. | |
| 767 | */ | |
| 768 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
| 769 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 770 | ||
| 771 | #ifdef CONFIG_CMD_KGDB | |
| 772 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 062ef1a6 PJ |
773 | #endif |
| 774 | ||
| 68b74739 PK |
775 | /* |
| 776 | * Dynamic MTD Partition support with mtdparts | |
| 777 | */ | |
| e856bdcf | 778 | #ifdef CONFIG_MTD_NOR_FLASH |
| 68b74739 PK |
779 | #define CONFIG_MTD_DEVICE |
| 780 | #define CONFIG_MTD_PARTITIONS | |
| 68b74739 | 781 | #define CONFIG_FLASH_CFI_MTD |
| 68b74739 PK |
782 | #endif |
| 783 | ||
| 062ef1a6 PJ |
784 | /* |
| 785 | * Environment Configuration | |
| 786 | */ | |
| 787 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
| 788 | #define CONFIG_BOOTFILE "uImage" | |
| 789 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ | |
| 790 | ||
| 791 | /* default location for tftp and bootm */ | |
| 792 | #define CONFIG_LOADADDR 1000000 | |
| 793 | ||
| 062ef1a6 | 794 | #define __USB_PHY_TYPE utmi |
| 363fb32a | 795 | #define RAMDISKFILE "t104xrdb/ramdisk.uboot" |
| 062ef1a6 | 796 | |
| 6fcddd09 | 797 | #ifdef CONFIG_TARGET_T1040RDB |
| f4c3917a | 798 | #define FDTFILE "t1040rdb/t1040rdb.dtb" |
| 55ed8ae3 | 799 | #elif defined(CONFIG_TARGET_T1042RDB_PI) |
| 363fb32a | 800 | #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" |
| 0167369c | 801 | #elif defined(CONFIG_TARGET_T1042RDB) |
| 363fb32a | 802 | #define FDTFILE "t1042rdb/t1042rdb.dtb" |
| a016735c | 803 | #elif defined(CONFIG_TARGET_T1040D4RDB) |
| 4b6067ae | 804 | #define FDTFILE "t1042rdb/t1040d4rdb.dtb" |
| 319ed24a | 805 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
| 4b6067ae | 806 | #define FDTFILE "t1042rdb/t1042d4rdb.dtb" |
| f4c3917a | 807 | #endif |
| 808 | ||
| cf8ddacf JJ |
809 | #ifdef CONFIG_FSL_DIU_FB |
| 810 | #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" | |
| 811 | #else | |
| 812 | #define DIU_ENVIRONMENT | |
| 813 | #endif | |
| 814 | ||
| 062ef1a6 | 815 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 9b444be3 PJ |
816 | "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ |
| 817 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ | |
| 818 | "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
| 062ef1a6 | 819 | "netdev=eth0\0" \ |
| cf8ddacf | 820 | "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ |
| 062ef1a6 PJ |
821 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 822 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
| 823 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
| 824 | "protect off $ubootaddr +$filesize && " \ | |
| 825 | "erase $ubootaddr +$filesize && " \ | |
| 826 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
| 827 | "protect on $ubootaddr +$filesize && " \ | |
| 828 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
| 829 | "consoledev=ttyS0\0" \ | |
| 830 | "ramdiskaddr=2000000\0" \ | |
| f4c3917a | 831 | "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ |
| b24a4f62 | 832 | "fdtaddr=1e00000\0" \ |
| f4c3917a | 833 | "fdtfile=" __stringify(FDTFILE) "\0" \ |
| 3246584d | 834 | "bdev=sda3\0" |
| 062ef1a6 PJ |
835 | |
| 836 | #define CONFIG_LINUX \ | |
| 837 | "setenv bootargs root=/dev/ram rw " \ | |
| 838 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 839 | "setenv ramdiskaddr 0x02000000;" \ | |
| 840 | "setenv fdtaddr 0x00c00000;" \ | |
| 841 | "setenv loadaddr 0x1000000;" \ | |
| 842 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 843 | ||
| 844 | #define CONFIG_HDBOOT \ | |
| 845 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 846 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 847 | "tftp $loadaddr $bootfile;" \ | |
| 848 | "tftp $fdtaddr $fdtfile;" \ | |
| 849 | "bootm $loadaddr - $fdtaddr" | |
| 850 | ||
| 851 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 852 | "setenv bootargs root=/dev/nfs rw " \ | |
| 853 | "nfsroot=$serverip:$rootpath " \ | |
| 854 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 855 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 856 | "tftp $loadaddr $bootfile;" \ | |
| 857 | "tftp $fdtaddr $fdtfile;" \ | |
| 858 | "bootm $loadaddr - $fdtaddr" | |
| 859 | ||
| 860 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 861 | "setenv bootargs root=/dev/ram rw " \ | |
| 862 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 863 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 864 | "tftp $loadaddr $bootfile;" \ | |
| 865 | "tftp $fdtaddr $fdtfile;" \ | |
| 866 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 867 | ||
| 868 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
| 869 | ||
| 062ef1a6 | 870 | #include <asm/fsl_secure_boot.h> |
| ef6c55a2 | 871 | |
| 062ef1a6 | 872 | #endif /* __CONFIG_H */ |