[J-u-boot.git] / drivers / net / pcnet.c

/*
 * (C) Copyright 2002 Wolfgang Grandegger, [email protected].
 *
 * This driver for AMD PCnet network controllers is derived from the
 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <pci.h>

#define	PCNET_DEBUG_LEVEL	0	/* 0=off, 1=init, 2=rx/tx */

#define PCNET_DEBUG1(fmt,args...)	\
	debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
#define PCNET_DEBUG2(fmt,args...)	\
	debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)

#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
#error "Macro for PCnet chip version is not defined!"
#endif

/*
 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
 */
#define PCNET_LOG_TX_BUFFERS	0
#define PCNET_LOG_RX_BUFFERS	2

#define TX_RING_SIZE		(1 << (PCNET_LOG_TX_BUFFERS))
#define TX_RING_LEN_BITS	((PCNET_LOG_TX_BUFFERS) << 12)

#define RX_RING_SIZE		(1 << (PCNET_LOG_RX_BUFFERS))
#define RX_RING_LEN_BITS	((PCNET_LOG_RX_BUFFERS) << 4)

#define PKT_BUF_SZ		1544

/* The PCNET Rx and Tx ring descriptors. */
struct pcnet_rx_head {
	u32 base;
	s16 buf_length;
	s16 status;
	u32 msg_length;
	u32 reserved;
};

struct pcnet_tx_head {
	u32 base;
	s16 length;
	s16 status;
	u32 misc;
	u32 reserved;
};

/* The PCNET 32-Bit initialization block, described in databook. */
struct pcnet_init_block {
	u16 mode;
	u16 tlen_rlen;
	u8 phys_addr[6];
	u16 reserved;
	u32 filter[2];
	/* Receive and transmit ring base, along with extra bits. */
	u32 rx_ring;
	u32 tx_ring;
	u32 reserved2;
};

struct pcnet_uncached_priv {
	struct pcnet_rx_head rx_ring[RX_RING_SIZE];
	struct pcnet_tx_head tx_ring[TX_RING_SIZE];
	struct pcnet_init_block init_block;
};

typedef struct pcnet_priv {
	struct pcnet_uncached_priv *uc;
	/* Receive Buffer space */
	unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
	int cur_rx;
	int cur_tx;
} pcnet_priv_t;

static pcnet_priv_t *lp;

/* Offsets from base I/O address for WIO mode */
#define PCNET_RDP		0x10
#define PCNET_RAP		0x12
#define PCNET_RESET		0x14
#define PCNET_BDP		0x16

static u16 pcnet_read_csr(struct eth_device *dev, int index)
{
	outw(index, dev->iobase + PCNET_RAP);
	return inw(dev->iobase + PCNET_RDP);
}

static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
{
	outw(index, dev->iobase + PCNET_RAP);
	outw(val, dev->iobase + PCNET_RDP);
}

static u16 pcnet_read_bcr(struct eth_device *dev, int index)
{
	outw(index, dev->iobase + PCNET_RAP);
	return inw(dev->iobase + PCNET_BDP);
}

static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
{
	outw(index, dev->iobase + PCNET_RAP);
	outw(val, dev->iobase + PCNET_BDP);
}

static void pcnet_reset(struct eth_device *dev)
{
	inw(dev->iobase + PCNET_RESET);
}

static int pcnet_check(struct eth_device *dev)
{
	outw(88, dev->iobase + PCNET_RAP);
	return inw(dev->iobase + PCNET_RAP) == 88;
}

static int pcnet_init (struct eth_device *dev, bd_t * bis);
static int pcnet_send(struct eth_device *dev, void *packet, int length);
static int pcnet_recv (struct eth_device *dev);
static void pcnet_halt (struct eth_device *dev);
static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);

#define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a))
#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))

static struct pci_device_id supported[] = {
	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
	{}
};


int pcnet_initialize(bd_t *bis)
{
	pci_dev_t devbusfn;
	struct eth_device *dev;
	u16 command, status;
	int dev_nr = 0;

	PCNET_DEBUG1("\npcnet_initialize...\n");

	for (dev_nr = 0;; dev_nr++) {

		/*
		 * Find the PCnet PCI device(s).
		 */
		devbusfn = pci_find_devices(supported, dev_nr);
		if (devbusfn < 0)
			break;

		/*
		 * Allocate and pre-fill the device structure.
		 */
		dev = (struct eth_device *)malloc(sizeof(*dev));
		if (!dev) {
			printf("pcnet: Can not allocate memory\n");
			break;
		}
		memset(dev, 0, sizeof(*dev));
		dev->priv = (void *)devbusfn;
		sprintf(dev->name, "pcnet#%d", dev_nr);

		/*
		 * Setup the PCI device.
		 */
		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
				      (unsigned int *)&dev->iobase);
		dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
		dev->iobase &= ~0xf;

		PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
			     dev->name, devbusfn, dev->iobase);

		command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
		pci_write_config_word(devbusfn, PCI_COMMAND, command);
		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
		if ((status & command) != command) {
			printf("%s: Couldn't enable IO access or Bus Mastering\n",
			       dev->name);
			free(dev);
			continue;
		}

		pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);

		/*
		 * Probe the PCnet chip.
		 */
		if (pcnet_probe(dev, bis, dev_nr) < 0) {
			free(dev);
			continue;
		}

		/*
		 * Setup device structure and register the driver.
		 */
		dev->init = pcnet_init;
		dev->halt = pcnet_halt;
		dev->send = pcnet_send;
		dev->recv = pcnet_recv;

		eth_register(dev);
	}

	udelay(10 * 1000);

	return dev_nr;
}

static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
{
	int chip_version;
	char *chipname;

#ifdef PCNET_HAS_PROM
	int i;
#endif

	/* Reset the PCnet controller */
	pcnet_reset(dev);

	/* Check if register access is working */
	if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
		printf("%s: CSR register access check failed\n", dev->name);
		return -1;
	}

	/* Identify the chip */
	chip_version =
		pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
	if ((chip_version & 0xfff) != 0x003)
		return -1;
	chip_version = (chip_version >> 12) & 0xffff;
	switch (chip_version) {
	case 0x2621:
		chipname = "PCnet/PCI II 79C970A";	/* PCI */
		break;
#ifdef CONFIG_PCNET_79C973
	case 0x2625:
		chipname = "PCnet/FAST III 79C973";	/* PCI */
		break;
#endif
#ifdef CONFIG_PCNET_79C975
	case 0x2627:
		chipname = "PCnet/FAST III 79C975";	/* PCI */
		break;
#endif
	default:
		printf("%s: PCnet version %#x not supported\n",
		       dev->name, chip_version);
		return -1;
	}

	PCNET_DEBUG1("AMD %s\n", chipname);

#ifdef PCNET_HAS_PROM
	/*
	 * In most chips, after a chip reset, the ethernet address is read from
	 * the station address PROM at the base address and programmed into the
	 * "Physical Address Registers" CSR12-14.
	 */
	for (i = 0; i < 3; i++) {
		unsigned int val;

		val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
		/* There may be endianness issues here. */
		dev->enetaddr[2 * i] = val & 0x0ff;
		dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
	}
#endif /* PCNET_HAS_PROM */

	return 0;
}

static int pcnet_init(struct eth_device *dev, bd_t *bis)
{
	struct pcnet_uncached_priv *uc;
	int i, val;
	u32 addr;

	PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);

	/* Switch pcnet to 32bit mode */
	pcnet_write_bcr(dev, 20, 2);

	/* Set/reset autoselect bit */
	val = pcnet_read_bcr(dev, 2) & ~2;
	val |= 2;
	pcnet_write_bcr(dev, 2, val);

	/* Enable auto negotiate, setup, disable fd */
	val = pcnet_read_bcr(dev, 32) & ~0x98;
	val |= 0x20;
	pcnet_write_bcr(dev, 32, val);

	/*
	 * Enable NOUFLO on supported controllers, with the transmit
	 * start point set to the full packet. This will cause entire
	 * packets to be buffered by the ethernet controller before
	 * transmission, eliminating underflows which are common on
	 * slower devices. Controllers which do not support NOUFLO will
	 * simply be left with a larger transmit FIFO threshold.
	 */
	val = pcnet_read_bcr(dev, 18);
	val |= 1 << 11;
	pcnet_write_bcr(dev, 18, val);
	val = pcnet_read_csr(dev, 80);
	val |= 0x3 << 10;
	pcnet_write_csr(dev, 80, val);

	/*
	 * We only maintain one structure because the drivers will never
	 * be used concurrently. In 32bit mode the RX and TX ring entries
	 * must be aligned on 16-byte boundaries.
	 */
	if (lp == NULL) {
		addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
		addr = (addr + 0xf) & ~0xf;
		lp = (pcnet_priv_t *)addr;

		addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc));
		flush_dcache_range(addr, addr + sizeof(*lp->uc));
		addr = UNCACHED_SDRAM(addr);
		lp->uc = (struct pcnet_uncached_priv *)addr;
	}

	uc = lp->uc;

	uc->init_block.mode = cpu_to_le16(0x0000);
	uc->init_block.filter[0] = 0x00000000;
	uc->init_block.filter[1] = 0x00000000;

	/*
	 * Initialize the Rx ring.
	 */
	lp->cur_rx = 0;
	for (i = 0; i < RX_RING_SIZE; i++) {
		uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]);
		uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
		uc->rx_ring[i].status = cpu_to_le16(0x8000);
		PCNET_DEBUG1
			("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
			 uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
			 uc->rx_ring[i].status);
	}

	/*
	 * Initialize the Tx ring. The Tx buffer address is filled in as
	 * needed, but we do need to clear the upper ownership bit.
	 */
	lp->cur_tx = 0;
	for (i = 0; i < TX_RING_SIZE; i++) {
		uc->tx_ring[i].base = 0;
		uc->tx_ring[i].status = 0;
	}

	/*
	 * Setup Init Block.
	 */
	PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);

	for (i = 0; i < 6; i++) {
		lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
		PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
	}

	uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
					       RX_RING_LEN_BITS);
	uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring);
	uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring);

	PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
		     uc->init_block.tlen_rlen,
		     uc->init_block.rx_ring, uc->init_block.tx_ring);

	/*
	 * Tell the controller where the Init Block is located.
	 */
	barrier();
	addr = PCI_TO_MEM(dev, &lp->uc->init_block);
	pcnet_write_csr(dev, 1, addr & 0xffff);
	pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);

	pcnet_write_csr(dev, 4, 0x0915);
	pcnet_write_csr(dev, 0, 0x0001);	/* start */

	/* Wait for Init Done bit */
	for (i = 10000; i > 0; i--) {
		if (pcnet_read_csr(dev, 0) & 0x0100)
			break;
		udelay(10);
	}
	if (i <= 0) {
		printf("%s: TIMEOUT: controller init failed\n", dev->name);
		pcnet_reset(dev);
		return -1;
	}

	/*
	 * Finally start network controller operation.
	 */
	pcnet_write_csr(dev, 0, 0x0002);

	return 0;
}

static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
{
	int i, status;
	struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];

	PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
		     packet);

	flush_dcache_range((unsigned long)packet,
			   (unsigned long)packet + pkt_len);

	/* Wait for completion by testing the OWN bit */
	for (i = 1000; i > 0; i--) {
		status = le16_to_cpu(entry->status);
		if ((status & 0x8000) == 0)
			break;
		udelay(100);
		PCNET_DEBUG2(".");
	}
	if (i <= 0) {
		printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
		       dev->name, lp->cur_tx, status);
		pkt_len = 0;
		goto failure;
	}

	/*
	 * Setup Tx ring. Caution: the write order is important here,
	 * set the status with the "ownership" bits last.
	 */
	status = 0x8300;
	entry->length = cpu_to_le16(-pkt_len);
	entry->misc = 0x00000000;
	entry->base = PCI_TO_MEM_LE(dev, packet);
	entry->status = cpu_to_le16(status);

	/* Trigger an immediate send poll. */
	pcnet_write_csr(dev, 0, 0x0008);

      failure:
	if (++lp->cur_tx >= TX_RING_SIZE)
		lp->cur_tx = 0;

	PCNET_DEBUG2("done\n");
	return pkt_len;
}

static int pcnet_recv (struct eth_device *dev)
{
	struct pcnet_rx_head *entry;
	int pkt_len = 0;
	u16 status;

	while (1) {
		entry = &lp->uc->rx_ring[lp->cur_rx];
		/*
		 * If we own the next entry, it's a new packet. Send it up.
		 */
		status = le16_to_cpu(entry->status);
		if ((status & 0x8000) != 0)
			break;
		status >>= 8;

		if (status != 0x03) {	/* There was an error. */
			printf("%s: Rx%d", dev->name, lp->cur_rx);
			PCNET_DEBUG1(" (status=0x%x)", status);
			if (status & 0x20)
				printf(" Frame");
			if (status & 0x10)
				printf(" Overflow");
			if (status & 0x08)
				printf(" CRC");
			if (status & 0x04)
				printf(" Fifo");
			printf(" Error\n");
			entry->status &= le16_to_cpu(0x03ff);

		} else {
			pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4;
			if (pkt_len < 60) {
				printf("%s: Rx%d: invalid packet length %d\n",
				       dev->name, lp->cur_rx, pkt_len);
			} else {
				invalidate_dcache_range(
					(unsigned long)lp->rx_buf[lp->cur_rx],
					(unsigned long)lp->rx_buf[lp->cur_rx] +
					pkt_len);
				NetReceive(lp->rx_buf[lp->cur_rx], pkt_len);
				PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
					     lp->cur_rx, pkt_len,
					     lp->rx_buf[lp->cur_rx]);
			}
		}
		entry->status |= cpu_to_le16(0x8000);

		if (++lp->cur_rx >= RX_RING_SIZE)
			lp->cur_rx = 0;
	}
	return pkt_len;
}

static void pcnet_halt(struct eth_device *dev)
{
	int i;

	PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);

	/* Reset the PCnet controller */
	pcnet_reset(dev);

	/* Wait for Stop bit */
	for (i = 1000; i > 0; i--) {
		if (pcnet_read_csr(dev, 0) & 0x4)
			break;
		udelay(10);
	}
	if (i <= 0)
		printf("%s: TIMEOUT: controller reset failed\n", dev->name);
}
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2002 Wolfgang Grandegger, [email protected].
	3	*
	4	* This driver for AMD PCnet network controllers is derived from the
	5	* Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	8	*/
	9
	10	#include <common.h>
	11	#include <malloc.h>
	12	#include <net.h>
e3090534	13	#include <netdev.h>
c609719b WD	14	#include <asm/io.h>
	15	#include <pci.h>
	16
11ea26fd	17	#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
c609719b	18
138b6089 WD	19	#define PCNET_DEBUG1(fmt,args...) \
	20	debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
	21	#define PCNET_DEBUG2(fmt,args...) \
	22	debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
c609719b	23
c609719b WD	24	#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
	25	#error "Macro for PCnet chip version is not defined!"
	26	#endif
	27
	28	/*
	29	* Set the number of Tx and Rx buffers, using Log_2(# buffers).
	30	* Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
	31	* That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
	32	*/
	33	#define PCNET_LOG_TX_BUFFERS 0
	34	#define PCNET_LOG_RX_BUFFERS 2
	35
	36	#define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
	37	#define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
	38
	39	#define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
	40	#define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
	41
	42	#define PKT_BUF_SZ 1544
	43
	44	/* The PCNET Rx and Tx ring descriptors. */
	45	struct pcnet_rx_head {
11ea26fd WD	46	u32 base;
	47	s16 buf_length;
	48	s16 status;
	49	u32 msg_length;
	50	u32 reserved;
c609719b WD	51	};
	52
	53	struct pcnet_tx_head {
11ea26fd WD	54	u32 base;
	55	s16 length;
	56	s16 status;
	57	u32 misc;
	58	u32 reserved;
c609719b WD	59	};
	60
	61	/* The PCNET 32-Bit initialization block, described in databook. */
	62	struct pcnet_init_block {
11ea26fd WD	63	u16 mode;
	64	u16 tlen_rlen;
	65	u8 phys_addr[6];
	66	u16 reserved;
	67	u32 filter[2];
	68	/* Receive and transmit ring base, along with extra bits. */
	69	u32 rx_ring;
	70	u32 tx_ring;
	71	u32 reserved2;
c609719b WD	72	};
c609719b WD	73
f1ae382d	74	struct pcnet_uncached_priv {
11ea26fd WD	75	struct pcnet_rx_head rx_ring[RX_RING_SIZE];
	76	struct pcnet_tx_head tx_ring[TX_RING_SIZE];
	77	struct pcnet_init_block init_block;
f1ae382d PB	78	};
	79
	80	typedef struct pcnet_priv {
	81	struct pcnet_uncached_priv *uc;
11ea26fd WD	82	/* Receive Buffer space */
	83	unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
	84	int cur_rx;
	85	int cur_tx;
c609719b WD	86	} pcnet_priv_t;
	87
	88	static pcnet_priv_t *lp;
	89
	90	/* Offsets from base I/O address for WIO mode */
	91	#define PCNET_RDP 0x10
	92	#define PCNET_RAP 0x12
	93	#define PCNET_RESET 0x14
	94	#define PCNET_BDP 0x16
	95
6011dabd	96	static u16 pcnet_read_csr(struct eth_device *dev, int index)
c609719b	97	{
6011dabd PB	98	outw(index, dev->iobase + PCNET_RAP);
6011dabd PB	99	return inw(dev->iobase + PCNET_RDP);
c609719b WD	100	}
c609719b WD	101
6011dabd	102	static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
c609719b	103	{
6011dabd PB	104	outw(index, dev->iobase + PCNET_RAP);
6011dabd PB	105	outw(val, dev->iobase + PCNET_RDP);
c609719b WD	106	}
c609719b WD	107
6011dabd	108	static u16 pcnet_read_bcr(struct eth_device *dev, int index)
c609719b	109	{
6011dabd PB	110	outw(index, dev->iobase + PCNET_RAP);
6011dabd PB	111	return inw(dev->iobase + PCNET_BDP);
c609719b WD	112	}
c609719b WD	113
6011dabd	114	static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
c609719b	115	{
6011dabd PB	116	outw(index, dev->iobase + PCNET_RAP);
6011dabd PB	117	outw(val, dev->iobase + PCNET_BDP);
c609719b WD	118	}
c609719b WD	119
6011dabd	120	static void pcnet_reset(struct eth_device *dev)
c609719b	121	{
6011dabd	122	inw(dev->iobase + PCNET_RESET);
c609719b WD	123	}
c609719b WD	124
6011dabd	125	static int pcnet_check(struct eth_device *dev)
c609719b	126	{
6011dabd PB	127	outw(88, dev->iobase + PCNET_RAP);
6011dabd PB	128	return inw(dev->iobase + PCNET_RAP) == 88;
c609719b WD	129	}
c609719b WD	130
11ea26fd	131	static int pcnet_init (struct eth_device dev, bd_t bis);
f92a151c	132	static int pcnet_send(struct eth_device dev, void packet, int length);
11ea26fd WD	133	static int pcnet_recv (struct eth_device *dev);
	134	static void pcnet_halt (struct eth_device *dev);
	135	static int pcnet_probe (struct eth_device dev, bd_t bis, int dev_num);
c609719b	136
54fbcb0c	137	#define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a))
c609719b WD	138	#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
	139
	140	static struct pci_device_id supported[] = {
11ea26fd WD	141	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
11ea26fd WD	142	{}
c609719b WD	143	};
	144
	145
6011dabd	146	int pcnet_initialize(bd_t *bis)
c609719b	147	{
11ea26fd WD	148	pci_dev_t devbusfn;
	149	struct eth_device *dev;
	150	u16 command, status;
	151	int dev_nr = 0;
	152
6011dabd	153	PCNET_DEBUG1("\npcnet_initialize...\n");
11ea26fd WD	154
	155	for (dev_nr = 0;; dev_nr++) {
	156
	157	/*
	158	* Find the PCnet PCI device(s).
	159	*/
6011dabd PB	160	devbusfn = pci_find_devices(supported, dev_nr);
6011dabd PB	161	if (devbusfn < 0)
11ea26fd	162	break;
11ea26fd WD	163
	164	/*
	165	* Allocate and pre-fill the device structure.
	166	*/
6011dabd	167	dev = (struct eth_device )malloc(sizeof(dev));
5ed0eeca NI	168	if (!dev) {
	169	printf("pcnet: Can not allocate memory\n");
	170	break;
	171	}
	172	memset(dev, 0, sizeof(*dev));
6011dabd PB	173	dev->priv = (void *)devbusfn;
6011dabd PB	174	sprintf(dev->name, "pcnet#%d", dev_nr);
11ea26fd WD	175
	176	/*
	177	* Setup the PCI device.
	178	*/
6011dabd PB	179	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
	180	(unsigned int *)&dev->iobase);
	181	dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
11ea26fd WD	182	dev->iobase &= ~0xf;
11ea26fd WD	183
6011dabd PB	184	PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
6011dabd PB	185	dev->name, devbusfn, dev->iobase);
11ea26fd WD	186
11ea26fd WD	187	command = PCI_COMMAND_IO \| PCI_COMMAND_MASTER;
6011dabd PB	188	pci_write_config_word(devbusfn, PCI_COMMAND, command);
6011dabd PB	189	pci_read_config_word(devbusfn, PCI_COMMAND, &status);
11ea26fd	190	if ((status & command) != command) {
6011dabd PB	191	printf("%s: Couldn't enable IO access or Bus Mastering\n",
	192	dev->name);
	193	free(dev);
11ea26fd WD	194	continue;
	195	}
	196
6011dabd	197	pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
11ea26fd WD	198
	199	/*
	200	* Probe the PCnet chip.
	201	*/
6011dabd PB	202	if (pcnet_probe(dev, bis, dev_nr) < 0) {
6011dabd PB	203	free(dev);
11ea26fd WD	204	continue;
	205	}
	206
	207	/*
	208	* Setup device structure and register the driver.
	209	*/
	210	dev->init = pcnet_init;
	211	dev->halt = pcnet_halt;
	212	dev->send = pcnet_send;
	213	dev->recv = pcnet_recv;
	214
6011dabd	215	eth_register(dev);
c609719b WD	216	}
c609719b WD	217
6011dabd	218	udelay(10 * 1000);
c609719b	219
11ea26fd	220	return dev_nr;
c609719b WD	221	}
c609719b WD	222
6011dabd	223	static int pcnet_probe(struct eth_device dev, bd_t bis, int dev_nr)
c609719b	224	{
11ea26fd WD	225	int chip_version;
	226	char *chipname;
	227
c609719b	228	#ifdef PCNET_HAS_PROM
11ea26fd	229	int i;
c609719b WD	230	#endif
c609719b WD	231
11ea26fd	232	/* Reset the PCnet controller */
6011dabd	233	pcnet_reset(dev);
11ea26fd WD	234
11ea26fd WD	235	/* Check if register access is working */
6011dabd PB	236	if (pcnet_read_csr(dev, 0) != 4 \|\| !pcnet_check(dev)) {
6011dabd PB	237	printf("%s: CSR register access check failed\n", dev->name);
11ea26fd WD	238	return -1;
	239	}
	240
	241	/* Identify the chip */
	242	chip_version =
6011dabd	243	pcnet_read_csr(dev, 88) \| (pcnet_read_csr(dev, 89) << 16);
11ea26fd WD	244	if ((chip_version & 0xfff) != 0x003)
	245	return -1;
	246	chip_version = (chip_version >> 12) & 0xffff;
	247	switch (chip_version) {
	248	case 0x2621:
	249	chipname = "PCnet/PCI II 79C970A"; /* PCI */
	250	break;
c609719b	251	#ifdef CONFIG_PCNET_79C973
11ea26fd WD	252	case 0x2625:
	253	chipname = "PCnet/FAST III 79C973"; /* PCI */
	254	break;
c609719b WD	255	#endif
c609719b WD	256	#ifdef CONFIG_PCNET_79C975
11ea26fd WD	257	case 0x2627:
	258	chipname = "PCnet/FAST III 79C975"; /* PCI */
	259	break;
c609719b	260	#endif
11ea26fd	261	default:
6011dabd PB	262	printf("%s: PCnet version %#x not supported\n",
6011dabd PB	263	dev->name, chip_version);
11ea26fd WD	264	return -1;
11ea26fd WD	265	}
c609719b	266
6011dabd	267	PCNET_DEBUG1("AMD %s\n", chipname);
c609719b WD	268
c609719b WD	269	#ifdef PCNET_HAS_PROM
11ea26fd WD	270	/*
	271	* In most chips, after a chip reset, the ethernet address is read from
	272	* the station address PROM at the base address and programmed into the
	273	* "Physical Address Registers" CSR12-14.
	274	*/
	275	for (i = 0; i < 3; i++) {
	276	unsigned int val;
	277
6011dabd	278	val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
11ea26fd WD	279	/* There may be endianness issues here. */
	280	dev->enetaddr[2 * i] = val & 0x0ff;
	281	dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
	282	}
c609719b WD	283	#endif /* PCNET_HAS_PROM */
c609719b WD	284
11ea26fd	285	return 0;
c609719b WD	286	}
c609719b WD	287
6011dabd	288	static int pcnet_init(struct eth_device dev, bd_t bis)
c609719b	289	{
f1ae382d	290	struct pcnet_uncached_priv *uc;
11ea26fd WD	291	int i, val;
11ea26fd WD	292	u32 addr;
c609719b	293
6011dabd	294	PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
c609719b	295
11ea26fd	296	/* Switch pcnet to 32bit mode */
6011dabd	297	pcnet_write_bcr(dev, 20, 2);
c609719b	298
11ea26fd	299	/* Set/reset autoselect bit */
6011dabd	300	val = pcnet_read_bcr(dev, 2) & ~2;
11ea26fd	301	val \|= 2;
6011dabd	302	pcnet_write_bcr(dev, 2, val);
c609719b	303
11ea26fd	304	/* Enable auto negotiate, setup, disable fd */
6011dabd	305	val = pcnet_read_bcr(dev, 32) & ~0x98;
11ea26fd	306	val \|= 0x20;
6011dabd	307	pcnet_write_bcr(dev, 32, val);
c609719b	308
62715a2c PB	309	/*
	310	* Enable NOUFLO on supported controllers, with the transmit
	311	* start point set to the full packet. This will cause entire
	312	* packets to be buffered by the ethernet controller before
	313	* transmission, eliminating underflows which are common on
	314	* slower devices. Controllers which do not support NOUFLO will
	315	* simply be left with a larger transmit FIFO threshold.
	316	*/
	317	val = pcnet_read_bcr(dev, 18);
	318	val \|= 1 << 11;
	319	pcnet_write_bcr(dev, 18, val);
	320	val = pcnet_read_csr(dev, 80);
	321	val \|= 0x3 << 10;
	322	pcnet_write_csr(dev, 80, val);
	323
11ea26fd WD	324	/*
	325	* We only maintain one structure because the drivers will never
	326	* be used concurrently. In 32bit mode the RX and TX ring entries
	327	* must be aligned on 16-byte boundaries.
	328	*/
	329	if (lp == NULL) {
6011dabd	330	addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
11ea26fd	331	addr = (addr + 0xf) & ~0xf;
6011dabd	332	lp = (pcnet_priv_t *)addr;
f1ae382d PB	333
	334	addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc));
	335	flush_dcache_range(addr, addr + sizeof(*lp->uc));
	336	addr = UNCACHED_SDRAM(addr);
	337	lp->uc = (struct pcnet_uncached_priv *)addr;
11ea26fd	338	}
c609719b	339
f1ae382d PB	340	uc = lp->uc;
	341
	342	uc->init_block.mode = cpu_to_le16(0x0000);
	343	uc->init_block.filter[0] = 0x00000000;
	344	uc->init_block.filter[1] = 0x00000000;
11ea26fd WD	345
	346	/*
	347	* Initialize the Rx ring.
	348	*/
	349	lp->cur_rx = 0;
	350	for (i = 0; i < RX_RING_SIZE; i++) {
f1ae382d PB	351	uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]);
	352	uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
	353	uc->rx_ring[i].status = cpu_to_le16(0x8000);
11ea26fd WD	354	PCNET_DEBUG1
11ea26fd WD	355	("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
f1ae382d PB	356	uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
f1ae382d PB	357	uc->rx_ring[i].status);
11ea26fd WD	358	}
	359
	360	/*
	361	* Initialize the Tx ring. The Tx buffer address is filled in as
	362	* needed, but we do need to clear the upper ownership bit.
	363	*/
c609719b	364	lp->cur_tx = 0;
11ea26fd	365	for (i = 0; i < TX_RING_SIZE; i++) {
f1ae382d PB	366	uc->tx_ring[i].base = 0;
f1ae382d PB	367	uc->tx_ring[i].status = 0;
11ea26fd	368	}
c609719b	369
11ea26fd WD	370	/*
	371	* Setup Init Block.
	372	*/
f1ae382d	373	PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
c609719b	374
11ea26fd	375	for (i = 0; i < 6; i++) {
f1ae382d PB	376	lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
f1ae382d PB	377	PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
11ea26fd WD	378	}
11ea26fd WD	379
f1ae382d	380	uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS \|
6011dabd	381	RX_RING_LEN_BITS);
f1ae382d PB	382	uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring);
f1ae382d PB	383	uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring);
11ea26fd	384
6011dabd	385	PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
f1ae382d PB	386	uc->init_block.tlen_rlen,
f1ae382d PB	387	uc->init_block.rx_ring, uc->init_block.tx_ring);
c609719b	388
c609719b	389	/*
11ea26fd	390	* Tell the controller where the Init Block is located.
c609719b	391	*/
f1ae382d PB	392	barrier();
f1ae382d PB	393	addr = PCI_TO_MEM(dev, &lp->uc->init_block);
6011dabd PB	394	pcnet_write_csr(dev, 1, addr & 0xffff);
6011dabd PB	395	pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
11ea26fd	396
6011dabd PB	397	pcnet_write_csr(dev, 4, 0x0915);
6011dabd PB	398	pcnet_write_csr(dev, 0, 0x0001); /* start */
11ea26fd WD	399
	400	/* Wait for Init Done bit */
	401	for (i = 10000; i > 0; i--) {
6011dabd	402	if (pcnet_read_csr(dev, 0) & 0x0100)
11ea26fd	403	break;
6011dabd	404	udelay(10);
c609719b	405	}
11ea26fd	406	if (i <= 0) {
6011dabd PB	407	printf("%s: TIMEOUT: controller init failed\n", dev->name);
6011dabd PB	408	pcnet_reset(dev);
11ea26fd	409	return -1;
c609719b	410	}
c609719b	411
11ea26fd WD	412	/*
	413	* Finally start network controller operation.
	414	*/
6011dabd	415	pcnet_write_csr(dev, 0, 0x0002);
11ea26fd WD	416
11ea26fd WD	417	return 0;
c609719b WD	418	}
c609719b WD	419
f92a151c	420	static int pcnet_send(struct eth_device dev, void packet, int pkt_len)
c609719b	421	{
11ea26fd	422	int i, status;
f1ae382d	423	struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
11ea26fd	424
6011dabd PB	425	PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
6011dabd PB	426	packet);
11ea26fd	427
f3ac866c PB	428	flush_dcache_range((unsigned long)packet,
	429	(unsigned long)packet + pkt_len);
	430
11ea26fd WD	431	/* Wait for completion by testing the OWN bit */
11ea26fd WD	432	for (i = 1000; i > 0; i--) {
6011dabd	433	status = le16_to_cpu(entry->status);
11ea26fd WD	434	if ((status & 0x8000) == 0)
11ea26fd WD	435	break;
6011dabd PB	436	udelay(100);
6011dabd PB	437	PCNET_DEBUG2(".");
11ea26fd WD	438	}
11ea26fd WD	439	if (i <= 0) {
6011dabd PB	440	printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
6011dabd PB	441	dev->name, lp->cur_tx, status);
11ea26fd WD	442	pkt_len = 0;
	443	goto failure;
	444	}
	445
	446	/*
	447	* Setup Tx ring. Caution: the write order is important here,
	448	* set the status with the "ownership" bits last.
	449	*/
	450	status = 0x8300;
a9540041	451	entry->length = cpu_to_le16(-pkt_len);
11ea26fd	452	entry->misc = 0x00000000;
6011dabd	453	entry->base = PCI_TO_MEM_LE(dev, packet);
a9540041	454	entry->status = cpu_to_le16(status);
11ea26fd WD	455
11ea26fd WD	456	/* Trigger an immediate send poll. */
6011dabd	457	pcnet_write_csr(dev, 0, 0x0008);
11ea26fd WD	458
	459	failure:
	460	if (++lp->cur_tx >= TX_RING_SIZE)
	461	lp->cur_tx = 0;
	462
6011dabd	463	PCNET_DEBUG2("done\n");
11ea26fd WD	464	return pkt_len;
	465	}
	466
	467	static int pcnet_recv (struct eth_device *dev)
	468	{
	469	struct pcnet_rx_head *entry;
	470	int pkt_len = 0;
	471	u16 status;
	472
	473	while (1) {
f1ae382d	474	entry = &lp->uc->rx_ring[lp->cur_rx];
11ea26fd WD	475	/*
	476	* If we own the next entry, it's a new packet. Send it up.
	477	*/
6011dabd PB	478	status = le16_to_cpu(entry->status);
6011dabd PB	479	if ((status & 0x8000) != 0)
11ea26fd	480	break;
11ea26fd WD	481	status >>= 8;
	482
	483	if (status != 0x03) { /* There was an error. */
6011dabd PB	484	printf("%s: Rx%d", dev->name, lp->cur_rx);
6011dabd PB	485	PCNET_DEBUG1(" (status=0x%x)", status);
11ea26fd	486	if (status & 0x20)
6011dabd	487	printf(" Frame");
11ea26fd	488	if (status & 0x10)
6011dabd	489	printf(" Overflow");
11ea26fd	490	if (status & 0x08)
6011dabd	491	printf(" CRC");
11ea26fd	492	if (status & 0x04)
6011dabd PB	493	printf(" Fifo");
	494	printf(" Error\n");
	495	entry->status &= le16_to_cpu(0x03ff);
11ea26fd WD	496
11ea26fd WD	497	} else {
6011dabd	498	pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4;
11ea26fd	499	if (pkt_len < 60) {
6011dabd PB	500	printf("%s: Rx%d: invalid packet length %d\n",
6011dabd PB	501	dev->name, lp->cur_rx, pkt_len);
11ea26fd	502	} else {
f3ac866c PB	503	invalidate_dcache_range(
	504	(unsigned long)lp->rx_buf[lp->cur_rx],
	505	(unsigned long)lp->rx_buf[lp->cur_rx] +
	506	pkt_len);
6011dabd PB	507	NetReceive(lp->rx_buf[lp->cur_rx], pkt_len);
	508	PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
	509	lp->cur_rx, pkt_len,
	510	lp->rx_buf[lp->cur_rx]);
11ea26fd WD	511	}
11ea26fd WD	512	}
6011dabd	513	entry->status \|= cpu_to_le16(0x8000);
11ea26fd WD	514
	515	if (++lp->cur_rx >= RX_RING_SIZE)
	516	lp->cur_rx = 0;
	517	}
	518	return pkt_len;
c609719b WD	519	}
c609719b WD	520
6011dabd	521	static void pcnet_halt(struct eth_device *dev)
11ea26fd WD	522	{
	523	int i;
	524
6011dabd	525	PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
11ea26fd WD	526
11ea26fd WD	527	/* Reset the PCnet controller */
6011dabd	528	pcnet_reset(dev);
11ea26fd WD	529
	530	/* Wait for Stop bit */
	531	for (i = 1000; i > 0; i--) {
6011dabd	532	if (pcnet_read_csr(dev, 0) & 0x4)
11ea26fd	533	break;
6011dabd	534	udelay(10);
11ea26fd	535	}
6011dabd PB	536	if (i <= 0)
6011dabd PB	537	printf("%s: TIMEOUT: controller reset failed\n", dev->name);
11ea26fd	538	}