projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 4549e789 | 1 | // SPDX-License-Identifier: GPL-2.0+ OR X11 |
| b647442c KY |
2 | /* |
| 3 | * (C) Copyright 2017 Rockchip Electronics Co., Ltd. | |
| b647442c KY |
4 | */ |
| 5 | ||
| 6 | /dts-v1/; | |
| 7 | ||
| 8 | #include "rk322x.dtsi" | |
| 9 | ||
| 10 | / { | |
| 11 | model = "Rockchip RK3229 Evaluation board"; | |
| 12 | compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; | |
| 13 | ||
| 14 | chosen { | |
| 15 | stdout-path = &uart2; | |
| 16 | }; | |
| 17 | ||
| 18 | memory@60000000 { | |
| 19 | device_type = "memory"; | |
| 20 | reg = <0x60000000 0x40000000>; | |
| 21 | }; | |
| 22 | ||
| 23 | ext_gmac: ext_gmac { | |
| 24 | compatible = "fixed-clock"; | |
| 25 | clock-frequency = <125000000>; | |
| 26 | clock-output-names = "ext_gmac"; | |
| 27 | #clock-cells = <0>; | |
| 28 | }; | |
| 29 | ||
| 30 | vcc_phy: vcc-phy-regulator { | |
| 31 | compatible = "regulator-fixed"; | |
| 32 | enable-active-high; | |
| 33 | regulator-name = "vcc_phy"; | |
| 34 | regulator-min-microvolt = <1800000>; | |
| 35 | regulator-max-microvolt = <1800000>; | |
| 36 | regulator-always-on; | |
| 37 | regulator-boot-on; | |
| 38 | }; | |
| 39 | }; | |
| 40 | ||
| 41 | &dmc { | |
| b647442c KY |
42 | rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3 |
| 43 | 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4 | |
| 44 | 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1 | |
| 45 | 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4 | |
| 46 | 0x0 0x924>; | |
| 47 | rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>; | |
| 48 | rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15 | |
| 49 | 0 300 3 0 120>; | |
| 50 | }; | |
| 51 | ||
| 52 | &gmac { | |
| 53 | assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; | |
| 54 | assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; | |
| 55 | clock_in_out = "input"; | |
| 56 | phy-supply = <&vcc_phy>; | |
| 57 | phy-mode = "rgmii"; | |
| 58 | pinctrl-names = "default"; | |
| 59 | pinctrl-0 = <&rgmii_pins>; | |
| 60 | snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; | |
| 61 | snps,reset-active-low; | |
| 62 | snps,reset-delays-us = <0 10000 1000000>; | |
| 63 | tx_delay = <0x30>; | |
| 64 | rx_delay = <0x10>; | |
| 65 | status = "okay"; | |
| 66 | }; | |
| 67 | ||
| 68 | &emmc { | |
| 69 | u-boot,dm-pre-reloc; | |
| 70 | status = "okay"; | |
| 71 | }; | |
| 72 | ||
| a2a1bfe1 KY |
73 | &sdmmc { |
| 74 | status = "okay"; | |
| 75 | bus-width = <4>; | |
| 76 | cap-mmc-highspeed; | |
| 77 | cap-sd-highspeed; | |
| 78 | card-detect-delay = <200>; | |
| 79 | disable-wp; | |
| a2a1bfe1 KY |
80 | num-slots = <1>; |
| 81 | supports-sd; | |
| 82 | }; | |
| 83 | ||
| b647442c | 84 | &uart2 { |
| d55dbfed | 85 | u-boot,dm-pre-reloc; |
| b647442c KY |
86 | status = "okay"; |
| 87 | }; | |
| 01240628 MD |
88 | |
| 89 | &usb20_otg { | |
| 90 | status = "okay"; | |
| 91 | }; |