[J-u-boot.git] / drivers / phy / bcm6318-usbh-phy.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2018 Álvaro Fernández Rojas <[email protected]>
 *
 * Derived from linux/arch/mips/bcm63xx/usb-common.c:
 *	Copyright 2008 Maxime Bizon <[email protected]>
 *	Copyright 2013 Florian Fainelli <[email protected]>
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <generic-phy.h>
#include <log.h>
#include <malloc.h>
#include <power-domain.h>
#include <reset.h>
#include <asm/io.h>
#include <dm/device.h>
#include <linux/delay.h>

/* USBH Setup register */
#define USBH_SETUP_REG		0x00
#define USBH_SETUP_IOC		BIT(4)

/* USBH PLL Control register */
#define USBH_PLL_REG		0x04
#define USBH_PLL_SUSP_EN	BIT(27)
#define USBH_PLL_IDDQ_PWRDN	BIT(31)

/* USBH Swap Control register */
#define USBH_SWAP_REG		0x0c
#define USBH_SWAP_OHCI_DATA	BIT(0)
#define USBH_SWAP_OHCI_ENDIAN	BIT(1)
#define USBH_SWAP_EHCI_DATA	BIT(3)
#define USBH_SWAP_EHCI_ENDIAN	BIT(4)

/* USBH Sim Control register */
#define USBH_SIM_REG		0x20
#define USBH_SIM_LADDR		BIT(5)

struct bcm6318_usbh_priv {
	void __iomem *regs;
};

static int bcm6318_usbh_init(struct phy *phy)
{
	struct bcm6318_usbh_priv *priv = dev_get_priv(phy->dev);

	/* enable pll control susp */
	setbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_SUSP_EN);

	/* configure to work in native cpu endian */
	clrsetbits_be32(priv->regs + USBH_SWAP_REG,
			USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
			USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);

	/* setup config */
	setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);

	/* disable pll control pwrdn */
	clrbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_IDDQ_PWRDN);

	/* sim control config */
	setbits_be32(priv->regs + USBH_SIM_REG, USBH_SIM_LADDR);

	return 0;
}

static struct phy_ops bcm6318_usbh_ops = {
	.init = bcm6318_usbh_init,
};

static const struct udevice_id bcm6318_usbh_ids[] = {
	{ .compatible = "brcm,bcm6318-usbh" },
	{ /* sentinel */ }
};

static int bcm6318_usbh_probe(struct udevice *dev)
{
	struct bcm6318_usbh_priv *priv = dev_get_priv(dev);
	struct power_domain pwr_dom;
	struct reset_ctl rst_ctl;
	struct clk clk;
	int ret;

	priv->regs = dev_remap_addr(dev);
	if (!priv->regs)
		return -EINVAL;

	/* enable usbh clock */
	ret = clk_get_by_name(dev, "usbh", &clk);
	if (ret < 0)
		return ret;

	ret = clk_enable(&clk);
	if (ret < 0)
		return ret;

	ret = clk_free(&clk);
	if (ret < 0)
		return ret;

	/* enable power domain */
	ret = power_domain_get(dev, &pwr_dom);
	if (ret < 0)
		return ret;

	ret = power_domain_on(&pwr_dom);
	if (ret < 0)
		return ret;

	ret = power_domain_free(&pwr_dom);
	if (ret < 0)
		return ret;

	/* perform reset */
	ret = reset_get_by_index(dev, 0, &rst_ctl);
	if (ret < 0)
		return ret;

	ret = reset_deassert(&rst_ctl);
	if (ret < 0)
		return ret;

	ret = reset_free(&rst_ctl);
	if (ret < 0)
		return ret;

	mdelay(100);

	return 0;
}

U_BOOT_DRIVER(bcm6318_usbh) = {
	.name = "bcm6318-usbh",
	.id = UCLASS_PHY,
	.of_match = bcm6318_usbh_ids,
	.ops = &bcm6318_usbh_ops,
	.priv_auto_alloc_size = sizeof(struct bcm6318_usbh_priv),
	.probe = bcm6318_usbh_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
8e948c6f	2	/*
9ca33ebf	3	* Copyright (C) 2018 Álvaro Fernández Rojas <[email protected]>
8e948c6f ÁFR	4	*
	5	* Derived from linux/arch/mips/bcm63xx/usb-common.c:
	6	* Copyright 2008 Maxime Bizon <[email protected]>
	7	* Copyright 2013 Florian Fainelli <[email protected]>
8e948c6f ÁFR	8	*/
	9
	10	#include <common.h>
	11	#include <clk.h>
	12	#include <dm.h>
	13	#include <generic-phy.h>
f7ae49fc	14	#include <log.h>
336d4615	15	#include <malloc.h>
8e948c6f ÁFR	16	#include <power-domain.h>
	17	#include <reset.h>
	18	#include <asm/io.h>
	19	#include <dm/device.h>
c05ed00a	20	#include <linux/delay.h>
8e948c6f ÁFR	21
	22	/* USBH Setup register */
	23	#define USBH_SETUP_REG 0x00
	24	#define USBH_SETUP_IOC BIT(4)
	25
	26	/* USBH PLL Control register */
	27	#define USBH_PLL_REG 0x04
	28	#define USBH_PLL_SUSP_EN BIT(27)
	29	#define USBH_PLL_IDDQ_PWRDN BIT(31)
	30
	31	/* USBH Swap Control register */
	32	#define USBH_SWAP_REG 0x0c
	33	#define USBH_SWAP_OHCI_DATA BIT(0)
	34	#define USBH_SWAP_OHCI_ENDIAN BIT(1)
	35	#define USBH_SWAP_EHCI_DATA BIT(3)
	36	#define USBH_SWAP_EHCI_ENDIAN BIT(4)
	37
	38	/* USBH Sim Control register */
	39	#define USBH_SIM_REG 0x20
	40	#define USBH_SIM_LADDR BIT(5)
	41
	42	struct bcm6318_usbh_priv {
	43	void __iomem *regs;
	44	};
	45
	46	static int bcm6318_usbh_init(struct phy *phy)
	47	{
	48	struct bcm6318_usbh_priv *priv = dev_get_priv(phy->dev);
	49
	50	/* enable pll control susp */
	51	setbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_SUSP_EN);
	52
	53	/* configure to work in native cpu endian */
	54	clrsetbits_be32(priv->regs + USBH_SWAP_REG,
	55	USBH_SWAP_EHCI_ENDIAN \| USBH_SWAP_OHCI_ENDIAN,
	56	USBH_SWAP_EHCI_DATA \| USBH_SWAP_OHCI_DATA);
	57
	58	/* setup config */
	59	setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);
	60
	61	/* disable pll control pwrdn */
	62	clrbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_IDDQ_PWRDN);
	63
	64	/* sim control config */
	65	setbits_be32(priv->regs + USBH_SIM_REG, USBH_SIM_LADDR);
	66
	67	return 0;
	68	}
	69
	70	static struct phy_ops bcm6318_usbh_ops = {
	71	.init = bcm6318_usbh_init,
	72	};
	73
	74	static const struct udevice_id bcm6318_usbh_ids[] = {
	75	{ .compatible = "brcm,bcm6318-usbh" },
	76	{ /* sentinel */ }
	77	};
	78
	79	static int bcm6318_usbh_probe(struct udevice *dev)
	80	{
	81	struct bcm6318_usbh_priv *priv = dev_get_priv(dev);
	82	struct power_domain pwr_dom;
	83	struct reset_ctl rst_ctl;
	84	struct clk clk;
8e948c6f ÁFR	85	int ret;
8e948c6f ÁFR	86
9ca33ebf ÁFR	87	priv->regs = dev_remap_addr(dev);
9ca33ebf ÁFR	88	if (!priv->regs)
8e948c6f ÁFR	89	return -EINVAL;
8e948c6f ÁFR	90
8e948c6f ÁFR	91	/* enable usbh clock */
	92	ret = clk_get_by_name(dev, "usbh", &clk);
	93	if (ret < 0)
	94	return ret;
	95
	96	ret = clk_enable(&clk);
	97	if (ret < 0)
	98	return ret;
	99
	100	ret = clk_free(&clk);
	101	if (ret < 0)
	102	return ret;
	103
	104	/* enable power domain */
	105	ret = power_domain_get(dev, &pwr_dom);
	106	if (ret < 0)
	107	return ret;
	108
	109	ret = power_domain_on(&pwr_dom);
	110	if (ret < 0)
	111	return ret;
	112
	113	ret = power_domain_free(&pwr_dom);
	114	if (ret < 0)
	115	return ret;
	116
	117	/* perform reset */
	118	ret = reset_get_by_index(dev, 0, &rst_ctl);
	119	if (ret < 0)
	120	return ret;
	121
	122	ret = reset_deassert(&rst_ctl);
	123	if (ret < 0)
	124	return ret;
	125
	126	ret = reset_free(&rst_ctl);
	127	if (ret < 0)
	128	return ret;
	129
	130	mdelay(100);
	131
	132	return 0;
	133	}
	134
	135	U_BOOT_DRIVER(bcm6318_usbh) = {
	136	.name = "bcm6318-usbh",
	137	.id = UCLASS_PHY,
	138	.of_match = bcm6318_usbh_ids,
	139	.ops = &bcm6318_usbh_ops,
	140	.priv_auto_alloc_size = sizeof(struct bcm6318_usbh_priv),
	141	.probe = bcm6318_usbh_probe,
	142	};