[J-u-boot.git] / include / zynqmp_tap_delay.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Xilinx ZynqMP SoC Tap Delay Programming
 *
 * Copyright (C) 2018 Xilinx, Inc.
 */

#ifndef __ZYNQMP_TAP_DELAY_H__
#define __ZYNQMP_TAP_DELAY_H__

#ifdef CONFIG_ARCH_ZYNQMP
void zynqmp_dll_reset(u8 deviceid);
void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay, u32 otap_delay);
#else
inline void zynqmp_dll_reset(u8 deviceid) {}
inline void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay,
				       u32 otap_delay) {}
#endif

#endif
Commit	Line	Data
d1f4e39d SDPP	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Xilinx ZynqMP SoC Tap Delay Programming
	4	*
	5	* Copyright (C) 2018 Xilinx, Inc.
	6	*/
	7
	8	#ifndef __ZYNQMP_TAP_DELAY_H__
	9	#define __ZYNQMP_TAP_DELAY_H__
	10
	11	#ifdef CONFIG_ARCH_ZYNQMP
	12	void zynqmp_dll_reset(u8 deviceid);
728d21b8	13	void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay, u32 otap_delay);
d1f4e39d SDPP	14	#else
d1f4e39d SDPP	15	inline void zynqmp_dll_reset(u8 deviceid) {}
728d21b8 ARS	16	inline void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay,
728d21b8 ARS	17	u32 otap_delay) {}
d1f4e39d SDPP	18	#endif
	19
	20	#endif