[J-u-boot.git] / board / freescale / t102xrdb / t102xrdb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 * Copyright 2020 NXP
 */

#include <common.h>
#include <command.h>
#include <env.h>
#include <fdt_support.h>
#include <i2c.h>
#include <image.h>
#include <init.h>
#include <netdev.h>
#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t102xrdb.h"
#ifdef CONFIG_TARGET_T1024RDB
#include "cpld.h"
#elif defined(CONFIG_TARGET_T1023RDB)
#include <i2c.h>
#include <mmc.h>
#endif
#include "../common/sleep.h"

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_TARGET_T1023RDB
enum {
	GPIO1_SD_SEL    = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
	GPIO1_EMMC_SEL,
	GPIO3_GET_VERSION,	       /* GPIO3_4/5, 00:RevB, 01: RevC */
	GPIO3_BRD_VER_MASK = 0x0c000000,
	GPIO3_OFFSET = 0x2000,
	I2C_GET_BANK,
	I2C_SET_BANK0,
	I2C_SET_BANK4,
};
#endif

int checkboard(void)
{
	struct cpu_type *cpu = gd->arch.cpu;
	static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 srds_s1;

	srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;

	printf("Board: %sRDB, ", cpu->name);
#if defined(CONFIG_TARGET_T1024RDB)
	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
#elif defined(CONFIG_TARGET_T1023RDB)
	printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
#endif
	printf("boot from ");

#ifdef CONFIG_SDCARD
	puts("SD/MMC\n");
#elif CONFIG_SPIFLASH
	puts("SPI\n");
#elif defined(CONFIG_TARGET_T1024RDB)
	u8 reg;

	reg = CPLD_READ(flash_csr);

	if (reg & CPLD_BOOT_SEL) {
		puts("NAND\n");
	} else {
		reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
		printf("NOR vBank%d\n", reg);
	}
#elif defined(CONFIG_TARGET_T1023RDB)
#ifdef CONFIG_MTD_RAW_NAND
	puts("NAND\n");
#else
	printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
#endif
#endif

	puts("SERDES Reference Clocks:\n");
	if (srds_s1 == 0x95)
		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
	else
		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);

	return 0;
}

#ifdef CONFIG_TARGET_T1024RDB
static void board_mux_lane(void)
{
	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 srds_prtcl_s1;
	u8 reg = CPLD_READ(misc_ctl_status);

	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;

	if (srds_prtcl_s1 == 0x95) {
		/* Route Lane B to PCIE */
		CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
	} else {
		/* Route Lane B to SGMII */
		CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
	}
	CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
}
#endif

int board_early_init_f(void)
{
#if defined(CONFIG_DEEP_SLEEP)
	if (is_warm_boot())
		fsl_dp_disable_console();
#endif

	return 0;
}

int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	int flash_esel = find_tlb_idx((void *)flashbase, 1);
	/*
	 * Remap Boot flash region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();
	if (flash_esel == -1) {
		/* very unlikely unless something is messed up */
		puts("Error: Could not find TLB for FLASH BASE\n");
		flash_esel = 2;	/* give our best effort to continue */
	} else {
		/* invalidate existing TLB entry for flash + promjet */
		disable_tlb(flash_esel);
	}

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif

#ifdef CONFIG_TARGET_T1024RDB
	board_mux_lane();
#endif

	return 0;
}

unsigned long get_board_sys_clk(void)
{
	return CONFIG_SYS_CLK_FREQ;
}

#ifdef CONFIG_TARGET_T1024RDB
void board_reset(void)
{
	CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
}
#endif

int misc_init_r(void)
{
	return 0;
}

int ft_board_setup(void *blob, struct bd_info *bd)
{
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = env_get_bootm_low();
	size = env_get_bootm_size();

	fdt_fixup_memory(blob, (u64)base, (u64)size);

#ifdef CONFIG_PCI
	pci_of_setup(blob, bd);
#endif

	fdt_fixup_liodn(blob);
	fsl_fdt_fixup_dr_usb(blob, bd);

#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
	fdt_fixup_fman_ethernet(blob);
#endif
	fdt_fixup_board_enet(blob);
#endif

#ifdef CONFIG_TARGET_T1023RDB
	if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
		fdt_enable_nor(blob);
#endif

	return 0;
}

#ifdef CONFIG_TARGET_T1023RDB
/* Enable NOR flash for RevC */
static void fdt_enable_nor(void *blob)
{
	int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");

	if (nodeoff >= 0)
		fdt_status_okay(blob, nodeoff);
	else
		printf("WARNING unable to set status for NOR\n");
}

int board_mmc_getcd(struct mmc *mmc)
{
	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	u32 val = in_be32(&pgpio->gpdat);

	/* GPIO1_14, 0: eMMC, 1: SD/MMC */
	val &= GPIO1_SD_SEL;

	return val ? -1 : 1;
}

int board_mmc_getwp(struct mmc *mmc)
{
	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	u32 val = in_be32(&pgpio->gpdat);

	val &= GPIO1_SD_SEL;

	return val ? -1 : 0;
}

static u32 t1023rdb_ctrl(u32 ctrl_type)
{
	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	ccsr_gur_t __iomem  *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 val;
	u8 tmp;
	int bus_num = I2C_PCA6408_BUS_NUM;

#if CONFIG_IS_ENABLED(DM_I2C)
	struct udevice *dev;
	int ret;

	ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR,
				      1, &dev);
	if (ret) {
		printf("%s: Cannot find udev for a bus %d\n", __func__,
		       bus_num);
		return ret;
	}
	switch (ctrl_type) {
	case GPIO1_SD_SEL:
		val = in_be32(&pgpio->gpdat);
		val |= GPIO1_SD_SEL;
		out_be32(&pgpio->gpdat, val);
		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
		break;
	case GPIO1_EMMC_SEL:
		val = in_be32(&pgpio->gpdat);
		val &= ~GPIO1_SD_SEL;
		out_be32(&pgpio->gpdat, val);
		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
		break;
	case GPIO3_GET_VERSION:
		pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
			 + GPIO3_OFFSET);
		val = in_be32(&pgpio->gpdat);
		val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
		if (val == 0x3) /* GPIO3_4/5 not used on RevB */
			val = 0;
		return val;
	case I2C_GET_BANK:
		dm_i2c_read(dev, 0, &tmp, 1);
		tmp &= 0x7;
		tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
		return tmp;
	case I2C_SET_BANK0:
		tmp = 0x0;
		dm_i2c_write(dev, 1, &tmp, 1);
		tmp = 0xf8;
		dm_i2c_write(dev, 3, &tmp, 1);
		/* asserting HRESET_REQ */
		out_be32(&gur->rstcr, 0x2);
		break;
	case I2C_SET_BANK4:
		tmp = 0x1;
		dm_i2c_write(dev, 1, &tmp, 1);
		tmp = 0xf8;
		dm_i2c_write(dev, 3, &tmp, 1);
		out_be32(&gur->rstcr, 0x2);
		break;
	default:
		break;
	}
#else
	u32 orig_bus;

	orig_bus = i2c_get_bus_num();

	switch (ctrl_type) {
	case GPIO1_SD_SEL:
		val = in_be32(&pgpio->gpdat);
		val |= GPIO1_SD_SEL;
		out_be32(&pgpio->gpdat, val);
		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
		break;
	case GPIO1_EMMC_SEL:
		val = in_be32(&pgpio->gpdat);
		val &= ~GPIO1_SD_SEL;
		out_be32(&pgpio->gpdat, val);
		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
		break;
	case GPIO3_GET_VERSION:
		pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
			 + GPIO3_OFFSET);
		val = in_be32(&pgpio->gpdat);
		val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
		if (val == 0x3) /* GPIO3_4/5 not used on RevB */
			val = 0;
		return val;
	case I2C_GET_BANK:
		i2c_set_bus_num(bus_num);
		i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
		tmp &= 0x7;
		tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
		i2c_set_bus_num(orig_bus);
		return tmp;
	case I2C_SET_BANK0:
		i2c_set_bus_num(bus_num);
		tmp = 0x0;
		i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
		tmp = 0xf8;
		i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
		/* asserting HRESET_REQ */
		out_be32(&gur->rstcr, 0x2);
		break;
	case I2C_SET_BANK4:
		i2c_set_bus_num(bus_num);
		tmp = 0x1;
		i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
		tmp = 0xf8;
		i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
		out_be32(&gur->rstcr, 0x2);
		break;
	default:
		break;
	}
#endif
	return 0;
}

static int switch_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
		      char *const argv[])
{
	if (argc < 2)
		return CMD_RET_USAGE;
	if (!strcmp(argv[1], "bank0"))
		t1023rdb_ctrl(I2C_SET_BANK0);
	else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
		t1023rdb_ctrl(I2C_SET_BANK4);
	else if (!strcmp(argv[1], "sd"))
		t1023rdb_ctrl(GPIO1_SD_SEL);
	else if (!strcmp(argv[1], "emmc"))
		t1023rdb_ctrl(GPIO1_EMMC_SEL);
	else
		return CMD_RET_USAGE;
	return 0;
}

U_BOOT_CMD(
	switch, 2, 0, switch_cmd,
	"for bank0/bank4/sd/emmc switch control in runtime",
	"command (e.g. switch bank4)"
);
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
48c6f328 SL	2	/*
48c6f328 SL	3	* Copyright 2014 Freescale Semiconductor, Inc.
9e9771a6	4	* Copyright 2020 NXP
48c6f328 SL	5	*/
	6
	7	#include <common.h>
	8	#include <command.h>
7b51b576	9	#include <env.h>
807765b0	10	#include <fdt_support.h>
48c6f328	11	#include <i2c.h>
4d72caa5	12	#include <image.h>
5255932f	13	#include <init.h>
48c6f328	14	#include <netdev.h>
401d1c4f	15	#include <asm/global_data.h>
48c6f328 SL	16	#include <linux/compiler.h>
	17	#include <asm/mmu.h>
	18	#include <asm/processor.h>
	19	#include <asm/immap_85xx.h>
	20	#include <asm/fsl_law.h>
	21	#include <asm/fsl_serdes.h>
48c6f328	22	#include <asm/fsl_liodn.h>
48c6f328 SL	23	#include <fm_eth.h>
48c6f328 SL	24	#include "t102xrdb.h"
960286b6	25	#ifdef CONFIG_TARGET_T1024RDB
48c6f328	26	#include "cpld.h"
9082405d	27	#elif defined(CONFIG_TARGET_T1023RDB)
ff7ea2d1 SL	28	#include <i2c.h>
ff7ea2d1 SL	29	#include <mmc.h>
e8a7f1c3	30	#endif
f49b8c1b	31	#include "../common/sleep.h"
48c6f328 SL	32
	33	DECLARE_GLOBAL_DATA_PTR;
	34
9082405d	35	#ifdef CONFIG_TARGET_T1023RDB
e8a7f1c3	36	enum {
ff7ea2d1	37	GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
e8a7f1c3	38	GPIO1_EMMC_SEL,
ff7ea2d1 SL	39	GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */
	40	GPIO3_BRD_VER_MASK = 0x0c000000,
	41	GPIO3_OFFSET = 0x2000,
	42	I2C_GET_BANK,
	43	I2C_SET_BANK0,
	44	I2C_SET_BANK4,
e8a7f1c3 SL	45	};
	46	#endif
	47
48c6f328 SL	48	int checkboard(void)
	49	{
	50	struct cpu_type *cpu = gd->arch.cpu;
	51	static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
e26416a3 SL	52	ccsr_gur_t __iomem gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	53	u32 srds_s1;
	54
	55	srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	56	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
48c6f328 SL	57
48c6f328 SL	58	printf("Board: %sRDB, ", cpu->name);
960286b6	59	#if defined(CONFIG_TARGET_T1024RDB)
e8a7f1c3	60	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
48c6f328	61	CPLD_READ(hw_ver), CPLD_READ(sw_ver));
9082405d	62	#elif defined(CONFIG_TARGET_T1023RDB)
ff7ea2d1	63	printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
e8a7f1c3 SL	64	#endif
e8a7f1c3 SL	65	printf("boot from ");
48c6f328 SL	66
	67	#ifdef CONFIG_SDCARD
	68	puts("SD/MMC\n");
	69	#elif CONFIG_SPIFLASH
	70	puts("SPI\n");
960286b6	71	#elif defined(CONFIG_TARGET_T1024RDB)
48c6f328 SL	72	u8 reg;
	73
	74	reg = CPLD_READ(flash_csr);
	75
	76	if (reg & CPLD_BOOT_SEL) {
	77	puts("NAND\n");
	78	} else {
	79	reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
	80	printf("NOR vBank%d\n", reg);
	81	}
9082405d	82	#elif defined(CONFIG_TARGET_T1023RDB)
88718be3	83	#ifdef CONFIG_MTD_RAW_NAND
e8a7f1c3 SL	84	puts("NAND\n");
e8a7f1c3 SL	85	#else
ff7ea2d1	86	printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
e8a7f1c3	87	#endif
48c6f328 SL	88	#endif
	89
	90	puts("SERDES Reference Clocks:\n");
e26416a3 SL	91	if (srds_s1 == 0x95)
	92	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
	93	else
e8a7f1c3	94	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
48c6f328 SL	95
	96	return 0;
	97	}
	98
960286b6	99	#ifdef CONFIG_TARGET_T1024RDB
e26416a3 SL	100	static void board_mux_lane(void)
	101	{
	102	ccsr_gur_t __iomem gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	103	u32 srds_prtcl_s1;
	104	u8 reg = CPLD_READ(misc_ctl_status);
	105
	106	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
	107	FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	108	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
	109
	110	if (srds_prtcl_s1 == 0x95) {
	111	/* Route Lane B to PCIE */
	112	CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
	113	} else {
	114	/* Route Lane B to SGMII */
	115	CPLD_WRITE(misc_ctl_status, reg \| CPLD_PCIE_SGMII_MUX);
	116	}
	117	CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
	118	}
e8a7f1c3	119	#endif
e26416a3	120
f49b8c1b	121	int board_early_init_f(void)
	122	{
	123	#if defined(CONFIG_DEEP_SLEEP)
	124	if (is_warm_boot())
	125	fsl_dp_disable_console();
	126	#endif
	127
	128	return 0;
	129	}
	130
48c6f328 SL	131	int board_early_init_r(void)
	132	{
	133	#ifdef CONFIG_SYS_FLASH_BASE
	134	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	135	int flash_esel = find_tlb_idx((void *)flashbase, 1);
	136	/*
	137	* Remap Boot flash region to caching-inhibited
	138	* so that flash can be erased properly.
	139	*/
	140
	141	/* Flush d-cache and invalidate i-cache of any FLASH data */
	142	flush_dcache();
	143	invalidate_icache();
	144	if (flash_esel == -1) {
	145	/* very unlikely unless something is messed up */
	146	puts("Error: Could not find TLB for FLASH BASE\n");
	147	flash_esel = 2; /* give our best effort to continue */
	148	} else {
	149	/* invalidate existing TLB entry for flash + promjet */
	150	disable_tlb(flash_esel);
	151	}
	152
	153	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
	154	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	155	0, flash_esel, BOOKE_PAGESZ_256M, 1);
	156	#endif
	157
960286b6	158	#ifdef CONFIG_TARGET_T1024RDB
e26416a3	159	board_mux_lane();
e8a7f1c3	160	#endif
48c6f328 SL	161
	162	return 0;
	163	}
	164
	165	unsigned long get_board_sys_clk(void)
	166	{
	167	return CONFIG_SYS_CLK_FREQ;
	168	}
	169
e0dfec86 SL	170	#ifdef CONFIG_TARGET_T1024RDB
	171	void board_reset(void)
	172	{
	173	CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
	174	}
	175	#endif
	176
48c6f328 SL	177	int misc_init_r(void)
	178	{
	179	return 0;
	180	}
	181
b75d8dc5	182	int ft_board_setup(void blob, struct bd_info bd)
48c6f328 SL	183	{
	184	phys_addr_t base;
	185	phys_size_t size;
	186
	187	ft_cpu_setup(blob, bd);
	188
723806cc SG	189	base = env_get_bootm_low();
723806cc SG	190	size = env_get_bootm_size();
48c6f328 SL	191
	192	fdt_fixup_memory(blob, (u64)base, (u64)size);
	193
	194	#ifdef CONFIG_PCI
	195	pci_of_setup(blob, bd);
	196	#endif
	197
	198	fdt_fixup_liodn(blob);
a5c289b9	199	fsl_fdt_fixup_dr_usb(blob, bd);
48c6f328 SL	200
48c6f328 SL	201	#ifdef CONFIG_SYS_DPAA_FMAN
564637a3	202	#ifndef CONFIG_DM_ETH
48c6f328	203	fdt_fixup_fman_ethernet(blob);
564637a3	204	#endif
48c6f328 SL	205	fdt_fixup_board_enet(blob);
	206	#endif
	207
9082405d	208	#ifdef CONFIG_TARGET_T1023RDB
ff7ea2d1 SL	209	if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
	210	fdt_enable_nor(blob);
	211	#endif
	212
48c6f328 SL	213	return 0;
48c6f328 SL	214	}
e8a7f1c3	215
9082405d	216	#ifdef CONFIG_TARGET_T1023RDB
ff7ea2d1 SL	217	/* Enable NOR flash for RevC */
ff7ea2d1 SL	218	static void fdt_enable_nor(void *blob)
e8a7f1c3	219	{
ff7ea2d1 SL	220	int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
	221
	222	if (nodeoff >= 0)
	223	fdt_status_okay(blob, nodeoff);
	224	else
	225	printf("WARNING unable to set status for NOR\n");
	226	}
e8a7f1c3	227
ff7ea2d1 SL	228	int board_mmc_getcd(struct mmc *mmc)
	229	{
	230	ccsr_gpio_t __iomem pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	231	u32 val = in_be32(&pgpio->gpdat);
	232
	233	/* GPIO1_14, 0: eMMC, 1: SD/MMC */
	234	val &= GPIO1_SD_SEL;
	235
	236	return val ? -1 : 1;
	237	}
	238
	239	int board_mmc_getwp(struct mmc *mmc)
	240	{
	241	ccsr_gpio_t __iomem pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	242	u32 val = in_be32(&pgpio->gpdat);
	243
	244	val &= GPIO1_SD_SEL;
	245
	246	return val ? -1 : 0;
	247	}
	248
	249	static u32 t1023rdb_ctrl(u32 ctrl_type)
	250	{
	251	ccsr_gpio_t __iomem pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	252	ccsr_gur_t __iomem gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
9e9771a6	253	u32 val;
ff7ea2d1	254	u8 tmp;
9e9771a6 BL	255	int bus_num = I2C_PCA6408_BUS_NUM;
9e9771a6 BL	256
2147a169	257	#if CONFIG_IS_ENABLED(DM_I2C)
9e9771a6 BL	258	struct udevice *dev;
	259	int ret;
	260
	261	ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR,
	262	1, &dev);
	263	if (ret) {
	264	printf("%s: Cannot find udev for a bus %d\n", __func__,
	265	bus_num);
	266	return ret;
	267	}
	268	switch (ctrl_type) {
	269	case GPIO1_SD_SEL:
	270	val = in_be32(&pgpio->gpdat);
	271	val \|= GPIO1_SD_SEL;
	272	out_be32(&pgpio->gpdat, val);
	273	setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
	274	break;
	275	case GPIO1_EMMC_SEL:
	276	val = in_be32(&pgpio->gpdat);
	277	val &= ~GPIO1_SD_SEL;
	278	out_be32(&pgpio->gpdat, val);
	279	setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
	280	break;
	281	case GPIO3_GET_VERSION:
	282	pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
	283	+ GPIO3_OFFSET);
	284	val = in_be32(&pgpio->gpdat);
	285	val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
	286	if (val == 0x3) /* GPIO3_4/5 not used on RevB */
	287	val = 0;
	288	return val;
	289	case I2C_GET_BANK:
	290	dm_i2c_read(dev, 0, &tmp, 1);
	291	tmp &= 0x7;
	292	tmp = ((tmp & 1) << 2) \| (tmp & 2) \| ((tmp & 4) >> 2);
	293	return tmp;
	294	case I2C_SET_BANK0:
	295	tmp = 0x0;
	296	dm_i2c_write(dev, 1, &tmp, 1);
	297	tmp = 0xf8;
	298	dm_i2c_write(dev, 3, &tmp, 1);
	299	/* asserting HRESET_REQ */
	300	out_be32(&gur->rstcr, 0x2);
	301	break;
	302	case I2C_SET_BANK4:
	303	tmp = 0x1;
	304	dm_i2c_write(dev, 1, &tmp, 1);
	305	tmp = 0xf8;
	306	dm_i2c_write(dev, 3, &tmp, 1);
	307	out_be32(&gur->rstcr, 0x2);
	308	break;
	309	default:
	310	break;
	311	}
	312	#else
	313	u32 orig_bus;
	314
	315	orig_bus = i2c_get_bus_num();
e8a7f1c3 SL	316
	317	switch (ctrl_type) {
	318	case GPIO1_SD_SEL:
ff7ea2d1 SL	319	val = in_be32(&pgpio->gpdat);
	320	val \|= GPIO1_SD_SEL;
	321	out_be32(&pgpio->gpdat, val);
	322	setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
e8a7f1c3 SL	323	break;
e8a7f1c3 SL	324	case GPIO1_EMMC_SEL:
ff7ea2d1 SL	325	val = in_be32(&pgpio->gpdat);
	326	val &= ~GPIO1_SD_SEL;
	327	out_be32(&pgpio->gpdat, val);
	328	setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
e8a7f1c3	329	break;
ff7ea2d1 SL	330	case GPIO3_GET_VERSION:
	331	pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
	332	+ GPIO3_OFFSET);
	333	val = in_be32(&pgpio->gpdat);
	334	val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
	335	if (val == 0x3) /* GPIO3_4/5 not used on RevB */
	336	val = 0;
	337	return val;
	338	case I2C_GET_BANK:
9e9771a6	339	i2c_set_bus_num(bus_num);
ff7ea2d1 SL	340	i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
	341	tmp &= 0x7;
	342	tmp = ((tmp & 1) << 2) \| (tmp & 2) \| ((tmp & 4) >> 2);
	343	i2c_set_bus_num(orig_bus);
	344	return tmp;
	345	case I2C_SET_BANK0:
9e9771a6	346	i2c_set_bus_num(bus_num);
ff7ea2d1 SL	347	tmp = 0x0;
	348	i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
	349	tmp = 0xf8;
	350	i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
	351	/* asserting HRESET_REQ */
	352	out_be32(&gur->rstcr, 0x2);
e8a7f1c3	353	break;
ff7ea2d1	354	case I2C_SET_BANK4:
9e9771a6	355	i2c_set_bus_num(bus_num);
ff7ea2d1 SL	356	tmp = 0x1;
	357	i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
	358	tmp = 0xf8;
	359	i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
	360	out_be32(&gur->rstcr, 0x2);
e8a7f1c3	361	break;
e8a7f1c3 SL	362	default:
	363	break;
	364	}
9e9771a6	365	#endif
e8a7f1c3 SL	366	return 0;
	367	}
	368
09140113 SG	369	static int switch_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
09140113 SG	370	char *const argv[])
e8a7f1c3 SL	371	{
	372	if (argc < 2)
	373	return CMD_RET_USAGE;
ff7ea2d1 SL	374	if (!strcmp(argv[1], "bank0"))
	375	t1023rdb_ctrl(I2C_SET_BANK0);
	376	else if (!strcmp(argv[1], "bank4") \|\| !strcmp(argv[1], "altbank"))
	377	t1023rdb_ctrl(I2C_SET_BANK4);
e8a7f1c3	378	else if (!strcmp(argv[1], "sd"))
ff7ea2d1 SL	379	t1023rdb_ctrl(GPIO1_SD_SEL);
	380	else if (!strcmp(argv[1], "emmc"))
	381	t1023rdb_ctrl(GPIO1_EMMC_SEL);
e8a7f1c3 SL	382	else
	383	return CMD_RET_USAGE;
	384	return 0;
	385	}
	386
	387	U_BOOT_CMD(
ff7ea2d1 SL	388	switch, 2, 0, switch_cmd,
	389	"for bank0/bank4/sd/emmc switch control in runtime",
	390	"command (e.g. switch bank4)"
e8a7f1c3 SL	391	);
e8a7f1c3 SL	392	#endif