[J-u-boot.git] / include / configs / cm_t3517.h

/*
 * (C) Copyright 2013 CompuLab, Ltd.
 * Author: Igor Grinberg <[email protected]>
 *
 * Configuration settings for the CompuLab CM-T3517 board
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP	/* in a TI OMAP core */
#define CONFIG_CM_T3517	/* working with CM-T3517 */
#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766

#define CONFIG_SYS_TEXT_BASE	0x80008000

/*
 * This is needed for the DMA stuff.
 * Although the default iss 64, we still define it
 * to be on the safe side once the default is changed.
 */

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

#define CONFIG_MACH_TYPE                MACH_TYPE_CM_T3517

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

/*
 * The early kernel mapping on ARM currently only maps from the base of DRAM
 * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
 * so that leaves DRAM base to DRAM base + 0x4000 available.
 */
#define CONFIG_SYS_BOOTMAPSZ	        0x4000

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SERIAL_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

#define CONFIG_OMAP_GPIO

#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION

/* USB */
#define CONFIG_USB_MUSB_AM35X

#ifndef CONFIG_USB_MUSB_AM35X
#define CONFIG_USB_OMAP3
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
#else /* !CONFIG_USB_MUSB_AM35X */
#define CONFIG_USB_MUSB_PIO_ONLY
#endif /* CONFIG_USB_MUSB_AM35X */

/* commands to include */
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT		"nand0=nand"
#define MTDPARTS_DEFAULT	"mtdparts=nand:512k(x-loader),"\
				"1920k(u-boot),256k(u-boot-env),"\
				"4m(kernel),-(fs)"

#define CONFIG_CMD_NAND		/* NAND support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	400000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_I2C_EEPROM_BUS	0
#define CONFIG_I2C_MULTI_BUS

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */

/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"baudrate=115200\0" \
	"console=ttyO2,115200n8\0" \
	"netretry=yes\0" \
	"mpurate=auto\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
	"mmcrootfstype=ext4\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=ubifs\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 2a0000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

/*
 * Miscellaneous configurable options
 */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_TIMESTAMP
#define CONFIG_SYS_AUTOLOAD		"no"
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	/* CM-T3517 DRAM is only on CS0 */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define CONFIG_SYS_CS0_SIZE		(256 << 20)

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#if defined(CONFIG_CMD_NET)
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE	(0x2C000000 + (16 << 20))
#define CONFIG_ARP_TIMEOUT		200UL
#define CONFIG_NET_RETRY_COUNT		5
#endif /* CONFIG_CMD_NET */

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
					 CONFIG_SYS_INIT_RAM_SIZE -	\
					 GENERATED_GBL_DATA_SIZE)

/* Status LED */
#define CONFIG_STATUS_LED		/* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED
#define CONFIG_GPIO_LED
#define GREEN_LED_GPIO			186 /* CM-T3517 Green LED is GPIO186 */
#define GREEN_LED_DEV			0
#define STATUS_LED_BIT			GREEN_LED_GPIO
#define STATUS_LED_STATE		STATUS_LED_ON
#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BOOT			GREEN_LED_DEV

/* GPIO banks */
#ifdef CONFIG_STATUS_LED
#define CONFIG_OMAP3_GPIO_6	/* GPIO186 is in GPIO bank 6  */
#endif

/* Display Configuration */
#define CONFIG_OMAP3_GPIO_2
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_VIDEO_OMAP3
#define LCD_BPP		LCD_COLOR16

#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASHIMAGE_GUARD
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_SCF0403_LCD

#define CONFIG_OMAP3_SPI

/* EEPROM */
#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
#define CONFIG_SYS_EEPROM_SIZE			256

#define CONFIG_CMD_EEPROM_LAYOUT
#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v1, v2, v3"

#endif /* __CONFIG_H */
Commit	Line	Data
b09bf723 IG	1	/*
	2	* (C) Copyright 2013 CompuLab, Ltd.
	3	* Author: Igor Grinberg <[email protected]>
	4	*
	5	* Configuration settings for the CompuLab CM-T3517 board
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	/*
	14	* High Level Configuration Options
	15	*/
	16	#define CONFIG_OMAP /* in a TI OMAP core */
	17	#define CONFIG_CM_T3517 /* working with CM-T3517 */
	18	#define CONFIG_OMAP_COMMON
c6f90e14 NM	19	/* Common ARM Erratas */
	20	#define CONFIG_ARM_ERRATA_454179
	21	#define CONFIG_ARM_ERRATA_430973
	22	#define CONFIG_ARM_ERRATA_621766
b09bf723 IG	23
	24	#define CONFIG_SYS_TEXT_BASE 0x80008000
	25
	26	/*
	27	* This is needed for the DMA stuff.
	28	* Although the default iss 64, we still define it
	29	* to be on the safe side once the default is changed.
	30	*/
b09bf723 IG	31
	32	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
	33
	34	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	35	#include <asm/arch/omap.h>
b09bf723	36
f3b44e8b DL	37	#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517
f3b44e8b DL	38
b09bf723 IG	39	/* Clock Defines */
	40	#define V_OSCK 26000000 /* Clock output from T2 */
	41	#define V_SCLK (V_OSCK >> 1)
	42
	43	#define CONFIG_MISC_INIT_R
	44
b09bf723 IG	45	/*
	46	* The early kernel mapping on ARM currently only maps from the base of DRAM
	47	* to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
	48	* The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
	49	* so that leaves DRAM base to DRAM base + 0x4000 available.
	50	*/
	51	#define CONFIG_SYS_BOOTMAPSZ 0x4000
	52
	53	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	54	#define CONFIG_SETUP_MEMORY_TAGS
	55	#define CONFIG_INITRD_TAG
	56	#define CONFIG_REVISION_TAG
	57	#define CONFIG_SERIAL_TAG
	58
	59	/*
	60	* Size of malloc() pool
	61	*/
2f6e4bf8	62	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
b09bf723 IG	63	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
	64
	65	/*
	66	* Hardware drivers
	67	*/
	68
	69	/*
	70	* NS16550 Configuration
	71	*/
b09bf723 IG	72	#define CONFIG_SYS_NS16550_SERIAL
	73	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	74	#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	75
	76	/*
	77	* select serial console configuration
	78	*/
	79	#define CONFIG_CONS_INDEX 3
	80	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	81	#define CONFIG_SERIAL3 3 /* UART3 */
b09bf723 IG	82
	83	/* allow to overwrite serial and ethaddr */
	84	#define CONFIG_ENV_OVERWRITE
	85	#define CONFIG_BAUDRATE 115200
	86	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	87	115200}
	88
	89	#define CONFIG_OMAP_GPIO
	90
	91	#define CONFIG_GENERIC_MMC
	92	#define CONFIG_MMC
	93	#define CONFIG_OMAP_HSMMC
	94	#define CONFIG_DOS_PARTITION
	95
011f5c13 IG	96	/* USB */
	97	#define CONFIG_USB_MUSB_AM35X
	98
	99	#ifndef CONFIG_USB_MUSB_AM35X
	100	#define CONFIG_USB_OMAP3
	101	#define CONFIG_USB_EHCI
	102	#define CONFIG_USB_EHCI_OMAP
	103	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
	104	#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
	105	#else /* !CONFIG_USB_MUSB_AM35X */
95de1e2f	106	#define CONFIG_USB_MUSB_PIO_ONLY
011f5c13 IG	107	#endif /* CONFIG_USB_MUSB_AM35X */
011f5c13 IG	108
b09bf723	109	/* commands to include */
b09bf723 IG	110	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
	111	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
	112	#define CONFIG_MTD_PARTITIONS
	113	#define MTDIDS_DEFAULT "nand0=nand"
	114	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
	115	"1920k(u-boot),256k(u-boot-env),"\
	116	"4m(kernel),-(fs)"
	117
b09bf723	118	#define CONFIG_CMD_NAND /* NAND support */
b09bf723	119
b09bf723 IG	120	#define CONFIG_SYS_NO_FLASH
	121	#define CONFIG_SYS_I2C
	122	#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
	123	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	124	#define CONFIG_SYS_I2C_OMAP34XX
	125	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	126	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	127	#define CONFIG_SYS_I2C_EEPROM_BUS 0
	128	#define CONFIG_I2C_MULTI_BUS
	129
	130	/*
	131	* Board NAND Info.
	132	*/
b09bf723 IG	133	#define CONFIG_NAND_OMAP_GPMC
	134	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	135	/* to access nand */
	136	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	137	/* to access nand at */
	138	/* CS0 */
	139	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	140	/* devices */
	141
	142	/* Environment information */
b09bf723 IG	143	#define CONFIG_EXTRA_ENV_SETTINGS \
	144	"loadaddr=0x82000000\0" \
	145	"baudrate=115200\0" \
	146	"console=ttyO2,115200n8\0" \
e093d0b2	147	"netretry=yes\0" \
b09bf723 IG	148	"mpurate=auto\0" \
	149	"vram=12M\0" \
	150	"dvimode=1024x768MR-16@60\0" \
	151	"defaultdisplay=dvi\0" \
	152	"mmcdev=0\0" \
	153	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
	154	"mmcrootfstype=ext4\0" \
	155	"nandroot=/dev/mtdblock4 rw\0" \
	156	"nandrootfstype=ubifs\0" \
	157	"mmcargs=setenv bootargs console=${console} " \
	158	"mpurate=${mpurate} " \
	159	"vram=${vram} " \
	160	"omapfb.mode=dvi:${dvimode} " \
	161	"omapdss.def_disp=${defaultdisplay} " \
	162	"root=${mmcroot} " \
	163	"rootfstype=${mmcrootfstype}\0" \
	164	"nandargs=setenv bootargs console=${console} " \
	165	"mpurate=${mpurate} " \
	166	"vram=${vram} " \
	167	"omapfb.mode=dvi:${dvimode} " \
	168	"omapdss.def_disp=${defaultdisplay} " \
	169	"root=${nandroot} " \
	170	"rootfstype=${nandrootfstype}\0" \
	171	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	172	"bootscript=echo Running bootscript from mmc ...; " \
	173	"source ${loadaddr}\0" \
	174	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	175	"mmcboot=echo Booting from mmc ...; " \
	176	"run mmcargs; " \
	177	"bootm ${loadaddr}\0" \
	178	"nandboot=echo Booting from nand ...; " \
	179	"run nandargs; " \
	180	"nand read ${loadaddr} 2a0000 400000; " \
	181	"bootm ${loadaddr}\0" \
	182
b09bf723 IG	183	#define CONFIG_BOOTCOMMAND \
	184	"mmc dev ${mmcdev}; if mmc rescan; then " \
	185	"if run loadbootscript; then " \
	186	"run bootscript; " \
	187	"else " \
	188	"if run loaduimage; then " \
	189	"run mmcboot; " \
	190	"else run nandboot; " \
	191	"fi; " \
	192	"fi; " \
	193	"else run nandboot; fi"
	194
	195	/*
	196	* Miscellaneous configurable options
	197	*/
	198	#define CONFIG_AUTO_COMPLETE
	199	#define CONFIG_CMDLINE_EDITING
	200	#define CONFIG_TIMESTAMP
	201	#define CONFIG_SYS_AUTOLOAD "no"
	202	#define CONFIG_SYS_LONGHELP /* undef to save memory */
b09bf723 IG	203	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	204	/* Print Buffer Size */
	205	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	206	sizeof(CONFIG_SYS_PROMPT) + 16)
	207	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
	208	/* Boot Argument Buffer Size */
	209	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	210
	211	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
	212
	213	/*
	214	* AM3517 has 12 GP timers, they can be driven by the system clock
	215	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	216	* This rate is divided by a local divisor.
	217	*/
	218	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	219	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	220	#define CONFIG_SYS_HZ 1000
	221
	222	/*-----------------------------------------------------------------------
	223	* Physical Memory Map
	224	*/
	225	#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */
	226	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	227	#define CONFIG_SYS_CS0_SIZE (256 << 20)
	228
	229	/*-----------------------------------------------------------------------
	230	* FLASH and environment organization
	231	*/
	232
	233	/* ** PISMO SUPPORT * */
	234	/* Monitor at start of flash */
	235	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	236	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
	237
	238	#define CONFIG_ENV_IS_IN_NAND
	239	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	240	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	241	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	242
a8a78c74 IG	243	#if defined(CONFIG_CMD_NET)
	244	#define CONFIG_DRIVER_TI_EMAC
	245	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	246	#define CONFIG_MII
	247	#define CONFIG_SMC911X
	248	#define CONFIG_SMC911X_32_BIT
	249	#define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20))
e093d0b2 DL	250	#define CONFIG_ARP_TIMEOUT 200UL
e093d0b2 DL	251	#define CONFIG_NET_RETRY_COUNT 5
a8a78c74 IG	252	#endif /* CONFIG_CMD_NET */
a8a78c74 IG	253
b09bf723 IG	254	/* additions for new relocation code, must be added to all boards */
	255	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	256	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	257	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	258	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	259	CONFIG_SYS_INIT_RAM_SIZE - \
	260	GENERATED_GBL_DATA_SIZE)
	261
	262	/* Status LED */
	263	#define CONFIG_STATUS_LED /* Status LED enabled */
	264	#define CONFIG_BOARD_SPECIFIC_LED
	265	#define CONFIG_GPIO_LED
	266	#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
	267	#define GREEN_LED_DEV 0
	268	#define STATUS_LED_BIT GREEN_LED_GPIO
	269	#define STATUS_LED_STATE STATUS_LED_ON
	270	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	271	#define STATUS_LED_BOOT GREEN_LED_DEV
	272
	273	/* GPIO banks */
	274	#ifdef CONFIG_STATUS_LED
	275	#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
	276	#endif
	277
40bbd52a IG	278	/* Display Configuration */
	279	#define CONFIG_OMAP3_GPIO_2
	280	#define CONFIG_OMAP3_GPIO_5
	281	#define CONFIG_VIDEO_OMAP3
	282	#define LCD_BPP LCD_COLOR16
	283
40bbd52a IG	284	#define CONFIG_SPLASH_SCREEN
	285	#define CONFIG_SPLASHIMAGE_GUARD
	286	#define CONFIG_CMD_BMP
	287	#define CONFIG_BMP_16BPP
	288	#define CONFIG_SCF0403_LCD
	289
	290	#define CONFIG_OMAP3_SPI
	291
19a90ed6 NK	292	/* EEPROM */
	293	#define CONFIG_CMD_EEPROM
	294	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	295	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	296	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	297	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	298	#define CONFIG_SYS_EEPROM_SIZE 256
	299
	300	#define CONFIG_CMD_EEPROM_LAYOUT
	301	#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v1, v2, v3"
	302
b09bf723	303	#endif /* __CONFIG_H */