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bf9e3b38 WD |
1 | /* |
2 | * Configuation settings for the Motorola MC5272C3 board. | |
3 | * | |
4 | * (C) Copyright 2003 Josef Baumgartner <[email protected]> | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
bf9e3b38 | 7 | */ |
4e5ca3eb | 8 | |
bf9e3b38 WD |
9 | /* |
10 | * board/config.h - configuration options, board specific | |
11 | */ | |
12 | ||
13 | #ifndef _M5272C3_H | |
14 | #define _M5272C3_H | |
15 | ||
16 | /* | |
17 | * High Level Configuration Options | |
18 | * (easy to change) | |
19 | */ | |
f28e1bd9 | 20 | #define CONFIG_MCFTMR |
4e5ca3eb | 21 | |
f28e1bd9 | 22 | #define CONFIG_MCFUART |
6d0f6bcf | 23 | #define CONFIG_SYS_UART_PORT (0) |
79e0799c | 24 | #define CONFIG_BAUDRATE 115200 |
bf9e3b38 | 25 | |
f28e1bd9 | 26 | #undef CONFIG_WATCHDOG |
bf9e3b38 WD |
27 | #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ |
28 | ||
f28e1bd9 | 29 | #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ |
bf9e3b38 WD |
30 | |
31 | /* Configuration for environment | |
32 | * Environment is embedded in u-boot in the second sector of the flash | |
33 | */ | |
34 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
0e8d1586 JCPV |
35 | #define CONFIG_ENV_OFFSET 0x4000 |
36 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 37 | #define CONFIG_ENV_IS_IN_FLASH 1 |
bf9e3b38 | 38 | #else |
0e8d1586 JCPV |
39 | #define CONFIG_ENV_ADDR 0xffe04000 |
40 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 41 | #define CONFIG_ENV_IS_IN_FLASH 1 |
bf9e3b38 WD |
42 | #endif |
43 | ||
5296cb1d | 44 | #define LDS_BOARD_TEXT \ |
45 | . = DEFINED(env_offset) ? env_offset : .; \ | |
46 | common/env_embedded.o (.text); | |
47 | ||
659e2f67 JL |
48 | /* |
49 | * BOOTP options | |
50 | */ | |
51 | #define CONFIG_BOOTP_BOOTFILESIZE | |
52 | #define CONFIG_BOOTP_BOOTPATH | |
53 | #define CONFIG_BOOTP_GATEWAY | |
54 | #define CONFIG_BOOTP_HOSTNAME | |
55 | ||
8353e139 JL |
56 | /* |
57 | * Command line configuration. | |
58 | */ | |
dd9f054e | 59 | #define CONFIG_CMD_CACHE |
8353e139 | 60 | #define CONFIG_CMD_MII |
f28e1bd9 | 61 | #define CONFIG_CMD_PING |
f28e1bd9 | 62 | #define CONFIG_CMD_ELF |
8353e139 | 63 | |
8353e139 | 64 | |
bf9e3b38 | 65 | #define CONFIG_BOOTDELAY 5 |
f28e1bd9 TL |
66 | #define CONFIG_MCFFEC |
67 | #ifdef CONFIG_MCFFEC | |
f28e1bd9 | 68 | # define CONFIG_MII 1 |
d53cf6a9 | 69 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
70 | # define CONFIG_SYS_DISCOVER_PHY |
71 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
72 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
f28e1bd9 | 73 | |
6d0f6bcf JCPV |
74 | # define CONFIG_SYS_FEC0_PINMUX 0 |
75 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
53677ef1 | 76 | # define MCFFEC_TOUT_LOOP 50000 |
6d0f6bcf JCPV |
77 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
78 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
f28e1bd9 TL |
79 | # define FECDUPLEX FULL |
80 | # define FECSPEED _100BASET | |
81 | # else | |
6d0f6bcf JCPV |
82 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
83 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
f28e1bd9 | 84 | # endif |
6d0f6bcf | 85 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
f28e1bd9 TL |
86 | #endif |
87 | ||
88 | #ifdef CONFIG_MCFFEC | |
f28e1bd9 TL |
89 | # define CONFIG_IPADDR 192.162.1.2 |
90 | # define CONFIG_NETMASK 255.255.255.0 | |
91 | # define CONFIG_SERVERIP 192.162.1.1 | |
92 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
f28e1bd9 TL |
93 | #endif /* CONFIG_MCFFEC */ |
94 | ||
95 | #define CONFIG_HOSTNAME M5272C3 | |
96 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
97 | "netdev=eth0\0" \ | |
98 | "loadaddr=10000\0" \ | |
99 | "u-boot=u-boot.bin\0" \ | |
100 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
101 | "upd=run load; run prog\0" \ | |
102 | "prog=prot off ffe00000 ffe3ffff;" \ | |
103 | "era ffe00000 ffe3ffff;" \ | |
104 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ | |
105 | "save\0" \ | |
106 | "" | |
bf9e3b38 | 107 | |
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_PROMPT "-> " |
109 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
bf9e3b38 | 110 | |
8353e139 | 111 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 112 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
bf9e3b38 | 113 | #else |
6d0f6bcf | 114 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
bf9e3b38 | 115 | #endif |
bf9e3b38 | 116 | |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
118 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
119 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
120 | #define CONFIG_SYS_LOAD_ADDR 0x20000 | |
121 | #define CONFIG_SYS_MEMTEST_START 0x400 | |
122 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
6d0f6bcf | 123 | #define CONFIG_SYS_CLK 66000000 |
bf9e3b38 WD |
124 | |
125 | /* | |
126 | * Low Level Configuration Settings | |
127 | * (address mappings, register initial values, etc.) | |
128 | * You should know what you are doing if you make changes here. | |
129 | */ | |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
131 | #define CONFIG_SYS_SCR 0x0003 | |
132 | #define CONFIG_SYS_SPR 0xffff | |
bf9e3b38 | 133 | |
bf9e3b38 WD |
134 | /*----------------------------------------------------------------------- |
135 | * Definitions for initial stack pointer and data area (in DPRAM) | |
136 | */ | |
6d0f6bcf | 137 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 138 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ |
25ddd1fb | 139 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 140 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
bf9e3b38 WD |
141 | |
142 | /*----------------------------------------------------------------------- | |
143 | * Start addresses for the final memory configuration | |
144 | * (Set up by the startup code) | |
6d0f6bcf | 145 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
bf9e3b38 | 146 | */ |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
148 | #define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ | |
149 | #define CONFIG_SYS_FLASH_BASE 0xffe00000 | |
bf9e3b38 WD |
150 | |
151 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
6d0f6bcf | 152 | #define CONFIG_SYS_MONITOR_BASE 0x20000 |
bf9e3b38 | 153 | #else |
6d0f6bcf | 154 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
bf9e3b38 WD |
155 | #endif |
156 | ||
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
158 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
159 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
bf9e3b38 WD |
160 | |
161 | /* | |
162 | * For booting Linux, the board info and command line data | |
163 | * have to be in the first 8 MB of memory, since this is | |
164 | * the maximum mapped by the Linux kernel during initialization ?? | |
165 | */ | |
6d0f6bcf | 166 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
bf9e3b38 | 167 | |
b202816c | 168 | /* |
bf9e3b38 WD |
169 | * FLASH organization |
170 | */ | |
b202816c TL |
171 | #define CONFIG_SYS_FLASH_CFI |
172 | #ifdef CONFIG_SYS_FLASH_CFI | |
173 | # define CONFIG_FLASH_CFI_DRIVER 1 | |
174 | # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ | |
175 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
176 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
177 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
178 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
179 | #endif | |
bf9e3b38 WD |
180 | |
181 | /*----------------------------------------------------------------------- | |
182 | * Cache Configuration | |
183 | */ | |
6d0f6bcf | 184 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
bf9e3b38 | 185 | |
dd9f054e | 186 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 187 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 188 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 189 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
190 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
191 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
192 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
193 | CF_ACR_EN | CF_ACR_SM_ALL) | |
194 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ | |
195 | CF_CACR_DISD | CF_CACR_INVI | \ | |
196 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
197 | CF_CACR_EUSP) | |
198 | ||
bf9e3b38 WD |
199 | /*----------------------------------------------------------------------- |
200 | * Memory bank definitions | |
201 | */ | |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 |
203 | #define CONFIG_SYS_OR0_PRELIM 0xFFE00014 | |
204 | #define CONFIG_SYS_BR1_PRELIM 0 | |
205 | #define CONFIG_SYS_OR1_PRELIM 0 | |
206 | #define CONFIG_SYS_BR2_PRELIM 0x30000001 | |
207 | #define CONFIG_SYS_OR2_PRELIM 0xFFF80000 | |
208 | #define CONFIG_SYS_BR3_PRELIM 0 | |
209 | #define CONFIG_SYS_OR3_PRELIM 0 | |
210 | #define CONFIG_SYS_BR4_PRELIM 0 | |
211 | #define CONFIG_SYS_OR4_PRELIM 0 | |
212 | #define CONFIG_SYS_BR5_PRELIM 0 | |
213 | #define CONFIG_SYS_OR5_PRELIM 0 | |
214 | #define CONFIG_SYS_BR6_PRELIM 0 | |
215 | #define CONFIG_SYS_OR6_PRELIM 0 | |
216 | #define CONFIG_SYS_BR7_PRELIM 0x00000701 | |
217 | #define CONFIG_SYS_OR7_PRELIM 0xFFC0007C | |
bf9e3b38 WD |
218 | |
219 | /*----------------------------------------------------------------------- | |
220 | * Port configuration | |
221 | */ | |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_PACNT 0x00000000 |
223 | #define CONFIG_SYS_PADDR 0x0000 | |
224 | #define CONFIG_SYS_PADAT 0x0000 | |
225 | #define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ | |
226 | #define CONFIG_SYS_PBDDR 0x0000 | |
227 | #define CONFIG_SYS_PBDAT 0x0000 | |
228 | #define CONFIG_SYS_PDCNT 0x00000000 | |
f28e1bd9 | 229 | #endif /* _M5272C3_H */ |