[J-u-boot.git] / board / lwmon / lwmon.c

/***********************************************************************
 *
M* Modul:         lwmon.c
M*
M* Content:       LWMON specific U-Boot commands.
 *
 * (C) Copyright 2001, 2002
 * DENX Software Engineering
 * Wolfgang Denk, [email protected]
 * All rights reserved.
 *
D* Design:        [email protected]
C* Coding:        [email protected]
V* Verification:  [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 ***********************************************************************/

/*---------------------------- Headerfiles ----------------------------*/
#include <common.h>
#include <mpc8xx.h>
#include <commproc.h>
#include <i2c.h>
#include <command.h>
#include <malloc.h>
#include <post.h>
#include <serial.h>

#include <linux/types.h>
#include <linux/string.h>	/* for strdup */

/*------------------------ Local prototypes ---------------------------*/
static long int dram_size (long int, long int *, long int);
static void kbd_init (void);
static int compare_magic (uchar *kbd_data, uchar *str);


/*--------------------- Local macros and constants --------------------*/
#define	_NOT_USED_	0xFFFFFFFF

#ifdef CONFIG_MODEM_SUPPORT
static int key_pressed(void);
extern void disable_putc(void);
#endif /* CONFIG_MODEM_SUPPORT */

/*
 * 66 MHz SDRAM access using UPM A
 */
const uint sdram_table[] =
{
#if defined(CFG_MEMORY_75) || defined(CFG_MEMORY_8E)
	/*
	 * Single Read. (Offset 0 in UPM RAM)
	 */
	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
	0x1FF5FC47, /* last */
	/*
	 * SDRAM Initialization (offset 5 in UPM RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	/*
	 * Burst Read. (Offset 8 in UPM RAM)
	 */
	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPM RAM)
	 */
	0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPM RAM)
	 */
	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
	0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPM RAM)
	 */
	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC84, 0xFFFFFC07, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPM RAM)
	 */
	0x7FFFFC07, /* last */
		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
#endif
#ifdef CFG_MEMORY_7E
	/*
	 * Single Read. (Offset 0 in UPM RAM)
	 */
	0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */
	_NOT_USED_,
	/*
	 * SDRAM Initialization (offset 5 in UPM RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	/*
	 * Burst Read. (Offset 8 in UPM RAM)
	 */
	0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00,
	0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPM RAM)
	 */
	0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPM RAM)
	 */
	0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00,
	0xE1BAFC04, 0x1FF5FC47, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPM RAM)
	 */
	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC84, 0xFFFFFC07, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPM RAM)
	 */
	0x7FFFFC07, /* last */
		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
#endif
};

/*
 * Check Board Identity:
 *
 */

/***********************************************************************
F* Function:     int checkboard (void) P*A*Z*
 *
P* Parameters:   none
P*
P* Returnvalue:  int - 0 is always returned
 *
Z* Intention:    This function is the checkboard() method implementation
Z*               for the lwmon board.  Only a standard message is printed.
 *
D* Design:       [email protected]
C* Coding:       [email protected]
V* Verification: [email protected]
 ***********************************************************************/
int checkboard (void)
{
	puts ("Board: LICCON Konsole LCD2\n");
	return (0);
}

/***********************************************************************
F* Function:     long int initdram (int board_type) P*A*Z*
 *
P* Parameters:   int board_type
P*                - Usually type of the board - ignored here.
P*
P* Returnvalue:  long int
P*                - Size of initialized memory
 *
Z* Intention:    This function is the initdram() method implementation
Z*               for the lwmon board.
Z*               The memory controller is initialized to access the
Z*               DRAM.
 *
D* Design:       [email protected]
C* Coding:       [email protected]
V* Verification: [email protected]
 ***********************************************************************/
long int initdram (int board_type)
{
	volatile immap_t *immr = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;
	long int size_b0;
	long int size8, size9;
	int i;

	/*
	 * Configure UPMA for SDRAM
	 */
	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));

	memctl->memc_mptpr = CFG_MPTPR;

	/* burst length=4, burst type=sequential, CAS latency=2 */
	memctl->memc_mar = CFG_MAR;

	/*
	 * Map controller bank 3 to the SDRAM bank at preliminary address.
	 */
	memctl->memc_or3 = CFG_OR3_PRELIM;
	memctl->memc_br3 = CFG_BR3_PRELIM;

	/* initialize memory address register */
	memctl->memc_mamr = CFG_MAMR_8COL;	/* refresh not enabled yet */

	/* mode initialization (offset 5) */
	udelay (200);				/* 0x80006105 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);

	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
	udelay (1);				/* 0x80006130 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
	udelay (1);				/* 0x80006130 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);

	udelay (1);				/* 0x80006106 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);

	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */

	udelay (200);

	/* Need at least 10 DRAM accesses to stabilize */
	for (i = 0; i < 10; ++i) {
		volatile unsigned long *addr =
			(volatile unsigned long *) SDRAM_BASE3_PRELIM;
		unsigned long val;

		val = *(addr + i);
		*(addr + i) = val;
	}

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 * try 8 column mode
	 */
	size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);

	udelay (1000);

	/*
	 * try 9 column mode
	 */
	size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);

	if (size8 < size9) {		/* leave configuration at 9 columns */
		size_b0 = size9;
		memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTAE;
		udelay (500);
	} else {			/* back to 8 columns            */
		size_b0 = size8;
		memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
		udelay (500);
	}

	/*
	 * Final mapping:
	 */

	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) |
			OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
	udelay (1000);

	return (size_b0);
}

/***********************************************************************
F* Function:     static long int dram_size (long int mamr_value,
F*                                          long int *base,
F*                                          long int maxsize) P*A*Z*
 *
P* Parameters:   long int mamr_value
P*                - Value for MAMR for the test
P*               long int *base
P*                - Base address for the test
P*               long int maxsize
P*                - Maximum size to test for
P*
P* Returnvalue:  long int
P*                - Size of probed memory
 *
Z* Intention:    Check memory range for valid RAM. A simple memory test
Z*               determines the actually available RAM size between
Z*               addresses `base' and `base + maxsize'. Some (not all)
Z*               hardware errors are detected:
Z*                - short between address lines
Z*                - short between data lines
 *
D* Design:       [email protected]
C* Coding:       [email protected]
V* Verification: [email protected]
 ***********************************************************************/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
	volatile immap_t *immr = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;

	memctl->memc_mamr = mamr_value;

	return (get_ram_size(base, maxsize));
}

/* ------------------------------------------------------------------------- */

#ifndef	PB_ENET_TENA
# define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
#endif

/***********************************************************************
F* Function:     int board_early_init_f (void) P*A*Z*
 *
P* Parameters:   none
P*
P* Returnvalue:  int
P*                - 0 is always returned.
 *
Z* Intention:    This function is the board_early_init_f() method implementation
Z*               for the lwmon board.
Z*               Disable Ethernet TENA on Port B.
 *
D* Design:       [email protected]
C* Coding:       [email protected]
V* Verification: [email protected]
 ***********************************************************************/
int board_early_init_f (void)
{
	volatile immap_t *immr = (immap_t *) CFG_IMMR;

	/* Disable Ethernet TENA on Port B
	 * Necessary because of pull up in COM3 port.
	 *
	 * This is just a preliminary fix, intended to turn off TENA
	 * as soon as possible to avoid noise on the network. Once
Commit	Line	Data
e2211743 WD	1	/***********************************************************************
	2	*
	3	M* Modul: lwmon.c
	4	M*
	5	M* Content: LWMON specific U-Boot commands.
	6	*
	7	* (C) Copyright 2001, 2002
	8	* DENX Software Engineering
	9	* Wolfgang Denk, [email protected]
	10	* All rights reserved.
	11	*
	12	D* Design: [email protected]
	13	C* Coding: [email protected]
	14	V* Verification: [email protected]
	15	*
	16	* See file CREDITS for list of people who contributed to this
	17	* project.
	18	*
	19	* This program is free software; you can redistribute it and/or
	20	* modify it under the terms of the GNU General Public License as
	21	* published by the Free Software Foundation; either version 2 of
	22	* the License, or (at your option) any later version.
	23	*
	24	* This program is distributed in the hope that it will be useful,
	25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	27	* GNU General Public License for more details.
	28	*
	29	* You should have received a copy of the GNU General Public License
	30	* along with this program; if not, write to the Free Software
	31	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	32	* MA 02111-1307 USA
	33	***********************************************************************/
	34
	35	/---------------------------- Headerfiles ----------------------------/
	36	#include <common.h>
	37	#include <mpc8xx.h>
	38	#include <commproc.h>
	39	#include <i2c.h>
	40	#include <command.h>
e2211743 WD	41	#include <malloc.h>
e2211743 WD	42	#include <post.h>
281e00a3	43	#include <serial.h>
e2211743 WD	44
	45	#include <linux/types.h>
	46	#include <linux/string.h> /* for strdup */
	47
	48	/------------------------ Local prototypes ---------------------------/
	49	static long int dram_size (long int, long int *, long int);
4532cb69 WD	50	static void kbd_init (void);
4532cb69 WD	51	static int compare_magic (uchar kbd_data, uchar str);
e2211743 WD	52
	53
	54	/--------------------- Local macros and constants --------------------/
	55	#define _NOT_USED_ 0xFFFFFFFF
	56
4532cb69 WD	57	#ifdef CONFIG_MODEM_SUPPORT
	58	static int key_pressed(void);
	59	extern void disable_putc(void);
	60	#endif /* CONFIG_MODEM_SUPPORT */
	61
e2211743 WD	62	/*
	63	* 66 MHz SDRAM access using UPM A
	64	*/
	65	const uint sdram_table[] =
	66	{
	67	#if defined(CFG_MEMORY_75) \|\| defined(CFG_MEMORY_8E)
	68	/*
	69	* Single Read. (Offset 0 in UPM RAM)
	70	*/
	71	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
	72	0x1FF5FC47, /* last */
	73	/*
	74	* SDRAM Initialization (offset 5 in UPM RAM)
	75	*
8bde7f77 WD	76	* This is no UPM entry point. The following definition uses
	77	* the remaining space to establish an initialization
	78	* sequence, which is executed by a RUN command.
e2211743 WD	79	*
	80	*/
	81	0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	82	/*
	83	* Burst Read. (Offset 8 in UPM RAM)
	84	*/
	85	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
	86	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
	87	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	88	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	89	/*
	90	* Single Write. (Offset 18 in UPM RAM)
	91	*/
	92	0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
	93	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	94	/*
	95	* Burst Write. (Offset 20 in UPM RAM)
	96	*/
	97	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
	98	0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */
	99	_NOT_USED_,
	100	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	101	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	102	/*
	103	* Refresh (Offset 30 in UPM RAM)
	104	*/
	105	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	106	0xFFFFFC84, 0xFFFFFC07, /* last */
	107	_NOT_USED_, _NOT_USED_,
	108	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	109	/*
	110	* Exception. (Offset 3c in UPM RAM)
	111	*/
	112	0x7FFFFC07, /* last */
	113	0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
	114	#endif
	115	#ifdef CFG_MEMORY_7E
	116	/*
	117	* Single Read. (Offset 0 in UPM RAM)
	118	*/
	119	0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */
	120	_NOT_USED_,
	121	/*
	122	* SDRAM Initialization (offset 5 in UPM RAM)
	123	*
8bde7f77 WD	124	* This is no UPM entry point. The following definition uses
	125	* the remaining space to establish an initialization
	126	* sequence, which is executed by a RUN command.
e2211743 WD	127	*
	128	*/
	129	0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	130	/*
	131	* Burst Read. (Offset 8 in UPM RAM)
	132	*/
	133	0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00,
	134	0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
8bde7f77	135	_NOT_USED_,
e2211743 WD	136	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	137	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	138	/*
	139	* Single Write. (Offset 18 in UPM RAM)
	140	*/
	141	0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */
	142	_NOT_USED_,
	143	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	144	/*
	145	* Burst Write. (Offset 20 in UPM RAM)
	146	*/
	147	0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00,
	148	0xE1BAFC04, 0x1FF5FC47, /* last */
8bde7f77	149	_NOT_USED_, _NOT_USED_,
e2211743 WD	150	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	151	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	152	/*
	153	* Refresh (Offset 30 in UPM RAM)
	154	*/
	155	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	156	0xFFFFFC84, 0xFFFFFC07, /* last */
	157	_NOT_USED_, _NOT_USED_,
	158	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	159	/*
	160	* Exception. (Offset 3c in UPM RAM)
	161	*/
	162	0x7FFFFC07, /* last */
	163	0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
	164	#endif
	165	};
	166
	167	/*
	168	* Check Board Identity:
	169	*
	170	*/
	171
	172	/***********************************************************************
	173	F* Function: int checkboard (void) PAZ*
	174	*
	175	P* Parameters: none
	176	P*
	177	P* Returnvalue: int - 0 is always returned
	178	*
	179	Z* Intention: This function is the checkboard() method implementation
	180	Z* for the lwmon board. Only a standard message is printed.
	181	*
	182	D* Design: [email protected]
	183	C* Coding: [email protected]
	184	V* Verification: [email protected]
	185	***********************************************************************/
	186	int checkboard (void)
	187	{
8564acf9	188	puts ("Board: LICCON Konsole LCD2\n");
e2211743 WD	189	return (0);
	190	}
	191
	192	/***********************************************************************
	193	F* Function: long int initdram (int board_type) PAZ*
	194	*
	195	P* Parameters: int board_type
	196	P* - Usually type of the board - ignored here.
	197	P*
	198	P* Returnvalue: long int
	199	P* - Size of initialized memory
	200	*
	201	Z* Intention: This function is the initdram() method implementation
	202	Z* for the lwmon board.
	203	Z* The memory controller is initialized to access the
	204	Z* DRAM.
	205	*
	206	D* Design: [email protected]
	207	C* Coding: [email protected]
	208	V* Verification: [email protected]
	209	***********************************************************************/
	210	long int initdram (int board_type)
	211	{
	212	volatile immap_t immr = (immap_t ) CFG_IMMR;
	213	volatile memctl8xx_t *memctl = &immr->im_memctl;
	214	long int size_b0;
	215	long int size8, size9;
	216	int i;
	217
	218	/*
	219	* Configure UPMA for SDRAM
	220	*/
	221	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
	222
	223	memctl->memc_mptpr = CFG_MPTPR;
	224
	225	/* burst length=4, burst type=sequential, CAS latency=2 */
	226	memctl->memc_mar = CFG_MAR;
	227
	228	/*
	229	* Map controller bank 3 to the SDRAM bank at preliminary address.
	230	*/
	231	memctl->memc_or3 = CFG_OR3_PRELIM;
	232	memctl->memc_br3 = CFG_BR3_PRELIM;
	233
	234	/* initialize memory address register */
	235	memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */
	236
	237	/* mode initialization (offset 5) */
	238	udelay (200); /* 0x80006105 */
	239	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS3 \| MCR_MLCF (1) \| MCR_MAD (0x05);
	240
	241	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
	242	udelay (1); /* 0x80006130 */
	243	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS3 \| MCR_MLCF (1) \| MCR_MAD (0x30);
	244	udelay (1); /* 0x80006130 */
	245	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS3 \| MCR_MLCF (1) \| MCR_MAD (0x30);
	246
	247	udelay (1); /* 0x80006106 */
	248	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS3 \| MCR_MLCF (1) \| MCR_MAD (0x06);
	249
2535d602	250	memctl->memc_mamr \|= MAMR_PTAE; /* refresh enabled */
e2211743 WD	251
	252	udelay (200);
	253
	254	/* Need at least 10 DRAM accesses to stabilize */
	255	for (i = 0; i < 10; ++i) {
	256	volatile unsigned long *addr =
	257	(volatile unsigned long *) SDRAM_BASE3_PRELIM;
	258	unsigned long val;
	259
	260	val = *(addr + i);
	261	*(addr + i) = val;
	262	}
	263
	264	/*
	265	* Check Bank 0 Memory Size for re-configuration
	266	*
	267	* try 8 column mode
	268	*/
	269	size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
	270
	271	udelay (1000);
	272
	273	/*
	274	* try 9 column mode
	275	*/
	276	size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
	277
	278	if (size8 < size9) { /* leave configuration at 9 columns */
	279	size_b0 = size9;
2535d602	280	memctl->memc_mamr = CFG_MAMR_9COL \| MAMR_PTAE;
e2211743 WD	281	udelay (500);
	282	} else { /* back to 8 columns */
	283	size_b0 = size8;
2535d602	284	memctl->memc_mamr = CFG_MAMR_8COL \| MAMR_PTAE;
e2211743 WD	285	udelay (500);
	286	}
	287
	288	/*
	289	* Final mapping:
	290	*/
	291
	292	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) \|
	293	OR_CSNT_SAM \| OR_G5LS \| SDRAM_TIMING;
	294	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
	295	udelay (1000);
	296
	297	return (size_b0);
	298	}
	299
	300	/***********************************************************************
	301	F* Function: static long int dram_size (long int mamr_value,
	302	F* long int *base,
	303	F* long int maxsize) PAZ*
	304	*
	305	P* Parameters: long int mamr_value
	306	P* - Value for MAMR for the test
	307	P* long int *base
	308	P* - Base address for the test
	309	P* long int maxsize
	310	P* - Maximum size to test for
	311	P*
	312	P* Returnvalue: long int
	313	P* - Size of probed memory
	314	*
	315	Z* Intention: Check memory range for valid RAM. A simple memory test
	316	Z* determines the actually available RAM size between
	317	Z* addresses `base' and `base + maxsize'. Some (not all)
	318	Z* hardware errors are detected:
	319	Z* - short between address lines
	320	Z* - short between data lines
	321	*
	322	D* Design: [email protected]
	323	C* Coding: [email protected]
	324	V* Verification: [email protected]
	325	***********************************************************************/
	326	static long int dram_size (long int mamr_value, long int *base, long int maxsize)
	327	{
	328	volatile immap_t immr = (immap_t ) CFG_IMMR;
	329	volatile memctl8xx_t *memctl = &immr->im_memctl;
e2211743 WD	330
	331	memctl->memc_mamr = mamr_value;
	332
c83bf6a2	333	return (get_ram_size(base, maxsize));
e2211743 WD	334	}
	335
	336	/* ------------------------------------------------------------------------- */
	337
	338	#ifndef PB_ENET_TENA
	339	# define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
	340	#endif
	341
	342	/***********************************************************************
c837dcb1	343	F* Function: int board_early_init_f (void) PAZ*
e2211743 WD	344	*
	345	P* Parameters: none
	346	P*
	347	P* Returnvalue: int
	348	P* - 0 is always returned.
	349	*
c837dcb1	350	Z* Intention: This function is the board_early_init_f() method implementation
e2211743 WD	351	Z* for the lwmon board.
	352	Z* Disable Ethernet TENA on Port B.
	353	*
	354	D* Design: [email protected]
	355	C* Coding: [email protected]
	356	V* Verification: [email protected]
	357	***********************************************************************/
c837dcb1	358	int board_early_init_f (void)
e2211743 WD	359	{
	360	volatile immap_t immr = (immap_t ) CFG_IMMR;
	361
	362	/* Disable Ethernet TENA on Port B
	363	* Necessary because of pull up in COM3 port.
	364	*
	365	* This is just a preliminary fix, intended to turn off TENA
	366	* as soon as possible to avoid noise on the network. Once
	367