[J-u-boot.git] / include / configs / corvus.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Common board functions for siemens AT91SAM9G45 based boards
 * (C) Copyright 2013 Siemens AG
 *
 * Based on:
 * U-Boot file: include/configs/at91sam9m10g45ek.h
 * (C) Copyright 2007-2008
 * Stelian Pop <[email protected]>
 * Lead Tech Design <www.leadtechdesign.com>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/hardware.h>
#include <linux/sizes.h>

/*
 * Warning: changing CONFIG_SYS_TEXT_BASE requires
 * adapting the initial boot program.
 * Since the linker has to swallow that define, we must use a pure
 * hex number here!
 */

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */

/* serial console */
#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
#define CONFIG_USART_ID			ATMEL_ID_SYS

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
#define CONFIG_SYS_SDRAM_SIZE		0x08000000

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
#endif

/* DFU class support */
#define DFU_MANIFEST_POLL_TIMEOUT	25000

/* bootstrap + u-boot + env in nandflash */

/* Defines for SPL */
#define CONFIG_SPL_STACK		(SZ_16K)

#define CONFIG_SPL_BSS_START_ADDR	CONFIG_SPL_MAX_SIZE

#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_NAND_ECCSIZE		256
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
					  48, 49, 50, 51, 52, 53, 54, 55, \
					  56, 57, 58, 59, 60, 61, 62, 63, }

#define CONFIG_SYS_MASTER_CLOCK		132096000
#define AT91_PLL_LOCK_TIMEOUT		1000000
#define CONFIG_SYS_AT91_PLLA		0x20c73f03
#define CONFIG_SYS_MCKR			0x1301
#define CONFIG_SYS_MCKR_CSS		0x1302

#define CONFIG_SYS_SPL_LEN		CONFIG_SPL_PAD_TO

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
b89ac72a HS	2	/*
	3	* Common board functions for siemens AT91SAM9G45 based boards
	4	* (C) Copyright 2013 Siemens AG
	5	*
	6	* Based on:
	7	* U-Boot file: include/configs/at91sam9m10g45ek.h
	8	* (C) Copyright 2007-2008
	9	* Stelian Pop <[email protected]>
	10	* Lead Tech Design <www.leadtechdesign.com>
b89ac72a HS	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
	16	#include <asm/hardware.h>
fd45a0d1	17	#include <linux/sizes.h>
b89ac72a	18
b89ac72a HS	19	/*
	20	* Warning: changing CONFIG_SYS_TEXT_BASE requires
	21	* adapting the initial boot program.
	22	* Since the linker has to swallow that define, we must use a pure
	23	* hex number here!
	24	*/
	25
b89ac72a HS	26	/* ARM asynchronous clock */
	27	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
	28	#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
b89ac72a	29
b89ac72a	30	/* serial console */
b89ac72a HS	31	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
	32	#define CONFIG_USART_ID ATMEL_ID_SYS
	33
b89ac72a	34	/* SDRAM */
b89ac72a HS	35	#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
	36	#define CONFIG_SYS_SDRAM_SIZE 0x08000000
	37
b89ac72a HS	38	/* NAND flash */
b89ac72a HS	39	#ifdef CONFIG_CMD_NAND
b89ac72a HS	40	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	41	#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
	42	#define CONFIG_SYS_NAND_DBW_8
	43	/* our ALE is AD21 */
	44	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	45	/* our CLE is AD22 */
	46	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
	47	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
a5f8ccae	48	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
b89ac72a HS	49	#endif
b89ac72a HS	50
e11793bc	51	/* DFU class support */
e11793bc HS	52	#define DFU_MANIFEST_POLL_TIMEOUT 25000
e11793bc HS	53
b89ac72a	54	/* bootstrap + u-boot + env in nandflash */
b89ac72a	55
5b15fd98	56	/* Defines for SPL */
fd45a0d1	57	#define CONFIG_SPL_STACK (SZ_16K)
5b15fd98 HS	58
5b15fd98 HS	59	#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
5b15fd98	60
5b15fd98 HS	61	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
	62	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	63	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
5b15fd98	64
5b15fd98 HS	65	#define CONFIG_SYS_NAND_ECCSIZE 256
5b15fd98 HS	66	#define CONFIG_SYS_NAND_ECCBYTES 3
5b15fd98 HS	67	#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
	68	48, 49, 50, 51, 52, 53, 54, 55, \
	69	56, 57, 58, 59, 60, 61, 62, 63, }
	70
5b15fd98 HS	71	#define CONFIG_SYS_MASTER_CLOCK 132096000
	72	#define AT91_PLL_LOCK_TIMEOUT 1000000
	73	#define CONFIG_SYS_AT91_PLLA 0x20c73f03
	74	#define CONFIG_SYS_MCKR 0x1301
	75	#define CONFIG_SYS_MCKR_CSS 0x1302
	76
fc89afba SR	77	#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
fc89afba SR	78
b89ac72a	79	#endif