[J-u-boot.git] / include / i2c.h

/*
 * Copyright (C) 2009 Sergey Kubushyn <[email protected]>
 * Copyright (C) 2009 - 2013 Heiko Schocher <[email protected]>
 * Changes for multibus/multiadapter I2C support.
 *
 * (C) Copyright 2001
 * Gerald Van Baren, Custom IDEAS, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * The original I2C interface was
 *   (C) 2000 by Paolo Scaffardi ([email protected])
 *   AIRVENT SAM s.p.a - RIMINI(ITALY)
 * but has been changed substantially.
 */

#ifndef _I2C_H_
#define _I2C_H_

/*
 * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
 *
 * The implementation MUST NOT use static or global variables if the
 * I2C routines are used to read SDRAM configuration information
 * because this is done before the memories are initialized. Limited
 * use of stack-based variables are OK (the initial stack size is
 * limited).
 *
 * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
 */

/*
 * Configuration items.
 */
#define I2C_RXTX_LEN	128	/* maximum tx/rx buffer length */

#if !defined(CONFIG_SYS_I2C_MAX_HOPS)
/* no muxes used bus = i2c adapters */
#define CONFIG_SYS_I2C_DIRECT_BUS	1
#define CONFIG_SYS_I2C_MAX_HOPS		0
#define CONFIG_SYS_NUM_I2C_BUSES	ll_entry_count(struct i2c_adapter, i2c)
#else
/* we use i2c muxes */
#undef CONFIG_SYS_I2C_DIRECT_BUS
#endif

/* define the I2C bus number for RTC and DTT if not already done */
#if !defined(CONFIG_SYS_RTC_BUS_NUM)
#define CONFIG_SYS_RTC_BUS_NUM		0
#endif
#if !defined(CONFIG_SYS_DTT_BUS_NUM)
#define CONFIG_SYS_DTT_BUS_NUM		0
#endif
#if !defined(CONFIG_SYS_SPD_BUS_NUM)
#define CONFIG_SYS_SPD_BUS_NUM		0
#endif

struct i2c_adapter {
	void		(*init)(struct i2c_adapter *adap, int speed,
				int slaveaddr);
	int		(*probe)(struct i2c_adapter *adap, uint8_t chip);
	int		(*read)(struct i2c_adapter *adap, uint8_t chip,
				uint addr, int alen, uint8_t *buffer,
				int len);
	int		(*write)(struct i2c_adapter *adap, uint8_t chip,
				uint addr, int alen, uint8_t *buffer,
				int len);
	uint		(*set_bus_speed)(struct i2c_adapter *adap,
				uint speed);
	int		speed;
	int		slaveaddr;
	int		init_done;
	int		hwadapnr;
	char		*name;
};

#define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
		_set_speed, _speed, _slaveaddr, _hwadapnr, _name) \
	{ \
		.init		=	_init, \
		.probe		=	_probe, \
		.read		=	_read, \
		.write		=	_write, \
		.set_bus_speed	=	_set_speed, \
		.speed		=	_speed, \
		.slaveaddr	=	_slaveaddr, \
		.init_done	=	0, \
		.hwadapnr	=	_hwadapnr, \
		.name		=	#_name \
};

#define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \
			_set_speed, _speed, _slaveaddr, _hwadapnr) \
	ll_entry_declare(struct i2c_adapter, _name, i2c) = \
	U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
		 _set_speed, _speed, _slaveaddr, _hwadapnr, _name);

struct i2c_adapter *i2c_get_adapter(int index);

#ifndef CONFIG_SYS_I2C_DIRECT_BUS
struct i2c_mux {
	int	id;
	char	name[16];
};

struct i2c_next_hop {
	struct i2c_mux		mux;
	uint8_t		chip;
	uint8_t		channel;
};

struct i2c_bus_hose {
	int	adapter;
	struct i2c_next_hop	next_hop[CONFIG_SYS_I2C_MAX_HOPS];
};
#define I2C_NULL_HOP	{{-1, ""}, 0, 0}
extern struct i2c_bus_hose	i2c_bus[];

#define I2C_ADAPTER(bus)	i2c_bus[bus].adapter
#else
#define I2C_ADAPTER(bus)	bus
#endif
#define	I2C_BUS			gd->cur_i2c_bus

#define	I2C_ADAP_NR(bus)	i2c_get_adapter(I2C_ADAPTER(bus))
#define	I2C_ADAP		I2C_ADAP_NR(gd->cur_i2c_bus)
#define I2C_ADAP_HWNR		(I2C_ADAP->hwadapnr)

#ifndef CONFIG_SYS_I2C_DIRECT_BUS
#define I2C_MUX_PCA9540_ID	1
#define I2C_MUX_PCA9540		{I2C_MUX_PCA9540_ID, "PCA9540B"}
#define I2C_MUX_PCA9542_ID	2
#define I2C_MUX_PCA9542		{I2C_MUX_PCA9542_ID, "PCA9542A"}
#define I2C_MUX_PCA9544_ID	3
#define I2C_MUX_PCA9544		{I2C_MUX_PCA9544_ID, "PCA9544A"}
#define I2C_MUX_PCA9547_ID	4
#define I2C_MUX_PCA9547		{I2C_MUX_PCA9547_ID, "PCA9547A"}
#endif

#ifndef I2C_SOFT_DECLARATIONS
# if defined(CONFIG_MPC8260)
#  define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
# elif defined(CONFIG_8xx)
#  define I2C_SOFT_DECLARATIONS	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;

# elif (defined(CONFIG_AT91RM9200) || \
	defined(CONFIG_AT91SAM9260) ||  defined(CONFIG_AT91SAM9261) || \
	defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY)
#  define I2C_SOFT_DECLARATIONS	at91_pio_t *pio	= (at91_pio_t *) ATMEL_BASE_PIOA;
# else
#  define I2C_SOFT_DECLARATIONS
# endif
#endif

#ifdef CONFIG_8xx
/* Set default value for the I2C bus speed on 8xx. In the
 * future, we'll define these in all 8xx board config files.
 */
#ifndef	CONFIG_SYS_I2C_SPEED
#define	CONFIG_SYS_I2C_SPEED	50000
#endif
#endif

/*
 * Many boards/controllers/drivers don't support an I2C slave interface so
 * provide a default slave address for them for use in common code.  A real
 * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
 * support a slave interface.
 */
#ifndef	CONFIG_SYS_I2C_SLAVE
#define	CONFIG_SYS_I2C_SLAVE	0xfe
#endif

/*
 * Initialization, must be called once on start up, may be called
 * repeatedly to change the speed and slave addresses.
 */
void i2c_init(int speed, int slaveaddr);
void i2c_init_board(void);
#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
void i2c_board_late_init(void);
#endif

#if defined(CONFIG_I2C_MUX)

typedef struct _mux {
	uchar	chip;
	uchar	channel;
	char	*name;
	struct _mux	*next;
} I2C_MUX;

typedef struct _mux_device {
	int	busid;
	I2C_MUX	*mux;	/* List of muxes, to reach the device */
	struct _mux_device	*next;
} I2C_MUX_DEVICE;

I2C_MUX_DEVICE	*i2c_mux_search_device(int id);
I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
int i2x_mux_select_mux(int bus);
int i2c_mux_ident_muxstring_f (uchar *buf);
#endif

#ifdef CONFIG_SYS_I2C
/*
 * i2c_get_bus_num:
 *
 *  Returns index of currently active I2C bus.  Zero-based.
 */
unsigned int i2c_get_bus_num(void);

/*
 * i2c_set_bus_num:
 *
 *  Change the active I2C bus.  Subsequent read/write calls will
 *  go to this one.
 *
 *	bus - bus index, zero based
 *
 *	Returns: 0 on success, not 0 on failure
 *
 */
int i2c_set_bus_num(unsigned int bus);

/*
 * i2c_init_all():
 *
 * Initializes all I2C adapters in the system. All i2c_adap structures must
 * be initialized beforehead with function pointers and data, including
 * speed and slaveaddr. Returns 0 on success, non-0 on failure.
 */
void i2c_init_all(void);

/*
 * Probe the given I2C chip address.  Returns 0 if a chip responded,
 * not 0 on failure.
 */
int i2c_probe(uint8_t chip);

/*
 * Read/Write interface:
 *   chip:    I2C chip address, range 0..127
 *   addr:    Memory (register) address within the chip
 *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
 *              memories, 0 for register type devices with only one
 *              register)
 *   buffer:  Where to read/write the data
 *   len:     How many bytes to read/write
 *
 *   Returns: 0 on success, not 0 on failure
 */
int i2c_read(uint8_t chip, unsigned int addr, int alen,
				uint8_t *buffer, int len);

int i2c_write(uint8_t chip, unsigned int addr, int alen,
				uint8_t *buffer, int len);

/*
 * Utility routines to read/write registers.
 */
uint8_t i2c_reg_read(uint8_t addr, uint8_t reg);

void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val);

/*
 * i2c_set_bus_speed:
 *
 *  Change the speed of the active I2C bus
 *
 *	speed - bus speed in Hz
 *
 *	Returns: new bus speed
 *
 */
unsigned int i2c_set_bus_speed(unsigned int speed);

/*
 * i2c_get_bus_speed:
 *
 *  Returns speed of currently active I2C bus in Hz
 */

unsigned int i2c_get_bus_speed(void);

/*
 * i2c_reloc_fixup:
 *
 * Adjusts I2C pointers after U-Boot is relocated to DRAM
 */
void i2c_reloc_fixup(void);
#if defined(CONFIG_SYS_I2C_SOFT)
void i2c_soft_init(void);
void i2c_soft_active(void);
void i2c_soft_tristate(void);
int i2c_soft_read(void);
void i2c_soft_sda(int bit);
void i2c_soft_scl(int bit);
void i2c_soft_delay(void);
#endif
#else

/*
 * Probe the given I2C chip address.  Returns 0 if a chip responded,
 * not 0 on failure.
 */
int i2c_probe(uchar chip);

/*
 * Read/Write interface:
 *   chip:    I2C chip address, range 0..127
 *   addr:    Memory (register) address within the chip
 *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
 *              memories, 0 for register type devices with only one
 *              register)
 *   buffer:  Where to read/write the data
 *   len:     How many bytes to read/write
 *
 *   Returns: 0 on success, not 0 on failure
 */
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);

/*
 * Utility routines to read/write registers.
 */
static inline u8 i2c_reg_read(u8 addr, u8 reg)
{
	u8 buf;

#ifdef CONFIG_8xx
	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif

#ifdef DEBUG
	printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg);
#endif

	i2c_read(addr, reg, 1, &buf, 1);

	return buf;
}

static inline void i2c_reg_write(u8 addr, u8 reg, u8 val)
{
#ifdef CONFIG_8xx
	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif

#ifdef DEBUG
	printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n",
	       __func__, addr, reg, val);
#endif

	i2c_write(addr, reg, 1, &val, 1);
}

/*
 * Functions for setting the current I2C bus and its speed
 */

/*
 * i2c_set_bus_num:
 *
 *  Change the active I2C bus.  Subsequent read/write calls will
 *  go to this one.
 *
 *	bus - bus index, zero based
 *
 *	Returns: 0 on success, not 0 on failure
 *
 */
int i2c_set_bus_num(unsigned int bus);

/*
 * i2c_get_bus_num:
 *
 *  Returns index of currently active I2C bus.  Zero-based.
 */

unsigned int i2c_get_bus_num(void);

/*
 * i2c_set_bus_speed:
 *
 *  Change the speed of the active I2C bus
 *
 *	speed - bus speed in Hz
 *
 *	Returns: 0 on success, not 0 on failure
 *
 */
int i2c_set_bus_speed(unsigned int);

/*
 * i2c_get_bus_speed:
 *
 *  Returns speed of currently active I2C bus in Hz
 */

unsigned int i2c_get_bus_speed(void);
#endif /* CONFIG_SYS_I2C */

/*
 * only for backwardcompatibility, should go away if we switched
 * completely to new multibus support.
 */
#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
# if !defined(CONFIG_SYS_MAX_I2C_BUS)
#  define CONFIG_SYS_MAX_I2C_BUS		2
# endif
# define I2C_MULTI_BUS				0
#else
# define CONFIG_SYS_MAX_I2C_BUS		1
# define I2C_MULTI_BUS				0
#endif

/* NOTE: These two functions MUST be always_inline to avoid code growth! */
static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
static inline unsigned int I2C_GET_BUS(void)
{
	return I2C_MULTI_BUS ? i2c_get_bus_num() : 0;
}

static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline));
static inline void I2C_SET_BUS(unsigned int bus)
{
	if (I2C_MULTI_BUS)
		i2c_set_bus_num(bus);
}

/* Multi I2C definitions */
enum {
	I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7,
	I2C_8, I2C_9, I2C_10,
};

/* Multi I2C busses handling */
#ifdef CONFIG_SOFT_I2C_MULTI_BUS
extern int get_multi_scl_pin(void);
extern int get_multi_sda_pin(void);
extern int multi_i2c_init(void);
#endif

/**
 * Get FDT values for i2c bus.
 *
 * @param blob  Device tree blbo
 * @return the number of I2C bus
 */
void board_i2c_init(const void *blob);

/**
 * Find the I2C bus number by given a FDT I2C node.
 *
 * @param blob  Device tree blbo
 * @param node  FDT I2C node to find
 * @return the number of I2C bus (zero based), or -1 on error
 */
int i2c_get_bus_num_fdt(int node);

/**
 * Reset the I2C bus represented by the given a FDT I2C node.
 *
 * @param blob  Device tree blbo
 * @param node  FDT I2C node to find
 * @return 0 if port was reset, -1 if not found
 */
int i2c_reset_port_fdt(const void *blob, int node);
#endif	/* _I2C_H_ */
Commit	Line	Data
1f045217	1	/*
385c9ef5 HS	2	* Copyright (C) 2009 Sergey Kubushyn <[email protected]>
	3	* Copyright (C) 2009 - 2013 Heiko Schocher <[email protected]>
	4	* Changes for multibus/multiadapter I2C support.
	5	*
1f045217 WD	6	* (C) Copyright 2001
	7	* Gerald Van Baren, Custom IDEAS, [email protected].
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*
	27	* The original I2C interface was
	28	* (C) 2000 by Paolo Scaffardi ([email protected])
	29	* AIRVENT SAM s.p.a - RIMINI(ITALY)
	30	* but has been changed substantially.
	31	*/
	32
	33	#ifndef _I2C_H_
	34	#define _I2C_H_
	35
	36	/*
	37	* WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
	38	*
	39	* The implementation MUST NOT use static or global variables if the
	40	* I2C routines are used to read SDRAM configuration information
	41	* because this is done before the memories are initialized. Limited
	42	* use of stack-based variables are OK (the initial stack size is
	43	* limited).
	44	*
	45	* WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
	46	*/
	47
	48	/*
	49	* Configuration items.
	50	*/
	51	#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
	52
385c9ef5 HS	53	#if !defined(CONFIG_SYS_I2C_MAX_HOPS)
	54	/* no muxes used bus = i2c adapters */
	55	#define CONFIG_SYS_I2C_DIRECT_BUS 1
	56	#define CONFIG_SYS_I2C_MAX_HOPS 0
	57	#define CONFIG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c)
79b2d0bb	58	#else
385c9ef5 HS	59	/* we use i2c muxes */
385c9ef5 HS	60	#undef CONFIG_SYS_I2C_DIRECT_BUS
79b2d0bb SR	61	#endif
79b2d0bb SR	62
8c12045a	63	/* define the I2C bus number for RTC and DTT if not already done */
6d0f6bcf JCPV	64	#if !defined(CONFIG_SYS_RTC_BUS_NUM)
6d0f6bcf JCPV	65	#define CONFIG_SYS_RTC_BUS_NUM 0
8c12045a	66	#endif
6d0f6bcf JCPV	67	#if !defined(CONFIG_SYS_DTT_BUS_NUM)
6d0f6bcf JCPV	68	#define CONFIG_SYS_DTT_BUS_NUM 0
8c12045a	69	#endif
6d0f6bcf JCPV	70	#if !defined(CONFIG_SYS_SPD_BUS_NUM)
6d0f6bcf JCPV	71	#define CONFIG_SYS_SPD_BUS_NUM 0
d8a8ea5c	72	#endif
8c12045a	73
385c9ef5 HS	74	struct i2c_adapter {
	75	void (init)(struct i2c_adapter adap, int speed,
	76	int slaveaddr);
	77	int (probe)(struct i2c_adapter adap, uint8_t chip);
	78	int (read)(struct i2c_adapter adap, uint8_t chip,
	79	uint addr, int alen, uint8_t *buffer,
	80	int len);
	81	int (write)(struct i2c_adapter adap, uint8_t chip,
	82	uint addr, int alen, uint8_t *buffer,
	83	int len);
	84	uint (set_bus_speed)(struct i2c_adapter adap,
	85	uint speed);
	86	int speed;
	87	int slaveaddr;
	88	int init_done;
	89	int hwadapnr;
	90	char *name;
	91	};
	92
	93	#define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
	94	_set_speed, _speed, _slaveaddr, _hwadapnr, _name) \
	95	{ \
	96	.init = _init, \
	97	.probe = _probe, \
	98	.read = _read, \
	99	.write = _write, \
	100	.set_bus_speed = _set_speed, \
	101	.speed = _speed, \
	102	.slaveaddr = _slaveaddr, \
	103	.init_done = 0, \
	104	.hwadapnr = _hwadapnr, \
	105	.name = #_name \
	106	};
	107
	108	#define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \
	109	_set_speed, _speed, _slaveaddr, _hwadapnr) \
	110	ll_entry_declare(struct i2c_adapter, _name, i2c) = \
	111	U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
	112	_set_speed, _speed, _slaveaddr, _hwadapnr, _name);
	113
	114	struct i2c_adapter *i2c_get_adapter(int index);
	115
	116	#ifndef CONFIG_SYS_I2C_DIRECT_BUS
	117	struct i2c_mux {
	118	int id;
	119	char name[16];
	120	};
	121
	122	struct i2c_next_hop {
	123	struct i2c_mux mux;
	124	uint8_t chip;
	125	uint8_t channel;
	126	};
	127
	128	struct i2c_bus_hose {
	129	int adapter;
	130	struct i2c_next_hop next_hop[CONFIG_SYS_I2C_MAX_HOPS];
	131	};
	132	#define I2C_NULL_HOP {{-1, ""}, 0, 0}
	133	extern struct i2c_bus_hose i2c_bus[];
	134
	135	#define I2C_ADAPTER(bus) i2c_bus[bus].adapter
	136	#else
	137	#define I2C_ADAPTER(bus) bus
138	#endif
139	#define I2C_BUS gd->cur_i2c_bus
140
141	#define I2C_ADAP_NR(bus) i2c_get_adapter(I2C_ADAPTER(bus))
142	#define I2C_ADAP I2C_ADAP_NR(gd->cur_i2c_bus)
143	#define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr)
144
145	#ifndef CONFIG_SYS_I2C_DIRECT_BUS
146	#define I2C_MUX_PCA9540_ID 1
147	#define I2C_MUX_PCA9540 {I2C_MUX_PCA9540_ID, "PCA9540B"}
148	#define I2C_MUX_PCA9542_ID 2
149	#define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"}
150	#define I2C_MUX_PCA9544_ID 3
151	#define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"}
152	#define I2C_MUX_PCA9547_ID 4
153	#define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"}
154	#endif
155
98aed379 HS	156	#ifndef I2C_SOFT_DECLARATIONS
98aed379 HS	157	# if defined(CONFIG_MPC8260)
6d0f6bcf	158	# define I2C_SOFT_DECLARATIONS volatile ioport_t iop = ioport_addr((immap_t )CONFIG_SYS_IMMR, I2C_PORT);
98aed379	159	# elif defined(CONFIG_8xx)
6d0f6bcf	160	# define I2C_SOFT_DECLARATIONS volatile immap_t immr = (immap_t )CONFIG_SYS_IMMR;
0cf0b931 JS	161
	162	# elif (defined(CONFIG_AT91RM9200) \|\| \
	163	defined(CONFIG_AT91SAM9260) \|\| defined(CONFIG_AT91SAM9261) \|\| \
	164	defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY)
78132275	165	# define I2C_SOFT_DECLARATIONS at91_pio_t pio = (at91_pio_t ) ATMEL_BASE_PIOA;
98aed379 HS	166	# else
	167	# define I2C_SOFT_DECLARATIONS
	168	# endif
	169	#endif
ecf5f077 TT	170
ecf5f077 TT	171	#ifdef CONFIG_8xx
9c90a2c8	172	/* Set default value for the I2C bus speed on 8xx. In the
ecf5f077 TT	173	* future, we'll define these in all 8xx board config files.
	174	*/
	175	#ifndef CONFIG_SYS_I2C_SPEED
	176	#define CONFIG_SYS_I2C_SPEED 50000
	177	#endif
9c90a2c8	178	#endif
ecf5f077	179
9c90a2c8 PT	180	/*
	181	* Many boards/controllers/drivers don't support an I2C slave interface so
	182	* provide a default slave address for them for use in common code. A real
	183	* value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
	184	* support a slave interface.
	185	*/
ecf5f077	186	#ifndef CONFIG_SYS_I2C_SLAVE
9c90a2c8	187	#define CONFIG_SYS_I2C_SLAVE 0xfe
ecf5f077 TT	188	#endif
ecf5f077 TT	189
1f045217 WD	190	/*
	191	* Initialization, must be called once on start up, may be called
	192	* repeatedly to change the speed and slave addresses.
	193	*/
	194	void i2c_init(int speed, int slaveaddr);
06d01dbe	195	void i2c_init_board(void);
26a33504 RR	196	#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
	197	void i2c_board_late_init(void);
	198	#endif
1f045217	199
67b23a32 HS	200	#if defined(CONFIG_I2C_MUX)
	201
	202	typedef struct _mux {
	203	uchar chip;
	204	uchar channel;
	205	char *name;
	206	struct _mux *next;
	207	} I2C_MUX;
	208
	209	typedef struct _mux_device {
	210	int busid;
	211	I2C_MUX mux; / List of muxes, to reach the device */
	212	struct _mux_device *next;
	213	} I2C_MUX_DEVICE;
	214
67b23a32 HS	215	I2C_MUX_DEVICE *i2c_mux_search_device(int id);
	216	I2C_MUX_DEVICE i2c_mux_ident_muxstring (uchar buf);
	217	int i2x_mux_select_mux(int bus);
	218	int i2c_mux_ident_muxstring_f (uchar *buf);
	219	#endif
	220
385c9ef5	221	#ifdef CONFIG_SYS_I2C
385c9ef5 HS	222	/*
	223	* i2c_get_bus_num:
	224	*
	225	* Returns index of currently active I2C bus. Zero-based.
	226	*/
	227	unsigned int i2c_get_bus_num(void);
	228
	229	/*
	230	* i2c_set_bus_num:
	231	*
	232	* Change the active I2C bus. Subsequent read/write calls will
	233	* go to this one.
	234	*
	235	* bus - bus index, zero based
	236	*
	237	* Returns: 0 on success, not 0 on failure
	238	*
	239	*/
	240	int i2c_set_bus_num(unsigned int bus);
	241
	242	/*
	243	* i2c_init_all():
	244	*
	245	* Initializes all I2C adapters in the system. All i2c_adap structures must
	246	* be initialized beforehead with function pointers and data, including
	247	* speed and slaveaddr. Returns 0 on success, non-0 on failure.
	248	*/
	249	void i2c_init_all(void);
	250
	251	/*
	252	* Probe the given I2C chip address. Returns 0 if a chip responded,
	253	* not 0 on failure.
	254	*/
	255	int i2c_probe(uint8_t chip);
	256
	257	/*
	258	* Read/Write interface:
	259	* chip: I2C chip address, range 0..127
	260	* addr: Memory (register) address within the chip
	261	* alen: Number of bytes to use for addr (typically 1, 2 for larger
	262	* memories, 0 for register type devices with only one
	263	* register)
	264	* buffer: Where to read/write the data
	265	* len: How many bytes to read/write
	266	*
	267	* Returns: 0 on success, not 0 on failure
	268	*/
	269	int i2c_read(uint8_t chip, unsigned int addr, int alen,
	270	uint8_t *buffer, int len);
	271
	272	int i2c_write(uint8_t chip, unsigned int addr, int alen,
	273	uint8_t *buffer, int len);
	274
	275	/*
	276	* Utility routines to read/write registers.
	277	*/
	278	uint8_t i2c_reg_read(uint8_t addr, uint8_t reg);
	279
	280	void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val);
	281
	282	/*
	283	* i2c_set_bus_speed:
	284	*
	285	* Change the speed of the active I2C bus
286	*
287	* speed - bus speed in Hz
288	*
289	* Returns: new bus speed
290	*
291	*/
292	unsigned int i2c_set_bus_speed(unsigned int speed);
293
294	/*
295	* i2c_get_bus_speed:
296	*
297	* Returns speed of currently active I2C bus in Hz
298	*/
299
300	unsigned int i2c_get_bus_speed(void);
301
302	/*
303	* i2c_reloc_fixup:
304	*
305	* Adjusts I2C pointers after U-Boot is relocated to DRAM
306	*/
307	void i2c_reloc_fixup(void);
ea818dbb HS	308	#if defined(CONFIG_SYS_I2C_SOFT)
	309	void i2c_soft_init(void);
	310	void i2c_soft_active(void);
	311	void i2c_soft_tristate(void);
	312	int i2c_soft_read(void);
	313	void i2c_soft_sda(int bit);
	314	void i2c_soft_scl(int bit);
	315	void i2c_soft_delay(void);
	316	#endif
385c9ef5 HS	317	#else
385c9ef5 HS	318
1f045217 WD	319	/*
	320	* Probe the given I2C chip address. Returns 0 if a chip responded,
	321	* not 0 on failure.
	322	*/
	323	int i2c_probe(uchar chip);
	324
	325	/*
	326	* Read/Write interface:
	327	* chip: I2C chip address, range 0..127
	328	* addr: Memory (register) address within the chip
	329	* alen: Number of bytes to use for addr (typically 1, 2 for larger
	330	* memories, 0 for register type devices with only one
	331	* register)
	332	* buffer: Where to read/write the data
	333	* len: How many bytes to read/write
	334	*
	335	* Returns: 0 on success, not 0 on failure
	336	*/
	337	int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
	338	int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
	339
	340	/*
	341	* Utility routines to read/write registers.
	342	*/
ecf5f077 TT	343	static inline u8 i2c_reg_read(u8 addr, u8 reg)
	344	{
	345	u8 buf;
	346
	347	#ifdef CONFIG_8xx
	348	/* MPC8xx needs this. Maybe one day we can get rid of it. */
	349	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	350	#endif
	351
	352	#ifdef DEBUG
	353	printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg);
	354	#endif
	355
ecf5f077	356	i2c_read(addr, reg, 1, &buf, 1);
ecf5f077 TT	357
	358	return buf;
	359	}
	360
	361	static inline void i2c_reg_write(u8 addr, u8 reg, u8 val)
	362	{
	363	#ifdef CONFIG_8xx
	364	/* MPC8xx needs this. Maybe one day we can get rid of it. */
	365	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	366	#endif
	367
	368	#ifdef DEBUG
	369	printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n",
	370	__func__, addr, reg, val);
	371	#endif
	372
ecf5f077	373	i2c_write(addr, reg, 1, &val, 1);
ecf5f077	374	}
1f045217	375
bb99ad6d BW	376	/*
	377	* Functions for setting the current I2C bus and its speed
	378	*/
	379
	380	/*
	381	* i2c_set_bus_num:
	382	*
	383	* Change the active I2C bus. Subsequent read/write calls will
	384	* go to this one.
	385	*
53677ef1	386	* bus - bus index, zero based
bb99ad6d	387	*
53677ef1	388	* Returns: 0 on success, not 0 on failure
bb99ad6d BW	389	*
bb99ad6d BW	390	*/
9ca880a2	391	int i2c_set_bus_num(unsigned int bus);
bb99ad6d BW	392
	393	/*
	394	* i2c_get_bus_num:
	395	*
	396	* Returns index of currently active I2C bus. Zero-based.
	397	*/
	398
9ca880a2	399	unsigned int i2c_get_bus_num(void);
bb99ad6d BW	400
	401	/*
	402	* i2c_set_bus_speed:
	403	*
	404	* Change the speed of the active I2C bus
	405	*
53677ef1	406	* speed - bus speed in Hz
bb99ad6d	407	*
53677ef1	408	* Returns: 0 on success, not 0 on failure
bb99ad6d BW	409	*
bb99ad6d BW	410	*/
9ca880a2	411	int i2c_set_bus_speed(unsigned int);
bb99ad6d BW	412
	413	/*
	414	* i2c_get_bus_speed:
	415	*
	416	* Returns speed of currently active I2C bus in Hz
	417	*/
	418
9ca880a2	419	unsigned int i2c_get_bus_speed(void);
385c9ef5 HS	420	#endif /* CONFIG_SYS_I2C */
	421
	422	/*
	423	* only for backwardcompatibility, should go away if we switched
	424	* completely to new multibus support.
	425	*/
	426	#if defined(CONFIG_SYS_I2C) \|\| defined(CONFIG_I2C_MULTI_BUS)
	427	# if !defined(CONFIG_SYS_MAX_I2C_BUS)
	428	# define CONFIG_SYS_MAX_I2C_BUS 2
	429	# endif
	430	# define I2C_MULTI_BUS 0
	431	#else
	432	# define CONFIG_SYS_MAX_I2C_BUS 1
	433	# define I2C_MULTI_BUS 0
	434	#endif
bb99ad6d	435
cd7b4e82 MV	436	/* NOTE: These two functions MUST be always_inline to avoid code growth! */
	437	static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
	438	static inline unsigned int I2C_GET_BUS(void)
	439	{
	440	return I2C_MULTI_BUS ? i2c_get_bus_num() : 0;
	441	}
	442
	443	static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline));
	444	static inline void I2C_SET_BUS(unsigned int bus)
	445	{
	446	if (I2C_MULTI_BUS)
	447	i2c_set_bus_num(bus);
	448	}
	449
7ca8f73a ŁM	450	/* Multi I2C definitions */
	451	enum {
	452	I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7,
	453	I2C_8, I2C_9, I2C_10,
	454	};
	455
	456	/* Multi I2C busses handling */
	457	#ifdef CONFIG_SOFT_I2C_MULTI_BUS
	458	extern int get_multi_scl_pin(void);
	459	extern int get_multi_sda_pin(void);
	460	extern int multi_i2c_init(void);
	461	#endif
a9d2ae70 RS	462
	463	/**
	464	* Get FDT values for i2c bus.
	465	*
	466	* @param blob Device tree blbo
	467	* @return the number of I2C bus
	468	*/
	469	void board_i2c_init(const void *blob);
	470
	471	/**
	472	* Find the I2C bus number by given a FDT I2C node.
	473	*
	474	* @param blob Device tree blbo
	475	* @param node FDT I2C node to find
	476	* @return the number of I2C bus (zero based), or -1 on error
	477	*/
	478	int i2c_get_bus_num_fdt(int node);
	479
	480	/**
	481	* Reset the I2C bus represented by the given a FDT I2C node.
	482	*
	483	* @param blob Device tree blbo
	484	* @param node FDT I2C node to find
	485	* @return 0 if port was reset, -1 if not found
	486	*/
	487	int i2c_reset_port_fdt(const void *blob, int node);
1f045217	488	#endif /* _I2C_H_ */