projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| e2b65ea9 | 2 | /* |
| 34f39ce8 | 3 | * Copyright 2017, 2019-2021 NXP |
| e2b65ea9 | 4 | * Copyright 2015 Freescale Semiconductor |
| e2b65ea9 YS |
5 | */ |
| 6 | ||
| 7 | #ifndef __LS2_RDB_H | |
| 8 | #define __LS2_RDB_H | |
| 9 | ||
| 44937214 | 10 | #include "ls2080a_common.h" |
| e2b65ea9 | 11 | |
| 89a168f7 | 12 | #ifdef CONFIG_FSL_QSPI |
| 3049a583 PJ |
13 | #ifdef CONFIG_TARGET_LS2081ARDB |
| 14 | #define CONFIG_QIXIS_I2C_ACCESS | |
| 15 | #endif | |
| 2147a169 | 16 | #if !CONFIG_IS_ENABLED(DM_I2C) |
| 89a168f7 | 17 | #define CONFIG_SYS_I2C_EARLY_INIT |
| 89a168f7 | 18 | #endif |
| 654e4e70 | 19 | #endif |
| 89a168f7 | 20 | |
| ed2530d0 RH |
21 | #define I2C_MUX_CH_VOL_MONITOR 0xa |
| 22 | #define I2C_VOL_MONITOR_ADDR 0x38 | |
| 23 | #define CONFIG_VOL_MONITOR_IR36021_READ | |
| 24 | #define CONFIG_VOL_MONITOR_IR36021_SET | |
| 25 | ||
| 26 | #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv" | |
| 27 | #ifndef CONFIG_SPL_BUILD | |
| 28 | #define CONFIG_VID | |
| 29 | #endif | |
| 30 | /* step the IR regulator in 5mV increments */ | |
| 31 | #define IR_VDD_STEP_DOWN 5 | |
| 32 | #define IR_VDD_STEP_UP 5 | |
| 33 | /* The lowest and highest voltage allowed for LS2080ARDB */ | |
| 34 | #define VDD_MV_MIN 819 | |
| 35 | #define VDD_MV_MAX 1212 | |
| 36 | ||
| e2b65ea9 YS |
37 | #ifndef __ASSEMBLY__ |
| 38 | unsigned long get_board_sys_clk(void); | |
| 39 | #endif | |
| 40 | ||
| 41 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() | |
| 42 | #define CONFIG_DDR_CLK_FREQ 133333333 | |
| 43 | #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) | |
| 44 | ||
| 45 | #define CONFIG_DDR_SPD | |
| 46 | #define CONFIG_DDR_ECC | |
| 47 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 48 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 49 | #define SPD_EEPROM_ADDRESS1 0x51 | |
| 50 | #define SPD_EEPROM_ADDRESS2 0x52 | |
| fc7b3855 YS |
51 | #define SPD_EEPROM_ADDRESS3 0x53 |
| 52 | #define SPD_EEPROM_ADDRESS4 0x54 | |
| e2b65ea9 YS |
53 | #define SPD_EEPROM_ADDRESS5 0x55 |
| 54 | #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ | |
| 55 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 | |
| 56 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ | |
| 57 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
| 58 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
| 44937214 | 59 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
| e2b65ea9 | 60 | #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 |
| 44937214 | 61 | #endif |
| e2b65ea9 | 62 | |
| 989c5f0a | 63 | /* SATA */ |
| 989c5f0a | 64 | #define CONFIG_SCSI_AHCI_PLAT |
| 989c5f0a TY |
65 | |
| 66 | #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 | |
| 67 | #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 | |
| 68 | ||
| 69 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 | |
| 70 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
| 71 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
| 72 | CONFIG_SYS_SCSI_MAX_LUN) | |
| 9570df03 RB |
73 | |
| 74 | #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT) | |
| e2b65ea9 YS |
75 | |
| 76 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
| 77 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
| 78 | #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) | |
| 79 | ||
| 80 | #define CONFIG_SYS_NOR0_CSPR \ | |
| 81 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 82 | CSPR_PORT_SIZE_16 | \ | |
| 83 | CSPR_MSEL_NOR | \ | |
| 84 | CSPR_V) | |
| 85 | #define CONFIG_SYS_NOR0_CSPR_EARLY \ | |
| 86 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ | |
| 87 | CSPR_PORT_SIZE_16 | \ | |
| 88 | CSPR_MSEL_NOR | \ | |
| 89 | CSPR_V) | |
| 90 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) | |
| 91 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
| 92 | FTIM0_NOR_TEADC(0x5) | \ | |
| 93 | FTIM0_NOR_TEAHC(0x5)) | |
| 94 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
| 95 | FTIM1_NOR_TRAD_NOR(0x1a) |\ | |
| 96 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
| 97 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
| 98 | FTIM2_NOR_TCH(0x4) | \ | |
| 99 | FTIM2_NOR_TWPH(0x0E) | \ | |
| 100 | FTIM2_NOR_TWP(0x1c)) | |
| 101 | #define CONFIG_SYS_NOR_FTIM3 0x04000000 | |
| 102 | #define CONFIG_SYS_IFC_CCR 0x01000000 | |
| 103 | ||
| e856bdcf | 104 | #ifdef CONFIG_MTD_NOR_FLASH |
| e2b65ea9 YS |
105 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 106 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 107 | ||
| 108 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 109 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 110 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 111 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 112 | ||
| 113 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 114 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ | |
| 115 | CONFIG_SYS_FLASH_BASE + 0x40000000} | |
| 116 | #endif | |
| 117 | ||
| 118 | #define CONFIG_NAND_FSL_IFC | |
| 119 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 | |
| 120 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 | |
| 121 | ||
| e2b65ea9 YS |
122 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) |
| 123 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 124 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
| 125 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 126 | | CSPR_V) | |
| 127 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) | |
| 128 | ||
| 129 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 130 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 131 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 132 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
| 133 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
| 134 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | |
| 135 | | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ | |
| 136 | ||
| 137 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 138 | ||
| 139 | /* ONFI NAND Flash mode0 Timing Params */ | |
| 140 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ | |
| 141 | FTIM0_NAND_TWP(0x30) | \ | |
| 142 | FTIM0_NAND_TWCHT(0x0e) | \ | |
| 143 | FTIM0_NAND_TWH(0x14)) | |
| 144 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ | |
| 145 | FTIM1_NAND_TWBE(0xab) | \ | |
| 146 | FTIM1_NAND_TRR(0x1c) | \ | |
| 147 | FTIM1_NAND_TRP(0x30)) | |
| 148 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ | |
| 149 | FTIM2_NAND_TREH(0x14) | \ | |
| 150 | FTIM2_NAND_TWHRE(0x3c)) | |
| 151 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 152 | ||
| 153 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 154 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 155 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
| e2b65ea9 YS |
156 | |
| 157 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
| e2b65ea9 YS |
158 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ |
| 159 | #define QIXIS_LBMAP_SWITCH 0x06 | |
| 160 | #define QIXIS_LBMAP_MASK 0x0f | |
| 161 | #define QIXIS_LBMAP_SHIFT 0 | |
| 162 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 163 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
| 32eda7cc | 164 | #define QIXIS_LBMAP_NAND 0x09 |
| e2b65ea9 YS |
165 | #define QIXIS_RST_CTL_RESET 0x31 |
| 166 | #define QIXIS_RST_CTL_RESET_EN 0x30 | |
| 167 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
| 168 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 169 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 32eda7cc | 170 | #define QIXIS_RCW_SRC_NAND 0x119 |
| e2b65ea9 YS |
171 | #define QIXIS_RST_FORCE_MEM 0x01 |
| 172 | ||
| 173 | #define CONFIG_SYS_CSPR3_EXT (0x0) | |
| 174 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | |
| 175 | | CSPR_PORT_SIZE_8 \ | |
| 176 | | CSPR_MSEL_GPCM \ | |
| 177 | | CSPR_V) | |
| 178 | #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
| 179 | | CSPR_PORT_SIZE_8 \ | |
| 180 | | CSPR_MSEL_GPCM \ | |
| 181 | | CSPR_V) | |
| 182 | ||
| 183 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) | |
| 184 | #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) | |
| 185 | /* QIXIS Timing parameters for IFC CS3 */ | |
| 186 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 187 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 188 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 189 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
| 190 | FTIM1_GPCM_TRAD(0x3f)) | |
| 191 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
| 192 | FTIM2_GPCM_TCH(0xf) | \ | |
| 193 | FTIM2_GPCM_TWP(0x3E)) | |
| 194 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
| 195 | ||
| 88718be3 | 196 | #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND) |
| 32eda7cc SW |
197 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 198 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY | |
| 199 | #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR | |
| 200 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
| 201 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
| 202 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 203 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 204 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 205 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 206 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 207 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 208 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 209 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 210 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 211 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 212 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 213 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 214 | ||
| 32eda7cc SW |
215 | #define CONFIG_SPL_PAD_TO 0x80000 |
| 216 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) | |
| 217 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) | |
| 218 | #else | |
| e2b65ea9 YS |
219 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 220 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY | |
| 221 | #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR | |
| 222 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 223 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 224 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 225 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 226 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 227 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 228 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 229 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
| 230 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
| 231 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
| 232 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 233 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 234 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 235 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 9570df03 | 236 | #endif |
| 32eda7cc | 237 | |
| e2b65ea9 YS |
238 | /* Debug Server firmware */ |
| 239 | #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR | |
| 240 | #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL | |
| 89a168f7 | 241 | #endif |
| e2b65ea9 YS |
242 | #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 |
| 243 | ||
| 3049a583 PJ |
244 | #ifdef CONFIG_TARGET_LS2081ARDB |
| 245 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ | |
| 246 | #define QIXIS_QMAP_MASK 0x07 | |
| 247 | #define QIXIS_QMAP_SHIFT 5 | |
| 248 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 249 | #define QIXIS_LBMAP_QSPI 0x00 | |
| 250 | #define QIXIS_RCW_SRC_QSPI 0x62 | |
| 251 | #define QIXIS_LBMAP_ALTBANK 0x20 | |
| 252 | #define QIXIS_RST_CTL_RESET 0x31 | |
| 253 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
| 254 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 255 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 256 | #define QIXIS_LBMAP_MASK 0x0f | |
| 257 | #define QIXIS_RST_CTL_RESET_EN 0x30 | |
| 258 | #endif | |
| 259 | ||
| e2b65ea9 YS |
260 | /* |
| 261 | * I2C | |
| 262 | */ | |
| 3049a583 PJ |
263 | #ifdef CONFIG_TARGET_LS2081ARDB |
| 264 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
| 265 | #endif | |
| 4012350d PK |
266 | #define I2C_MUX_PCA_ADDR 0x75 |
| 267 | #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ | |
| e2b65ea9 YS |
268 | |
| 269 | /* I2C bus multiplexer */ | |
| 270 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| 271 | ||
| 0c42a8de | 272 | /* SPI */ |
| c93ad777 | 273 | #if defined(CONFIG_FSL_DSPI) |
| 21640db5 | 274 | #define CONFIG_SPI_FLASH_STMICRO |
| 0c42a8de HW |
275 | #endif |
| 276 | ||
| e2b65ea9 YS |
277 | /* |
| 278 | * RTC configuration | |
| 279 | */ | |
| 280 | #define RTC | |
| 3049a583 | 281 | #ifdef CONFIG_TARGET_LS2081ARDB |
| 3049a583 PJ |
282 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
| 283 | #else | |
| e2b65ea9 YS |
284 | #define CONFIG_RTC_DS3231 1 |
| 285 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 3049a583 | 286 | #endif |
| e2b65ea9 YS |
287 | |
| 288 | /* EEPROM */ | |
| 289 | #define CONFIG_ID_EEPROM | |
| e2b65ea9 YS |
290 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 291 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 292 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 293 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 294 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 295 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
| 296 | ||
| e2b65ea9 | 297 | #define CONFIG_FSL_MEMAC |
| e2b65ea9 YS |
298 | |
| 299 | #ifdef CONFIG_PCI | |
| e2b65ea9 | 300 | #define CONFIG_PCI_SCAN_SHOW |
| e2b65ea9 YS |
301 | #endif |
| 302 | ||
| b99ebaf9 AG |
303 | #define BOOT_TARGET_DEVICES(func) \ |
| 304 | func(USB, usb, 0) \ | |
| 305 | func(MMC, mmc, 0) \ | |
| e0db2f42 MYK |
306 | func(SCSI, scsi, 0) \ |
| 307 | func(DHCP, dhcp, na) | |
| b99ebaf9 AG |
308 | #include <config_distro_bootcmd.h> |
| 309 | ||
| 9570df03 | 310 | #ifdef CONFIG_TFABOOT |
| 6596e2e6 KS |
311 | #define QSPI_MC_INIT_CMD \ |
| 312 | "sf probe 0:0; " \ | |
| 313 | "sf read 0x80640000 0x640000 0x80000; " \ | |
| 314 | "env exists secureboot && " \ | |
| 315 | "esbc_validate 0x80640000 && " \ | |
| 316 | "esbc_validate 0x80680000; " \ | |
| 93f8ee8a | 317 | "sf read 0x80a00000 0xa00000 0x200000; " \ |
| 6596e2e6 KS |
318 | "sf read 0x80e00000 0xe00000 0x100000; " \ |
| 319 | "fsl_mc start mc 0x80a00000 0x80e00000 \0" | |
| 9570df03 | 320 | #define SD_MC_INIT_CMD \ |
| 93f8ee8a | 321 | "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \ |
| 196fa2ef | 322 | "mmc read 0x80e00000 0x7000 0x800;" \ |
| 9570df03 | 323 | "env exists secureboot && " \ |
| 8526a58a PS |
324 | "mmc read 0x80640000 0x3200 0x20 && " \ |
| 325 | "mmc read 0x80680000 0x3400 0x20 && " \ | |
| 326 | "esbc_validate 0x80640000 && " \ | |
| 327 | "esbc_validate 0x80680000 ;" \ | |
| 196fa2ef | 328 | "fsl_mc start mc 0x80a00000 0x80e00000\0" |
| 9570df03 RB |
329 | #define IFC_MC_INIT_CMD \ |
| 330 | "env exists secureboot && " \ | |
| 8526a58a PS |
331 | "esbc_validate 0x580640000 && " \ |
| 332 | "esbc_validate 0x580680000; " \ | |
| 9570df03 RB |
333 | "fsl_mc start mc 0x580a00000 0x580e00000 \0" |
| 334 | #else | |
| ec85721c | 335 | #ifdef CONFIG_QSPI_BOOT |
| 6596e2e6 KS |
336 | #define MC_INIT_CMD \ |
| 337 | "mcinitcmd=sf probe 0:0; " \ | |
| 338 | "sf read 0x80640000 0x640000 0x80000; " \ | |
| 339 | "env exists secureboot && " \ | |
| 340 | "esbc_validate 0x80640000 && " \ | |
| 341 | "esbc_validate 0x80680000; " \ | |
| 93f8ee8a | 342 | "sf read 0x80a00000 0xa00000 0x200000; " \ |
| 6596e2e6 KS |
343 | "sf read 0x80e00000 0xe00000 0x100000; " \ |
| 344 | "fsl_mc start mc 0x80a00000 0x80e00000 \0" | |
| bc085549 SL |
345 | #elif defined(CONFIG_SD_BOOT) |
| 346 | #define MC_INIT_CMD \ | |
| 93f8ee8a PJ |
347 | "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \ |
| 348 | "mmc read 0x80e00000 0x7000 0x800;" \ | |
| bc085549 | 349 | "env exists secureboot && " \ |
| 8526a58a PS |
350 | "mmc read 0x80640000 0x3200 0x20 && " \ |
| 351 | "mmc read 0x80680000 0x3400 0x20 && " \ | |
| 352 | "esbc_validate 0x80640000 && " \ | |
| 353 | "esbc_validate 0x80680000 ;" \ | |
| 93f8ee8a | 354 | "fsl_mc start mc 0x80a00000 0x80e00000\0" \ |
| bc085549 | 355 | "mcmemsize=0x70000000\0" |
| ec85721c VP |
356 | #else |
| 357 | #define MC_INIT_CMD \ | |
| 358 | "mcinitcmd=env exists secureboot && " \ | |
| 8526a58a PS |
359 | "esbc_validate 0x580640000 && " \ |
| 360 | "esbc_validate 0x580680000; " \ | |
| ec85721c VP |
361 | "fsl_mc start mc 0x580a00000 0x580e00000 \0" |
| 362 | #endif | |
| 9570df03 | 363 | #endif |
| ec85721c | 364 | |
| e2b65ea9 YS |
365 | /* Initial environment variables */ |
| 366 | #undef CONFIG_EXTRA_ENV_SETTINGS | |
| 9570df03 RB |
367 | #ifdef CONFIG_TFABOOT |
| 368 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 369 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
| 370 | "ramdisk_addr=0x800000\0" \ | |
| 371 | "ramdisk_size=0x2000000\0" \ | |
| 372 | "fdt_high=0xa0000000\0" \ | |
| 373 | "initrd_high=0xffffffffffffffff\0" \ | |
| 374 | "fdt_addr=0x64f00000\0" \ | |
| 375 | "kernel_addr=0x581000000\0" \ | |
| 376 | "kernel_start=0x1000000\0" \ | |
| 377 | "kernelheader_start=0x800000\0" \ | |
| 378 | "scriptaddr=0x80000000\0" \ | |
| 379 | "scripthdraddr=0x80080000\0" \ | |
| 380 | "fdtheader_addr_r=0x80100000\0" \ | |
| 381 | "kernelheader_addr_r=0x80200000\0" \ | |
| 8526a58a | 382 | "kernelheader_addr=0x580600000\0" \ |
| 9570df03 RB |
383 | "kernel_addr_r=0x81000000\0" \ |
| 384 | "kernelheader_size=0x40000\0" \ | |
| 385 | "fdt_addr_r=0x90000000\0" \ | |
| 386 | "load_addr=0xa0000000\0" \ | |
| 387 | "kernel_size=0x2800000\0" \ | |
| 388 | "kernel_addr_sd=0x8000\0" \ | |
| 389 | "kernel_size_sd=0x14000\0" \ | |
| 390 | "console=ttyAMA0,38400n8\0" \ | |
| 391 | "mcmemsize=0x70000000\0" \ | |
| 392 | "sd_bootcmd=echo Trying load from SD ..;" \ | |
| 393 | "mmcinfo; mmc read $load_addr " \ | |
| 394 | "$kernel_addr_sd $kernel_size_sd && " \ | |
| 395 | "bootm $load_addr#$board\0" \ | |
| 396 | QSPI_MC_INIT_CMD \ | |
| 397 | BOOTENV \ | |
| 398 | "boot_scripts=ls2088ardb_boot.scr\0" \ | |
| 399 | "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \ | |
| 400 | "scan_dev_for_boot_part=" \ | |
| 401 | "part list ${devtype} ${devnum} devplist; " \ | |
| 402 | "env exists devplist || setenv devplist 1; " \ | |
| 403 | "for distro_bootpart in ${devplist}; do " \ | |
| 404 | "if fstype ${devtype} " \ | |
| 405 | "${devnum}:${distro_bootpart} " \ | |
| 406 | "bootfstype; then " \ | |
| 407 | "run scan_dev_for_boot; " \ | |
| 408 | "fi; " \ | |
| 409 | "done\0" \ | |
| 9570df03 RB |
410 | "boot_a_script=" \ |
| 411 | "load ${devtype} ${devnum}:${distro_bootpart} " \ | |
| 412 | "${scriptaddr} ${prefix}${script}; " \ | |
| 413 | "env exists secureboot && load ${devtype} " \ | |
| 414 | "${devnum}:${distro_bootpart} " \ | |
| 415 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ | |
| 416 | "&& esbc_validate ${scripthdraddr};" \ | |
| 417 | "source ${scriptaddr}\0" \ | |
| 418 | "qspi_bootcmd=echo Trying load from qspi..;" \ | |
| 419 | "sf probe && sf read $load_addr " \ | |
| 420 | "$kernel_start $kernel_size ; env exists secureboot &&" \ | |
| 421 | "sf read $kernelheader_addr_r $kernelheader_start " \ | |
| 422 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ | |
| 423 | " bootm $load_addr#$board\0" \ | |
| 424 | "nor_bootcmd=echo Trying load from nor..;" \ | |
| 425 | "cp.b $kernel_addr $load_addr " \ | |
| 426 | "$kernel_size ; env exists secureboot && " \ | |
| 427 | "cp.b $kernelheader_addr $kernelheader_addr_r " \ | |
| 428 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ | |
| 429 | "bootm $load_addr#$board\0" | |
| 430 | #else | |
| e2b65ea9 YS |
431 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 432 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
| e2b65ea9 YS |
433 | "ramdisk_addr=0x800000\0" \ |
| 434 | "ramdisk_size=0x2000000\0" \ | |
| 435 | "fdt_high=0xa0000000\0" \ | |
| 436 | "initrd_high=0xffffffffffffffff\0" \ | |
| 0a09d20b | 437 | "fdt_addr=0x64f00000\0" \ |
| 3386c73d | 438 | "kernel_addr=0x581000000\0" \ |
| ec85721c | 439 | "kernel_start=0x1000000\0" \ |
| 8526a58a | 440 | "kernelheader_start=0x600000\0" \ |
| 0a09d20b | 441 | "scriptaddr=0x80000000\0" \ |
| ec85721c | 442 | "scripthdraddr=0x80080000\0" \ |
| 0a09d20b ZY |
443 | "fdtheader_addr_r=0x80100000\0" \ |
| 444 | "kernelheader_addr_r=0x80200000\0" \ | |
| 8526a58a | 445 | "kernelheader_addr=0x580600000\0" \ |
| 0a09d20b | 446 | "kernel_addr_r=0x81000000\0" \ |
| ec85721c | 447 | "kernelheader_size=0x40000\0" \ |
| 0a09d20b ZY |
448 | "fdt_addr_r=0x90000000\0" \ |
| 449 | "load_addr=0xa0000000\0" \ | |
| 16ed8560 | 450 | "kernel_size=0x2800000\0" \ |
| bc085549 SL |
451 | "kernel_addr_sd=0x8000\0" \ |
| 452 | "kernel_size_sd=0x14000\0" \ | |
| 0a09d20b | 453 | "console=ttyAMA0,38400n8\0" \ |
| 8472d876 | 454 | "mcmemsize=0x70000000\0" \ |
| bc085549 SL |
455 | "sd_bootcmd=echo Trying load from SD ..;" \ |
| 456 | "mmcinfo; mmc read $load_addr " \ | |
| 457 | "$kernel_addr_sd $kernel_size_sd && " \ | |
| 458 | "bootm $load_addr#$board\0" \ | |
| ec85721c | 459 | MC_INIT_CMD \ |
| 0a09d20b ZY |
460 | BOOTENV \ |
| 461 | "boot_scripts=ls2088ardb_boot.scr\0" \ | |
| ec85721c | 462 | "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \ |
| 0a09d20b ZY |
463 | "scan_dev_for_boot_part=" \ |
| 464 | "part list ${devtype} ${devnum} devplist; " \ | |
| 465 | "env exists devplist || setenv devplist 1; " \ | |
| 466 | "for distro_bootpart in ${devplist}; do " \ | |
| 467 | "if fstype ${devtype} " \ | |
| 468 | "${devnum}:${distro_bootpart} " \ | |
| 469 | "bootfstype; then " \ | |
| 470 | "run scan_dev_for_boot; " \ | |
| 471 | "fi; " \ | |
| 472 | "done\0" \ | |
| ec85721c VP |
473 | "boot_a_script=" \ |
| 474 | "load ${devtype} ${devnum}:${distro_bootpart} " \ | |
| 475 | "${scriptaddr} ${prefix}${script}; " \ | |
| 476 | "env exists secureboot && load ${devtype} " \ | |
| 477 | "${devnum}:${distro_bootpart} " \ | |
| 78c58082 VP |
478 | "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ |
| 479 | "env exists secureboot " \ | |
| ec85721c VP |
480 | "&& esbc_validate ${scripthdraddr};" \ |
| 481 | "source ${scriptaddr}\0" \ | |
| 0a09d20b ZY |
482 | "qspi_bootcmd=echo Trying load from qspi..;" \ |
| 483 | "sf probe && sf read $load_addr " \ | |
| ec85721c VP |
484 | "$kernel_start $kernel_size ; env exists secureboot &&" \ |
| 485 | "sf read $kernelheader_addr_r $kernelheader_start " \ | |
| 486 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ | |
| 0a09d20b ZY |
487 | " bootm $load_addr#$board\0" \ |
| 488 | "nor_bootcmd=echo Trying load from nor..;" \ | |
| 489 | "cp.b $kernel_addr $load_addr " \ | |
| ec85721c VP |
490 | "$kernel_size ; env exists secureboot && " \ |
| 491 | "cp.b $kernelheader_addr $kernelheader_addr_r " \ | |
| 492 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ | |
| 493 | "bootm $load_addr#$board\0" | |
| 9570df03 RB |
494 | #endif |
| 495 | ||
| 496 | #ifdef CONFIG_TFABOOT | |
| 497 | #define QSPI_NOR_BOOTCOMMAND \ | |
| 934eb607 KS |
498 | "sf probe 0:0; " \ |
| 499 | "sf read 0x806c0000 0x6c0000 0x40000; " \ | |
| 9570df03 | 500 | "env exists mcinitcmd && env exists secureboot "\ |
| 934eb607 KS |
501 | "&& esbc_validate 0x806c0000; " \ |
| 502 | "sf read 0x80d00000 0xd00000 0x100000; " \ | |
| 9570df03 | 503 | "env exists mcinitcmd && " \ |
| 934eb607 | 504 | "fsl_mc lazyapply dpl 0x80d00000; " \ |
| 9570df03 RB |
505 | "run distro_bootcmd;run qspi_bootcmd; " \ |
| 506 | "env exists secureboot && esbc_halt;" | |
| 507 | ||
| 508 | /* Try to boot an on-SD kernel first, then do normal distro boot */ | |
| 509 | #define SD_BOOTCOMMAND \ | |
| 510 | "env exists mcinitcmd && env exists secureboot "\ | |
| 8526a58a | 511 | "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ |
| 9570df03 RB |
512 | "&& esbc_validate $load_addr; " \ |
| 513 | "env exists mcinitcmd && run mcinitcmd " \ | |
| 196fa2ef WK |
514 | "&& mmc read 0x80d00000 0x6800 0x800 " \ |
| 515 | "&& fsl_mc lazyapply dpl 0x80d00000; " \ | |
| 9570df03 RB |
516 | "run distro_bootcmd;run sd_bootcmd; " \ |
| 517 | "env exists secureboot && esbc_halt;" | |
| 9ed44787 | 518 | |
| 9570df03 RB |
519 | /* Try to boot an on-NOR kernel first, then do normal distro boot */ |
| 520 | #define IFC_NOR_BOOTCOMMAND \ | |
| 521 | "env exists mcinitcmd && env exists secureboot "\ | |
| 8526a58a | 522 | "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ |
| 9570df03 RB |
523 | "&& fsl_mc lazyapply dpl 0x580d00000;" \ |
| 524 | "run distro_bootcmd;run nor_bootcmd; " \ | |
| 525 | "env exists secureboot && esbc_halt;" | |
| 526 | #else | |
| b99ebaf9 | 527 | #undef CONFIG_BOOTCOMMAND |
| 89a168f7 | 528 | #ifdef CONFIG_QSPI_BOOT |
| 89a168f7 | 529 | /* Try to boot an on-QSPI kernel first, then do normal distro boot */ |
| 0a09d20b | 530 | #define CONFIG_BOOTCOMMAND \ |
| 934eb607 KS |
531 | "sf probe 0:0; " \ |
| 532 | "sf read 0x806c0000 0x6c0000 0x40000; " \ | |
| ec85721c | 533 | "env exists mcinitcmd && env exists secureboot "\ |
| 934eb607 KS |
534 | "&& esbc_validate 0x806C0000; " \ |
| 535 | "sf read 0x80d00000 0xd00000 0x100000; " \ | |
| ec85721c | 536 | "env exists mcinitcmd && " \ |
| 934eb607 | 537 | "fsl_mc lazyapply dpl 0x80d00000; " \ |
| 3386c73d VP |
538 | "run distro_bootcmd;run qspi_bootcmd; " \ |
| 539 | "env exists secureboot && esbc_halt;" | |
| bc085549 SL |
540 | #elif defined(CONFIG_SD_BOOT) |
| 541 | /* Try to boot an on-SD kernel first, then do normal distro boot */ | |
| 542 | #define CONFIG_BOOTCOMMAND \ | |
| 543 | "env exists mcinitcmd && env exists secureboot "\ | |
| 8526a58a | 544 | "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ |
| bc085549 SL |
545 | "&& esbc_validate $load_addr; " \ |
| 546 | "env exists mcinitcmd && run mcinitcmd " \ | |
| 547 | "&& mmc read 0x88000000 0x6800 0x800 " \ | |
| 548 | "&& fsl_mc lazyapply dpl 0x88000000; " \ | |
| 3386c73d VP |
549 | "run distro_bootcmd;run sd_bootcmd; " \ |
| 550 | "env exists secureboot && esbc_halt;" | |
| 9ed44787 | 551 | #else |
| b99ebaf9 | 552 | /* Try to boot an on-NOR kernel first, then do normal distro boot */ |
| 0a09d20b | 553 | #define CONFIG_BOOTCOMMAND \ |
| ec85721c | 554 | "env exists mcinitcmd && env exists secureboot "\ |
| 8526a58a | 555 | "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ |
| ec85721c | 556 | "&& fsl_mc lazyapply dpl 0x580d00000;" \ |
| 3386c73d VP |
557 | "run distro_bootcmd;run nor_bootcmd; " \ |
| 558 | "env exists secureboot && esbc_halt;" | |
| 89a168f7 | 559 | #endif |
| 9570df03 | 560 | #endif |
| 9ed44787 | 561 | |
| 3484d953 | 562 | /* MAC/PHY configuration */ |
| 3484d953 PK |
563 | #define CORTINA_PHY_ADDR1 0x10 |
| 564 | #define CORTINA_PHY_ADDR2 0x11 | |
| 565 | #define CORTINA_PHY_ADDR3 0x12 | |
| 566 | #define CORTINA_PHY_ADDR4 0x13 | |
| 567 | #define AQ_PHY_ADDR1 0x00 | |
| 568 | #define AQ_PHY_ADDR2 0x01 | |
| 569 | #define AQ_PHY_ADDR3 0x02 | |
| 570 | #define AQ_PHY_ADDR4 0x03 | |
| abc7d0f7 | 571 | #define AQR405_IRQ_MASK 0x36 |
| 7ad9cc96 | 572 | #define CONFIG_ETHPRIME "DPMAC1@xgmii" |
| 3484d953 | 573 | |
| fcfdb6d5 SJ |
574 | #include <asm/fsl_secure_boot.h> |
| 575 | ||
| e2b65ea9 | 576 | #endif /* __LS2_RDB_H */ |