[J-u-boot.git] / include / configs / M5253DEMO.h

/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * Hayden Fraser ([email protected])
 */

#ifndef _M5253DEMO_H
#define _M5253DEMO_H

#include <linux/stringify.h>

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG		/* disable watchdog */


/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	env/embedded.o(.text*);

#ifdef CONFIG_IDE
/* ATA */
#	define CONFIG_IDE_RESET		1
#	define CONFIG_IDE_PREINIT	1
#	define CONFIG_ATAPI
#	undef CONFIG_LBA48

#	define CONFIG_SYS_IDE_MAXBUS		1
#	define CONFIG_SYS_IDE_MAXDEVICE	2

#	define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
#	define CONFIG_SYS_ATA_IDE0_OFFSET	0

#	define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
#	define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#	define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
#	define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
#endif

#define CONFIG_DRIVER_DM9000
#ifdef CONFIG_DRIVER_DM9000
#	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
#	define DM9000_IO		CONFIG_DM9000_BASE
#	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
#	undef CONFIG_DM9000_DEBUG
#	define CONFIG_DM9000_BYTE_SWAPPED

#	define CONFIG_OVERWRITE_ETHADDR_ONCE

#	define CONFIG_EXTRA_ENV_SETTINGS		\
		"netdev=eth0\0"				\
		"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
		"loadaddr=10000\0"			\
		"u-boot=u-boot.bin\0"			\
		"load=tftp ${loadaddr) ${u-boot}\0"	\
		"upd=run load; run prog\0"		\
		"prog=prot off 0xff800000 0xff82ffff;"	\
		"era 0xff800000 0xff82ffff;"		\
		"cp.b ${loadaddr} 0xff800000 ${filesize};"	\
		"save\0"				\
		""
#endif

#define CONFIG_HOSTNAME		"M5253DEMO"

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000280
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG	(*(u32 *) (CONFIG_SYS_MBAR+0x19C))
#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFFFE7FF)
#define CONFIG_SYS_I2C_PINMUX_SET	(0)

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
#	define CONFIG_SYS_PLLCR	0x1243E054
#	define CONFIG_SYS_CLK		140000000
#else
#	define CONFIG_SYS_PLLCR	0x135a4140
#	define CONFIG_SYS_CLK		70000000
#endif

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */

#ifdef CONFIG_MONITOR_IS_IN_RAM
#	define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x40000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000

#define FLASH_SST6401B		0x200
#define SST_ID_xF6401B		0x236D236D

#ifdef CONFIG_SYS_FLASH_CFI
/*
 * Unable to use CFI driver, due to incompatible sector erase command by SST.
 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
 * 0x30 is block erase in SST
 */
#	define CONFIG_SYS_FLASH_SIZE		0x800000
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_FLASH_CFI_LEGACY
#else
#	define CONFIG_SYS_SST_SECT		2048
#	define CONFIG_SYS_SST_SECTSZ		0x1000
#	define CONFIG_SYS_FLASH_WRITE_TOUT	500
#endif

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
					 CF_ADDRMASK(8) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
					 CF_CACR_DBWE)

/* Port configuration */
#define CONFIG_SYS_FECI2C		0xF0

#define CONFIG_SYS_CS0_BASE		0xFF800000
#define CONFIG_SYS_CS0_MASK		0x007F0021
#define CONFIG_SYS_CS0_CTRL		0x00001D80

#define CONFIG_SYS_CS1_BASE		0xE0000000
#define CONFIG_SYS_CS1_MASK		0x00000001
#define CONFIG_SYS_CS1_CTRL		0x00003DD8

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */

#endif				/* _M5253DEMO_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
6af3a0ea	2	/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6d33c6ac	3	* Hayden Fraser ([email protected])
6d33c6ac TL	4	*/
	5
	6	#ifndef _M5253DEMO_H
	7	#define _M5253DEMO_H
	8
1af3c7f4 SG	9	#include <linux/stringify.h>
1af3c7f4 SG	10
6d33c6ac TL	11	#define CONFIG_MCFTMR
	12
	13	#define CONFIG_MCFUART
6d0f6bcf	14	#define CONFIG_SYS_UART_PORT (0)
6d33c6ac TL	15
	16	#undef CONFIG_WATCHDOG /* disable watchdog */
	17
6d33c6ac TL	18
	19	/* Configuration for environment
	20	* Environment is embedded in u-boot in the second sector of the flash
	21	*/
6d33c6ac	22
5296cb1d	23	#define LDS_BOARD_TEXT \
0649cd0d SG	24	. = DEFINED(env_offset) ? env_offset : .; \
0649cd0d SG	25	env/embedded.o(.text*);
5296cb1d	26
fc843a02	27	#ifdef CONFIG_IDE
6d33c6ac	28	/* ATA */
6d33c6ac TL	29	# define CONFIG_IDE_RESET 1
	30	# define CONFIG_IDE_PREINIT 1
	31	# define CONFIG_ATAPI
	32	# undef CONFIG_LBA48
	33
6d0f6bcf JCPV	34	# define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	35	# define CONFIG_SYS_IDE_MAXDEVICE 2
6d33c6ac	36
6d0f6bcf JCPV	37	# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
6d0f6bcf JCPV	38	# define CONFIG_SYS_ATA_IDE0_OFFSET 0
6d33c6ac	39
6d0f6bcf JCPV	40	# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	41	# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	42	# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	43	# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
6d33c6ac TL	44	#endif
	45
	46	#define CONFIG_DRIVER_DM9000
	47	#ifdef CONFIG_DRIVER_DM9000
012522fe	48	# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE \| 0x300)
6d33c6ac TL	49	# define DM9000_IO CONFIG_DM9000_BASE
	50	# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
	51	# undef CONFIG_DM9000_DEBUG
f73e7d67	52	# define CONFIG_DM9000_BYTE_SWAPPED
6d33c6ac	53
6d33c6ac TL	54	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	55
	56	# define CONFIG_EXTRA_ENV_SETTINGS \
	57	"netdev=eth0\0" \
5368c55d	58	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
6d33c6ac TL	59	"loadaddr=10000\0" \
	60	"u-boot=u-boot.bin\0" \
	61	"load=tftp ${loadaddr) ${u-boot}\0" \
	62	"upd=run load; run prog\0" \
ac265f7f TL	63	"prog=prot off 0xff800000 0xff82ffff;" \
ac265f7f TL	64	"era 0xff800000 0xff82ffff;" \
f26a2473	65	"cp.b ${loadaddr} 0xff800000 ${filesize};" \
6d33c6ac TL	66	"save\0" \
	67	""
	68	#endif
	69
5bc0543d	70	#define CONFIG_HOSTNAME "M5253DEMO"
6d33c6ac	71
eec567a6	72	/* I2C */
00f792e0 HS	73	#define CONFIG_SYS_I2C
	74	#define CONFIG_SYS_I2C_FSL
	75	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	76	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	77	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
6d0f6bcf JCPV	78	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	79	#define CONFIG_SYS_I2C_PINMUX_REG ((u32 ) (CONFIG_SYS_MBAR+0x19C))
	80	#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
	81	#define CONFIG_SYS_I2C_PINMUX_SET (0)
eec567a6	82
6d0f6bcf	83	#define CONFIG_SYS_LOAD_ADDR 0x00100000
6d33c6ac	84
6d0f6bcf JCPV	85	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
	86	#define CONFIG_SYS_FAST_CLK
	87	#ifdef CONFIG_SYS_FAST_CLK
	88	# define CONFIG_SYS_PLLCR 0x1243E054
	89	# define CONFIG_SYS_CLK 140000000
6d33c6ac	90	#else
6d0f6bcf JCPV	91	# define CONFIG_SYS_PLLCR 0x135a4140
6d0f6bcf JCPV	92	# define CONFIG_SYS_CLK 70000000
6d33c6ac TL	93	#endif
	94
	95	/*
	96	* Low Level Configuration Settings
	97	* (address mappings, register initial values, etc.)
	98	* You should know what you are doing if you make changes here.
	99	*/
	100
6d0f6bcf JCPV	101	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
6d0f6bcf JCPV	102	#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
6d33c6ac TL	103
	104	/*
	105	* Definitions for initial stack pointer and data area (in DPRAM)
	106	*/
6d0f6bcf	107	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	108	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
25ddd1fb	109	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	110	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
6d33c6ac TL	111
	112	/*
	113	* Start addresses for the final memory configuration
	114	* (Set up by the startup code)
6d0f6bcf	115	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
6d33c6ac	116	*/
6d0f6bcf JCPV	117	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	118	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
6d33c6ac TL	119
6d33c6ac TL	120	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	121	# define CONFIG_SYS_MONITOR_BASE 0x20000
6d33c6ac	122	#else
6d0f6bcf	123	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d33c6ac TL	124	#endif
6d33c6ac TL	125
6d0f6bcf JCPV	126	#define CONFIG_SYS_MONITOR_LEN 0x40000
	127	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	128	#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
6d33c6ac TL	129
	130	/*
	131	* For booting Linux, the board info and command line data
	132	* have to be in the first 8 MB of memory, since this is
	133	* the maximum mapped by the Linux kernel during initialization ??
	134	*/
6d0f6bcf	135	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	136	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
6d33c6ac TL	137
6d33c6ac TL	138	/* FLASH organization */
012522fe	139	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
6d0f6bcf JCPV	140	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	141	#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
	142	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
6d33c6ac TL	143
	144	#define FLASH_SST6401B 0x200
	145	#define SST_ID_xF6401B 0x236D236D
	146
6d0f6bcf	147	#ifdef CONFIG_SYS_FLASH_CFI
6d33c6ac TL	148	/*
	149	* Unable to use CFI driver, due to incompatible sector erase command by SST.
	150	* Amd/Atmel use 0x30 for sector erase, SST use 0x50.
	151	* 0x30 is block erase in SST
	152	*/
6d0f6bcf JCPV	153	# define CONFIG_SYS_FLASH_SIZE 0x800000
6d0f6bcf JCPV	154	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
6d33c6ac TL	155	# define CONFIG_FLASH_CFI_LEGACY
6d33c6ac TL	156	#else
6d0f6bcf JCPV	157	# define CONFIG_SYS_SST_SECT 2048
	158	# define CONFIG_SYS_SST_SECTSZ 0x1000
	159	# define CONFIG_SYS_FLASH_WRITE_TOUT 500
6d33c6ac TL	160	#endif
	161
	162	/* Cache Configuration */
6d0f6bcf	163	#define CONFIG_SYS_CACHELINE_SIZE 16
6d33c6ac	164
dd9f054e	165	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	166	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	167	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	168	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	169	#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
	170	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE \| \
	171	CF_ADDRMASK(8) \| \
	172	CF_ACR_EN \| CF_ACR_SM_ALL)
	173	#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE \| \
	174	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	175	CF_ACR_EN \| CF_ACR_SM_ALL)
	176	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CEIB \| \
	177	CF_CACR_DBWE)
	178
6d33c6ac	179	/* Port configuration */
6d0f6bcf	180	#define CONFIG_SYS_FECI2C 0xF0
6d33c6ac	181
012522fe TL	182	#define CONFIG_SYS_CS0_BASE 0xFF800000
	183	#define CONFIG_SYS_CS0_MASK 0x007F0021
	184	#define CONFIG_SYS_CS0_CTRL 0x00001D80
6d33c6ac	185
012522fe TL	186	#define CONFIG_SYS_CS1_BASE 0xE0000000
	187	#define CONFIG_SYS_CS1_MASK 0x00000001
	188	#define CONFIG_SYS_CS1_CTRL 0x00003DD8
6d33c6ac TL	189
	190	/*-----------------------------------------------------------------------
	191	* Port configuration
	192	*/
6d0f6bcf JCPV	193	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
	194	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
	195	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
	196	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
	197	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
	198	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
	199	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
6d33c6ac TL	200
6d33c6ac TL	201	#endif /* _M5253DEMO_H */