[J-u-boot.git] / include / configs / CPCI440.h

/*
 * (C) Copyright 2002
 * Stefan Roese, esd gmbh germany, [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * board/config_CPCI440.h - configuration for esd CPCI-440 board
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_EBONY		1	    /* Board is ebony		*/
#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/

#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
#define CFG_GBL_DATA_SIZE  128		    /* num bytes initial data	*/

#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN	    (192 * 1024)    /* Reserve 192 kB for Mon	*/
#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#undef CFG_EXT_SERIAL_CLOCK /*	 (1843200 * 6)	 / * Ext clk @ 11.059 MHz */
#define CONFIG_BAUDRATE		9600

#define CFG_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}

/*-----------------------------------------------------------------------
 * NVRAM/RTC
 *
 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
 * The DS1743 code assumes this condition (i.e. -- it assumes the base
 * address for the RTC registers is:
 *
 *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
 *
 *----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#if 1 /* test-only */

#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_FLASH_INCREMENT	0	/* there is only one bank		*/
#define CFG_FLASH_PROTECTION	1	/* use hardware protection		*/
#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#undef CFG_FLASH_BASE
#define CFG_FLASH_BASE		0xFF800000 /* test-only...*/

#else /* test-only */

#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
#define CFG_MAX_FLASH_SECT	32		    /* sectors per device   */

#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#endif

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#if 0 /* test-only */
#define CFG_ENV_IS_IN_NVRAM	1	    /* Environment uses NVRAM	*/
#undef	CFG_ENV_IS_IN_FLASH		    /* ... not in flash		*/
#undef	CFG_ENV_IS_IN_EEPROM		    /* ... not in EEPROM	*/

#define CFG_ENV_SIZE		0x1000	    /* Size of Environment vars */
#define CFG_ENV_ADDR		\
	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
#else

#if 0 /* test-only */
#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CFG_ENV_OFFSET		0x010	/* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
				   /* total size of a CAT24WC16 is 2048 bytes */
#else
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
#endif

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

#endif

#define CONFIG_BOOTARGS		"root=/dev/hda1 "
#define CONFIG_BOOTCOMMAND	"bootm ffc00000"    /* autoboot command */
#define CONFIG_BOOTDELAY	-1		    /* disable autoboot */
#define CONFIG_BAUDRATE		9600

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		1	/* PHY address			*/

#if 0 /* test-only */
#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_I2C	| \
				CFG_CMD_KGDB	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_DATE	| \
				CFG_CMD_BEDBUG	| \
				CFG_CMD_ELF	)
#else
#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_ELF	| \
				CFG_CMD_DATE	| \
				CFG_CMD_I2C	| \
				CFG_CMD_EEPROM	)
/* test-only: support fehlt bisher... */
/*				CFG_CMD_IDE	| \*/
/*				CFG_CMD_PCI	| \*/
#endif

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

#undef CONFIG_SPD_EEPROM       /* don't use SPD EEPROM for setup    */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#if 0 /* test-only */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F
#endif


/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#if 0
#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
					/* resource configuration	*/

#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */

#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/

#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
#endif

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		32768	/* For IBM 440 CPUs			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif


/* Configuration Port location */
#define CONFIG_PORT_ADDR	0xF0000500

/*-----------------------------------------------------------------------
 * Definitions for Serial Presence Detect EEPROM address
 * (to get SDRAM settings)
 */
#define SPD_EEPROM_ADDRESS	0x50

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* (C) Copyright 2002
	3	* Stefan Roese, esd gmbh germany, [email protected]
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/************************************************************************
	25	* board/config_CPCI440.h - configuration for esd CPCI-440 board
	26	***********************************************************************/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*-----------------------------------------------------------------------
	32	* High Level Configuration Options
	33	----------------------------------------------------------------------/
	34	#define CONFIG_EBONY 1 /* Board is ebony */
	35	#define CONFIG_4xx 1 /* ... PPC4xx family */
c837dcb1	36	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
0f8c9768 WD	37	#undef CFG_DRAM_TEST /* Disable-takes long time! */
	38	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	39
	40	/*-----------------------------------------------------------------------
	41	* Base addresses -- Note these are effective addresses where the
	42	* actual resources get mapped (not physical addresses)
	43	----------------------------------------------------------------------/
	44	#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	45	#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
	46	#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
	47	#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
	48	#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
	49
	50	#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
	51	#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
	52
	53	/*-----------------------------------------------------------------------
	54	* Initial RAM & stack pointer (placed in internal SRAM)
	55	----------------------------------------------------------------------/
	56	#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
	57	#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
	58	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
	59
	60	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	61	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	62
	63	#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Mon */
	64	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
	65
	66	/*-----------------------------------------------------------------------
	67	* Serial Port
	68	----------------------------------------------------------------------/
	69	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	70	#undef CFG_EXT_SERIAL_CLOCK /* (1843200 * 6) / * Ext clk @ 11.059 MHz */
	71	#define CONFIG_BAUDRATE 9600
	72
	73	#define CFG_BAUDRATE_TABLE \
	74	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
	75
	76	/*-----------------------------------------------------------------------
	77	* NVRAM/RTC
	78	*
	79	* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
	80	* The DS1743 code assumes this condition (i.e. -- it assumes the base
	81	* address for the RTC registers is:
	82	*
	83	* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
	84	*
	85	----------------------------------------------------------------------/
	86	#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
	87	#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
	88
	89	/*-----------------------------------------------------------------------
	90	* FLASH related
	91	----------------------------------------------------------------------/
	92	#if 1 /* test-only */
	93
	94	#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
	95	#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
	96	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	97	#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
	98	#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
	99	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
	100	#undef CFG_FLASH_BASE
101	#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/
102
103	#else /* test-only */
104
105	#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
106	#define CFG_MAX_FLASH_SECT 32 /* sectors per device */
107
108	#undef CFG_FLASH_CHECKSUM
109	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
110	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
111
112	#endif
113
114	/*-----------------------------------------------------------------------
115	* Environment
116	----------------------------------------------------------------------/
117	#if 0 /* test-only */
118	#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
119	#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
120	#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
121
122	#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
123	#define CFG_ENV_ADDR \
124	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
125	#else
126
127	#if 0 /* test-only */
128	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
129	#define CFG_ENV_OFFSET 0x010 /* environment starts at the beginning of the EEPROM */
130	#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
131	/* total size of a CAT24WC16 is 2048 bytes */
132	#else
133	#define CFG_ENV_IS_IN_FLASH 1
134	#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
135	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
136	#endif
137
138	/*-----------------------------------------------------------------------
139	* I2C EEPROM (CAT24WC16) for environment
140	*/
141	#define CONFIG_HARD_I2C /* I2c with hardware support */
142	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
143	#define CFG_I2C_SLAVE 0x7F
144
145	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
146	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
147	/* mask of address bits that overflow into the "EEPROM chip address" */
148	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
149	#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
150	/* 16 byte page write mode using*/
151	/* last 4 bits of the address */
152	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
153	#define CFG_EEPROM_PAGE_WRITE_ENABLE
154
155	#endif
156
157	#define CONFIG_BOOTARGS "root=/dev/hda1 "
158	#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
159	#define CONFIG_BOOTDELAY -1 /* disable autoboot */
160	#define CONFIG_BAUDRATE 9600
161
162	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
163	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
164
165	#define CONFIG_MII 1 /* MII PHY management */
166	#define CONFIG_PHY_ADDR 1 /* PHY address */
167
168	#if 0 /* test-only */
169	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
170	CFG_CMD_IRQ \| \
171	CFG_CMD_I2C \| \
172	CFG_CMD_KGDB \| \
173	CFG_CMD_DHCP \| \
174	CFG_CMD_DATE \| \
175	CFG_CMD_BEDBUG \| \
176	CFG_CMD_ELF )
177	#else
178	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
179	CFG_CMD_IRQ \| \
180	CFG_CMD_ELF \| \
181	CFG_CMD_DATE \| \
182	CFG_CMD_I2C \| \
183	CFG_CMD_EEPROM )
184	/* test-only: support fehlt bisher... */
185	/* CFG_CMD_IDE \| \*/
186	/* CFG_CMD_PCI \| \*/
187	#endif
188
189	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
190	#include <cmd_confdefs.h>
191
192	#undef CONFIG_WATCHDOG /* watchdog disabled */
193
194	#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for setup */
195
196	/*
197	* Miscellaneous configurable options
198	*/
199	#define CFG_LONGHELP /* undef to save memory */
200	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
201	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
202	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
203	#else
204	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
205	#endif
206	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
207	#define CFG_MAXARGS 16 /* max number of command args */
208	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
209
210	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
211	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
212
213	#define CFG_LOAD_ADDR 0x100000 /* default load address */
214	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
215
216	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
217
218	#if 0 /* test-only */
219	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
220	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
221	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
222	#define CFG_I2C_SLAVE 0x7F
223	#endif
224
225
226	/*-----------------------------------------------------------------------
227	* PCI stuff
228	*-----------------------------------------------------------------------
229	*/
230	#if 0
231	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
232	#define PCI_HOST_FORCE 1 /* configure as pci host */
233	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
234
235	#define CONFIG_PCI /* include pci support */
236	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
237	#define CONFIG_PCI_PNP /* do pci plug-and-play */
238	/* resource configuration */
239
ad10dd9a SR	240	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	241
	242	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
	243
0f8c9768 WD	244	#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
	245	#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
	246	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	247	#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	248	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	249	#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
	250	#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
	251	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
	252	#endif
	253
	254	/*
	255	* For booting Linux, the board info and command line data
	256	* have to be in the first 8 MB of memory, since this is
	257	* the maximum mapped by the Linux kernel during initialization.
	258	*/
	259	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	260	/*-----------------------------------------------------------------------
	261	* Cache Configuration
	262	*/
	263	#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
	264	#define CFG_CACHELINE_SIZE 32 /* ... */
	265	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	266	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	267	#endif
	268
	269
	270	/* Configuration Port location */
	271	#define CONFIG_PORT_ADDR 0xF0000500
	272
	273	/*-----------------------------------------------------------------------
	274	* Definitions for Serial Presence Detect EEPROM address
	275	* (to get SDRAM settings)
	276	*/
	277	#define SPD_EEPROM_ADDRESS 0x50
	278
	279	/*
	280	* Internal Definitions
	281	*
	282	* Boot Flags
	283	*/
	284	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	285	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	286
	287	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	288	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	289	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	290	#endif
	291	#endif /* __CONFIG_H */