[J-u-boot.git] / include / configs / AR405.h

/*
 * (C) Copyright 2001
 * Stefan Roese, esd gmbh germany, [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_AR405		1	/* ...on a AR405 board		*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/

#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#if 1
#define CONFIG_BOOTCOMMAND	"bootm fff00000" /* autoboot command	*/
#else
#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
#endif

#if 0
#define CONFIG_BOOTARGS		"root=/dev/nfs "			\
    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 "	\
    "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
#else
#define CONFIG_BOOTARGS		"root=/dev/hda1 "			\
    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"

#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/

#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_PCI	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_ELF	)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
					/* resource configuration	*/

#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/

#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CFG_PCI_SUBSYS_DEVICEID 0x0403	/* PCI Device ID: ARISTO405	*/
#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
#define CFG_PCI_PTM2LA	0xfff00000	/* point to flash		*/
#define CFG_PCI_PTM2MS	0xfff00001	/* 1MB, enable			*/
#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFD0000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/

#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		8192	/* For IBM 405 CPUs			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CFG_EBC_PB0AP		0x92015480
#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (CAN0, 1, 2, 3) initialization					*/
#define CFG_EBC_PB1AP		0x01000380  /* enable Ready, BEM=0		*/
#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 2 (Expension Bus) initialization					*/
#define CFG_EBC_PB2AP		0x01000280  /* disable Ready, BEM=0		*/
#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (16552) initialization						*/
#define CFG_EBC_PB3AP		0x01000380  /* enable Ready, BEM=0		*/
#define CFG_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 4 (FPGA regs) initialization					*/
#define CFG_EBC_PB4AP		0x01005380  /* enable Ready, BEM=0		*/
#define CFG_EBC_PB4CR		0xF031C000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */

/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization				*/
#define CFG_EBC_PB5AP		0x92015480
#define CFG_EBC_PB5CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */

#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
ab255f26 WD	1	/*
	2	* (C) Copyright 2001
	3	* Stefan Roese, esd gmbh germany, [email protected]
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
c837dcb1 WD	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	38	#define CONFIG_AR405 1 /* ...on a AR405 board */
ab255f26	39
c837dcb1	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
ab255f26	41
c837dcb1	42	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
ab255f26 WD	43
	44	#define CONFIG_BAUDRATE 9600
	45	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	46
	47	#if 1
	48	#define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */
	49	#else
	50	#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
	51	#endif
	52
	53	#if 0
c837dcb1 WD	54	#define CONFIG_BOOTARGS "root=/dev/nfs " \
c837dcb1 WD	55	"ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
ab255f26 WD	56	"nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
	57	#else
	58	#define CONFIG_BOOTARGS "root=/dev/hda1 " \
	59	"ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
	60
	61	#endif
	62
	63	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	64	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	65
	66	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	67	#define CONFIG_PHY_ADDR 0 /* PHY address */
ab255f26	68
c5d22906 SR	69	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
	70	CFG_CMD_PCI \| \
	71	CFG_CMD_IRQ \| \
	72	CFG_CMD_ELF )
ab255f26 WD	73
	74	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	75	#include <cmd_confdefs.h>
	76
	77	#undef CONFIG_WATCHDOG /* watchdog disabled */
	78
c837dcb1	79	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
ab255f26 WD	80
	81	/*
	82	* Miscellaneous configurable options
	83	*/
	84	#define CFG_LONGHELP /* undef to save memory */
	85	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	86	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
c837dcb1	87	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
ab255f26	88	#else
c837dcb1	89	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
ab255f26 WD	90	#endif
	91	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	92	#define CFG_MAXARGS 16 /* max number of command args */
	93	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	94
c837dcb1	95	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
ab255f26 WD	96
	97	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	98	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	99
c837dcb1	100	#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
ab255f26 WD	101
ab255f26 WD	102	/* The following table includes the supported baudrates */
c837dcb1	103	#define CFG_BAUDRATE_TABLE \
8bde7f77 WD	104	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	105	57600, 115200, 230400, 460800, 921600 }
ab255f26 WD	106
	107	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	108	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	109
c837dcb1	110	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
ab255f26 WD	111
	112	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	113
	114	/*-----------------------------------------------------------------------
	115	* PCI stuff
	116	*-----------------------------------------------------------------------
	117	*/
c837dcb1 WD	118	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	119	#define PCI_HOST_FORCE 1 /* configure as pci host */
	120	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
ab255f26	121
c837dcb1 WD	122	#define CONFIG_PCI /* include pci support */
	123	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	124	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	125	/* resource configuration */
ab255f26	126
c837dcb1	127	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
ad10dd9a	128
c837dcb1	129	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
ad10dd9a	130
c837dcb1 WD	131	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	132	#define CFG_PCI_SUBSYS_DEVICEID 0x0403 /* PCI Device ID: ARISTO405 */
	133	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	134	#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	135	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	136	#define CFG_PCI_PTM2LA 0xfff00000 /* point to flash */
	137	#define CFG_PCI_PTM2MS 0xfff00001 /* 1MB, enable */
	138	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
ab255f26 WD	139
	140	/*-----------------------------------------------------------------------
	141	* Start addresses for the final memory configuration
	142	* (Set up by the startup code)
	143	* Please note that CFG_SDRAM_BASE _must_ start at 0
	144	*/
	145	#define CFG_SDRAM_BASE 0x00000000
	146	#define CFG_FLASH_BASE 0xFFFD0000
	147	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	148	#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
	149	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	150
	151	/*
	152	* For booting Linux, the board info and command line data
	153	* have to be in the first 8 MB of memory, since this is
	154	* the maximum mapped by the Linux kernel during initialization.
	155	*/
	156	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	157	/*-----------------------------------------------------------------------
	158	* FLASH organization
	159	*/
	160	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	161	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	162
	163	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	164	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	165
c837dcb1 WD	166	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	167	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	168	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
ab255f26 WD	169	/*
	170	* The following defines are added for buggy IOP480 byte interface.
	171	* All other boards should use the standard values (CPCI405 etc.)
	172	*/
c837dcb1 WD	173	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	174	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	175	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
ab255f26	176
c837dcb1	177	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
ab255f26	178
c837dcb1 WD	179	#define CFG_ENV_IS_IN_FLASH 1
c837dcb1 WD	180	#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
ab255f26 WD	181	#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
ab255f26 WD	182
c837dcb1	183	#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
ab255f26 WD	184
	185	/*-----------------------------------------------------------------------
	186	* Cache Configuration
	187	*/
	188	#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
	189	#define CFG_CACHELINE_SIZE 32 /* ... */
	190	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	191	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	192	#endif
	193
	194	/*
	195	* Init Memory Controller:
	196	*
	197	* BR0/1 and OR0/1 (FLASH)
	198	*/
	199
	200	#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
	201	#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
	202
	203	/*-----------------------------------------------------------------------
	204	* External Bus Controller (EBC) Setup
	205	*/
	206
c837dcb1 WD	207	/* Memory Bank 0 (Flash Bank 0) initialization */
	208	#define CFG_EBC_PB0AP 0x92015480
	209	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
ab255f26	210
c837dcb1 WD	211	/* Memory Bank 1 (CAN0, 1, 2, 3) initialization */
	212	#define CFG_EBC_PB1AP 0x01000380 /* enable Ready, BEM=0 */
	213	#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
ab255f26	214
c837dcb1 WD	215	/* Memory Bank 2 (Expension Bus) initialization */
	216	#define CFG_EBC_PB2AP 0x01000280 /* disable Ready, BEM=0 */
	217	#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
ab255f26	218
c837dcb1 WD	219	/* Memory Bank 3 (16552) initialization */
	220	#define CFG_EBC_PB3AP 0x01000380 /* enable Ready, BEM=0 */
	221	#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
ab255f26	222
c837dcb1 WD	223	/* Memory Bank 4 (FPGA regs) initialization */
	224	#define CFG_EBC_PB4AP 0x01005380 /* enable Ready, BEM=0 */
	225	#define CFG_EBC_PB4CR 0xF031C000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
ab255f26	226
c837dcb1 WD	227	/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization */
	228	#define CFG_EBC_PB5AP 0x92015480
	229	#define CFG_EBC_PB5CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
ab255f26 WD	230
ab255f26 WD	231	/*-----------------------------------------------------------------------
c5d22906	232	* Definitions for initial stack pointer and data area (in data cache)
ab255f26	233	*/
c837dcb1	234	#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
ab255f26	235
c837dcb1 WD	236	#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
c837dcb1 WD	237	#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
c5d22906 SR	238	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
c5d22906 SR	239	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
c837dcb1	240	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
ab255f26 WD	241
	242	/*
	243	* Internal Definitions
	244	*
	245	* Boot Flags
	246	*/
	247	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	248	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	249
	250	#endif /* __CONFIG_H */