[J-u-boot.git] / include / configs / ls1043a_common.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2015 Freescale Semiconductor
 */

#ifndef __LS1043A_COMMON_H
#define __LS1043A_COMMON_H

/* SPL build */
#ifdef CONFIG_SPL_BUILD
#define SPL_NO_FMAN
#define SPL_NO_DSPI
#define SPL_NO_PCIE
#define SPL_NO_ENV
#define SPL_NO_MISC
#define SPL_NO_USB
#define SPL_NO_SATA
#define SPL_NO_QE
#define SPL_NO_EEPROM
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
#define SPL_NO_MMC
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
#define SPL_NO_IFC
#endif

#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_MP
#define CONFIG_GICV2

#include <asm/arch/stream_id_lsch2.h>
#include <asm/arch/config.h>

/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL

#define CPU_RELEASE_ADDR               secondary_boot_func

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)

/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x17000
#define CONFIG_SPL_STACK		0x1001e000
#define CONFIG_SPL_PAD_TO		0x1d000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_SECURE_BOOT */
#endif

/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
#endif /* ifdef CONFIG_SECURE_BOOT */

#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */

#endif

/* IFC */
#ifndef SPL_NO_IFC
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
/*
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 */
#define CONFIG_SYS_FLASH_BASE			0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
#endif
#endif
#endif

/* I2C */
#define CONFIG_SYS_I2C

/* PCIe */
#ifndef SPL_NO_PCIE
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */
#define CONFIG_PCIE3		/* PCIE controller 3 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
#endif

/* Command line configuration */

/*  MMC  */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#endif

/*  DSPI  */
#ifndef SPL_NO_DSPI
#define CONFIG_FSL_DSPI
#ifdef CONFIG_FSL_DSPI
#define CONFIG_DM_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO	/* cs0 */
#define CONFIG_SPI_FLASH_SST		/* cs1 */
#define CONFIG_SPI_FLASH_EON		/* cs2 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SF_DEFAULT_BUS		1
#define CONFIG_SF_DEFAULT_CS		0
#endif
#endif
#endif

/* FMan ucode */
#ifndef SPL_NO_FMAN
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE	0x60000

#ifdef CONFIG_NAND_BOOT
/* Store Fman ucode at offeset 0x900000(72 blocks). */
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR		(72 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
/*
 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
 */
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
#define CONFIG_SYS_QE_FW_ADDR		(512 * 0x4a08)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
#define CONFIG_ENV_SPI_BUS		0
#define CONFIG_ENV_SPI_CS		0
#define CONFIG_ENV_SPI_MAX_HZ		1000000
#define CONFIG_ENV_SPI_MODE		0x03
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* FMan fireware Pre-load address */
#define CONFIG_SYS_FMAN_FW_ADDR		0x60900000
#define CONFIG_SYS_QE_FW_ADDR		0x60940000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
#endif

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#ifndef SPL_NO_MISC
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 0) \
	func(USB, usb, 0)
#include <config_distro_bootcmd.h>
#endif

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"fdt_high=0xffffffffffffffff\0"		\
	"initrd_high=0xffffffffffffffff\0"	\
	"fdt_addr=0x64f00000\0"		 	\
	"kernel_addr=0x61000000\0"		\
	"scriptaddr=0x80000000\0"		\
	"scripthdraddr=0x80080000\0"		\
	"fdtheader_addr_r=0x80100000\0"		\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"		\
	"fdt_addr_r=0x90000000\0"		\
	"load_addr=0xa0000000\0"		\
	"kernelheader_addr=0x60800000\0"	\
	"kernel_size=0x2800000\0"		\
	"kernelheader_size=0x40000\0"		\
	"kernel_addr_sd=0x8000\0"		\
	"kernel_size_sd=0x14000\0"		\
	"kernelhdr_addr_sd=0x4000\0"		\
	"kernelhdr_size_sd=0x10\0"		\
	"console=ttyS0,115200\0"		\
	"boot_os=y\0"				\
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"	\
	BOOTENV					\
	"boot_scripts=ls1043ardb_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1043ardb_bs.out\0"	\
	"scan_dev_for_boot_part="		\
		"part list ${devtype} ${devnum} devplist; "	\
		"env exists devplist || setenv devplist 1; "	\
		"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "			\
				"${devnum}:${distro_bootpart} "	\
				"bootfstype; then "		\
				"run scan_dev_for_boot; "	\
			"fi; "					\
		"done\0"			\
	"scan_dev_for_boot="					\
		"echo Scanning ${devtype} "			\
			"${devnum}:${distro_bootpart}...; "	\
		"for prefix in ${boot_prefixes}; do "		\
			"run scan_dev_for_scripts; "		\
		"done;\0"					\
	"boot_a_script="					\
		"load ${devtype} ${devnum}:${distro_bootpart} "	\
			"${scriptaddr} ${prefix}${script}; "	\
		"env exists secureboot && load ${devtype} "	\
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
			"&& esbc_validate ${scripthdraddr};"	\
		"source ${scriptaddr}\0"			\
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_addr $kernel_size; env exists secureboot "	\
		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"	\
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "	\
		"$kernel_size; env exists secureboot "	\
		"&& cp.b $kernelheader_addr $kernelheader_addr_r "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"	    \
	"sd_bootcmd=echo Trying load from SD ..;"       \
		"mmcinfo; mmc read $load_addr "         \
		"$kernel_addr_sd $kernel_size_sd && "     \
		"env exists secureboot && mmc read $kernelheader_addr_r "		\
		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$board\0"


#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
			   "env exists secureboot && esbc_halt;"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "  \
			   "env exists secureboot && esbc_halt;"
#else
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "	\
			   "env exists secureboot && esbc_halt;"
#endif
#endif

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */

#define CONFIG_SYS_MAXARGS		64	/* max command args */

#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */

#include <asm/arch/soc.h>

#endif /* __LS1043A_COMMON_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
f3a8e2b7 MH	2	/*
f3a8e2b7 MH	3	* Copyright (C) 2015 Freescale Semiconductor
f3a8e2b7 MH	4	*/
	5
	6	#ifndef __LS1043A_COMMON_H
	7	#define __LS1043A_COMMON_H
	8
4139b170 SG	9	/* SPL build */
	10	#ifdef CONFIG_SPL_BUILD
	11	#define SPL_NO_FMAN
	12	#define SPL_NO_DSPI
	13	#define SPL_NO_PCIE
	14	#define SPL_NO_ENV
	15	#define SPL_NO_MISC
	16	#define SPL_NO_USB
	17	#define SPL_NO_SATA
	18	#define SPL_NO_QE
	19	#define SPL_NO_EEPROM
	20	#endif
	21	#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
	22	#define SPL_NO_MMC
	23	#endif
3c7d647e	24	#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
4139b170 SG	25	#define SPL_NO_IFC
	26	#endif
	27
f3a8e2b7 MH	28	#define CONFIG_REMAKE_ELF
f3a8e2b7 MH	29	#define CONFIG_FSL_LAYERSCAPE
831c068f	30	#define CONFIG_MP
f3a8e2b7 MH	31	#define CONFIG_GICV2
f3a8e2b7 MH	32
5344c7b7	33	#include <asm/arch/stream_id_lsch2.h>
f3a8e2b7	34	#include <asm/arch/config.h>
f3a8e2b7 MH	35
	36	/* Link Definitions */
	37	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
	38
f3a8e2b7	39	#define CONFIG_SKIP_LOWLEVEL_INIT
f3a8e2b7	40
f3a8e2b7 MH	41	#define CONFIG_VERY_BIG_RAM
	42	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	43	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	44	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
e994dddb	45	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
f3a8e2b7	46
831c068f HZ	47	#define CPU_RELEASE_ADDR secondary_boot_func
831c068f HZ	48
f3a8e2b7 MH	49	/* Generic Timer Definitions */
	50	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
	51
	52	/* Size of malloc() pool */
	53	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
	54
	55	/* Serial Port */
f3a8e2b7 MH	56	#define CONFIG_SYS_NS16550_SERIAL
f3a8e2b7 MH	57	#define CONFIG_SYS_NS16550_REG_SIZE 1
904110c7	58	#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
f3a8e2b7	59
f3a8e2b7 MH	60	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
f3a8e2b7 MH	61
c7ca8b07 GQ	62	/* SD boot SPL */
c7ca8b07 GQ	63	#ifdef CONFIG_SD_BOOT
c7ca8b07	64	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
c7ca8b07 GQ	65
c7ca8b07 GQ	66	#define CONFIG_SPL_TEXT_BASE 0x10000000
70f9661c	67	#define CONFIG_SPL_MAX_SIZE 0x17000
c7ca8b07 GQ	68	#define CONFIG_SPL_STACK 0x1001e000
	69	#define CONFIG_SPL_PAD_TO 0x1d000
	70
23af484b YS	71	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
23af484b YS	72	CONFIG_SPL_BSS_MAX_SIZE)
c7ca8b07	73	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
23af484b	74	#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
c7ca8b07	75	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
70f9661c RG	76
	77	#ifdef CONFIG_SECURE_BOOT
	78	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
	79	/*
	80	* HDR would be appended at end of image and copied to DDR along
	81	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	82	* size increases then increase this size in case of secure boot as
	83	* it uses raw u-boot image instead of fit image.
	84	*/
	85	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
	86	#else
	87	#define CONFIG_SYS_MONITOR_LEN 0x100000
	88	#endif /* ifdef CONFIG_SECURE_BOOT */
c7ca8b07 GQ	89	#endif
c7ca8b07 GQ	90
3ad44729 GQ	91	/* NAND SPL */
	92	#ifdef CONFIG_NAND_BOOT
	93	#define CONFIG_SPL_PBL_PAD
3ad44729	94	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
3ad44729 GQ	95	#define CONFIG_SPL_TEXT_BASE 0x10000000
	96	#define CONFIG_SPL_MAX_SIZE 0x1a000
	97	#define CONFIG_SPL_STACK 0x1001d000
	98	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	99	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	100	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	101	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	102	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	103	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
762f92a6 RG	104
	105	#ifdef CONFIG_SECURE_BOOT
	106	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
	107	#endif /* ifdef CONFIG_SECURE_BOOT */
	108
	109	#ifdef CONFIG_U_BOOT_HDR_SIZE
	110	/*
	111	* HDR would be appended at end of image and copied to DDR along
	112	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	113	* size increases then increase this size in case of secure boot as
	114	* it uses raw u-boot image instead of fit image.
	115	*/
	116	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
	117	#else
	118	#define CONFIG_SYS_MONITOR_LEN 0x100000
	119	#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
	120
3ad44729 GQ	121	#endif
3ad44729 GQ	122
f3a8e2b7	123	/* IFC */
4139b170	124	#ifndef SPL_NO_IFC
b0f20caf	125	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
f3a8e2b7 MH	126	#define CONFIG_FSL_IFC
	127	/*
	128	* CONFIG_SYS_FLASH_BASE has the final address (core view)
	129	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
	130	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
	131	* CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
	132	*/
	133	#define CONFIG_SYS_FLASH_BASE 0x60000000
	134	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	135	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
	136
e856bdcf	137	#ifdef CONFIG_MTD_NOR_FLASH
f3a8e2b7 MH	138	#define CONFIG_FLASH_CFI_DRIVER
	139	#define CONFIG_SYS_FLASH_CFI
	140	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	141	#define CONFIG_SYS_FLASH_QUIET_TEST
	142	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	143	#endif
166ef1e9	144	#endif
4139b170	145	#endif
f3a8e2b7 MH	146
f3a8e2b7 MH	147	/* I2C */
f3a8e2b7	148	#define CONFIG_SYS_I2C
f3a8e2b7 MH	149
f3a8e2b7 MH	150	/* PCIe */
4139b170	151	#ifndef SPL_NO_PCIE
f3a8e2b7 MH	152	#define CONFIG_PCIE1 /* PCIE controller 1 */
	153	#define CONFIG_PCIE2 /* PCIE controller 2 */
	154	#define CONFIG_PCIE3 /* PCIE controller 3 */
f3a8e2b7	155
f3a8e2b7	156	#ifdef CONFIG_PCI
f3a8e2b7	157	#define CONFIG_PCI_SCAN_SHOW
f3a8e2b7	158	#endif
4139b170	159	#endif
f3a8e2b7 MH	160
f3a8e2b7 MH	161	/* Command line configuration */
f3a8e2b7	162
8ef0d5c4	163	/* MMC */
4139b170	164	#ifndef SPL_NO_MMC
8ef0d5c4	165	#ifdef CONFIG_MMC
8ef0d5c4	166	#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
8ef0d5c4	167	#endif
4139b170	168	#endif
8ef0d5c4	169
e0579a58	170	/* DSPI */
4139b170	171	#ifndef SPL_NO_DSPI
e0579a58 GQ	172	#define CONFIG_FSL_DSPI
e0579a58 GQ	173	#ifdef CONFIG_FSL_DSPI
e0579a58 GQ	174	#define CONFIG_DM_SPI_FLASH
	175	#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
	176	#define CONFIG_SPI_FLASH_SST /* cs1 */
	177	#define CONFIG_SPI_FLASH_EON /* cs2 */
b0f20caf	178	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
e0579a58 GQ	179	#define CONFIG_SF_DEFAULT_BUS 1
	180	#define CONFIG_SF_DEFAULT_CS 0
	181	#endif
166ef1e9	182	#endif
4139b170	183	#endif
e0579a58	184
e8297341	185	/* FMan ucode */
4139b170	186	#ifndef SPL_NO_FMAN
e8297341 SX	187	#define CONFIG_SYS_DPAA_FMAN
	188	#ifdef CONFIG_SYS_DPAA_FMAN
	189	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
	190
fd1b147c	191	#ifdef CONFIG_NAND_BOOT
a9a5cef3	192	/* Store Fman ucode at offeset 0x900000(72 blocks). */
fd1b147c	193	#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
a9a5cef3	194	#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
2a555839 QG	195	#elif defined(CONFIG_SD_BOOT)
	196	/*
	197	* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
	198	* about 1MB (2040 blocks), Env is stored after the image, and the env size is
a9a5cef3	199	* 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
2a555839 QG	200	*/
2a555839 QG	201	#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
a9a5cef3	202	#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
5aa03ddd	203	#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
2a555839	204	#elif defined(CONFIG_QSPI_BOOT)
166ef1e9	205	#define CONFIG_SYS_QE_FW_IN_SPIFLASH
a9a5cef3	206	#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
166ef1e9 GQ	207	#define CONFIG_ENV_SPI_BUS 0
	208	#define CONFIG_ENV_SPI_CS 0
	209	#define CONFIG_ENV_SPI_MAX_HZ 1000000
	210	#define CONFIG_ENV_SPI_MODE 0x03
	211	#else
e8297341 SX	212	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
e8297341 SX	213	/* FMan fireware Pre-load address */
a9a5cef3	214	#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
5aa03ddd	215	#define CONFIG_SYS_QE_FW_ADDR 0x60940000
166ef1e9	216	#endif
e8297341 SX	217	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
	218	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	219	#endif
4139b170	220	#endif
e8297341	221
f3a8e2b7 MH	222	/* Miscellaneous configurable options */
f3a8e2b7 MH	223	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
f3a8e2b7 MH	224
	225	#define CONFIG_HWCONFIG
	226	#define HWCONFIG_BUFFER_SIZE 128
	227
4139b170	228	#ifndef SPL_NO_MISC
5ba909f4 SL	229	#ifndef CONFIG_SPL_BUILD
	230	#define BOOT_TARGET_DEVICES(func) \
	231	func(MMC, mmc, 0) \
	232	func(USB, usb, 0)
	233	#include <config_distro_bootcmd.h>
	234	#endif
	235
f3a8e2b7 MH	236	/* Initial environment variables */
	237	#define CONFIG_EXTRA_ENV_SETTINGS \
	238	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
f3a8e2b7 MH	239	"fdt_high=0xffffffffffffffff\0" \
f3a8e2b7 MH	240	"initrd_high=0xffffffffffffffff\0" \
5ba909f4	241	"fdt_addr=0x64f00000\0" \
9b457cc6	242	"kernel_addr=0x61000000\0" \
5ba909f4	243	"scriptaddr=0x80000000\0" \
76bbf1c6	244	"scripthdraddr=0x80080000\0" \
5ba909f4 SL	245	"fdtheader_addr_r=0x80100000\0" \
	246	"kernelheader_addr_r=0x80200000\0" \
	247	"kernel_addr_r=0x81000000\0" \
	248	"fdt_addr_r=0x90000000\0" \
	249	"load_addr=0xa0000000\0" \
9b457cc6	250	"kernelheader_addr=0x60800000\0" \
ad6767b6	251	"kernel_size=0x2800000\0" \
9b457cc6	252	"kernelheader_size=0x40000\0" \
1c8263de SL	253	"kernel_addr_sd=0x8000\0" \
1c8263de SL	254	"kernel_size_sd=0x14000\0" \
9b457cc6 VPB	255	"kernelhdr_addr_sd=0x4000\0" \
9b457cc6 VPB	256	"kernelhdr_size_sd=0x10\0" \
5ba909f4	257	"console=ttyS0,115200\0" \
23af484b	258	"boot_os=y\0" \
43ede0bc	259	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
5ba909f4 SL	260	BOOTENV \
5ba909f4 SL	261	"boot_scripts=ls1043ardb_boot.scr\0" \
76bbf1c6	262	"boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
5ba909f4 SL	263	"scan_dev_for_boot_part=" \
	264	"part list ${devtype} ${devnum} devplist; " \
	265	"env exists devplist \|\| setenv devplist 1; " \
	266	"for distro_bootpart in ${devplist}; do " \
	267	"if fstype ${devtype} " \
	268	"${devnum}:${distro_bootpart} " \
	269	"bootfstype; then " \
	270	"run scan_dev_for_boot; " \
	271	"fi; " \
	272	"done\0" \
76bbf1c6 SG	273	"scan_dev_for_boot=" \
	274	"echo Scanning ${devtype} " \
	275	"${devnum}:${distro_bootpart}...; " \
	276	"for prefix in ${boot_prefixes}; do " \
	277	"run scan_dev_for_scripts; " \
	278	"done;\0" \
	279	"boot_a_script=" \
	280	"load ${devtype} ${devnum}:${distro_bootpart} " \
	281	"${scriptaddr} ${prefix}${script}; " \
	282	"env exists secureboot && load ${devtype} " \
	283	"${devnum}:${distro_bootpart} " \
	284	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	285	"&& esbc_validate ${scripthdraddr};" \
	286	"source ${scriptaddr}\0" \
5ba909f4 SL	287	"qspi_bootcmd=echo Trying load from qspi..;" \
5ba909f4 SL	288	"sf probe && sf read $load_addr " \
9b457cc6 VPB	289	"$kernel_addr $kernel_size; env exists secureboot " \
	290	"&& sf read $kernelheader_addr_r $kernelheader_addr " \
	291	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	292	"bootm $load_addr#$board\0" \
5ba909f4 SL	293	"nor_bootcmd=echo Trying load from nor..;" \
5ba909f4 SL	294	"cp.b $kernel_addr $load_addr " \
9b457cc6 VPB	295	"$kernel_size; env exists secureboot " \
	296	"&& cp.b $kernelheader_addr $kernelheader_addr_r " \
	297	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	298	"bootm $load_addr#$board\0" \
1c8263de SL	299	"sd_bootcmd=echo Trying load from SD ..;" \
	300	"mmcinfo; mmc read $load_addr " \
	301	"$kernel_addr_sd $kernel_size_sd && " \
9b457cc6 VPB	302	"env exists secureboot && mmc read $kernelheader_addr_r " \
	303	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	304	" && esbc_validate ${kernelheader_addr_r};" \
1c8263de SL	305	"bootm $load_addr#$board\0"
1c8263de SL	306
5ba909f4 SL	307
	308	#undef CONFIG_BOOTCOMMAND
	309	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
9b457cc6 VPB	310	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
9b457cc6 VPB	311	"env exists secureboot && esbc_halt;"
1c8263de	312	#elif defined(CONFIG_SD_BOOT)
9b457cc6 VPB	313	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
9b457cc6 VPB	314	"env exists secureboot && esbc_halt;"
5ba909f4	315	#else
9b457cc6 VPB	316	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
9b457cc6 VPB	317	"env exists secureboot && esbc_halt;"
5ba909f4	318	#endif
4139b170	319	#endif
f3a8e2b7 MH	320
	321	/* Monitor Command Prompt */
	322	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
4139b170	323
f3a8e2b7 MH	324	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	325
	326	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	327
457e51cf SG	328	#include <asm/arch/soc.h>
457e51cf SG	329
f3a8e2b7	330	#endif /* __LS1043A_COMMON_H */