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83d290c5 | 1 | # SPDX-License-Identifier: GPL-2.0+ |
f94c44e5 RC |
2 | # |
3 | # Copyright (C) 2017 Andes Technology Corporation. | |
4 | # Rick Chen, Andes Technology Corporation <[email protected]> | |
f94c44e5 | 5 | |
0c074845 LA |
6 | ifeq ($(CONFIG_ARCH_RV64I),y) |
7 | ARCH_BASE = rv64im | |
e67f34f7 | 8 | ABI_BASE = lp64 |
0c074845 LA |
9 | endif |
10 | ifeq ($(CONFIG_ARCH_RV32I),y) | |
11 | ARCH_BASE = rv32im | |
e67f34f7 | 12 | ABI_BASE = ilp32 |
0c074845 LA |
13 | endif |
14 | ifeq ($(CONFIG_RISCV_ISA_A),y) | |
15 | ARCH_A = a | |
16 | endif | |
e67f34f7 HS |
17 | ifeq ($(CONFIG_RISCV_ISA_F),y) |
18 | ARCH_F = f | |
19 | endif | |
20 | ifeq ($(CONFIG_RISCV_ISA_D),y) | |
21 | ARCH_D = d | |
22 | ABI_D = d | |
23 | endif | |
0c074845 LA |
24 | ifeq ($(CONFIG_RISCV_ISA_C),y) |
25 | ARCH_C = c | |
26 | endif | |
8176ea4d LA |
27 | ifeq ($(CONFIG_CMODEL_MEDLOW),y) |
28 | CMODEL = medlow | |
29 | endif | |
30 | ifeq ($(CONFIG_CMODEL_MEDANY),y) | |
31 | CMODEL = medany | |
32 | endif | |
0c074845 | 33 | |
e67f34f7 HS |
34 | |
35 | RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C) | |
36 | ABI = $(ABI_BASE)$(ABI_D) | |
1dde9775 AG |
37 | |
38 | # Newer binutils versions default to ISA spec version 20191213 which moves some | |
39 | # instructions from the I extension to the Zicsr and Zifencei extensions. | |
40 | toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei) | |
41 | ifeq ($(toolchain-need-zicsr-zifencei),y) | |
42 | RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei | |
43 | endif | |
44 | ||
45 | ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ | |
8176ea4d | 46 | -mcmodel=$(CMODEL) |
0c074845 LA |
47 | |
48 | PLATFORM_CPPFLAGS += $(ARCH_FLAGS) | |
49 | CFLAGS_EFI += $(ARCH_FLAGS) | |
50 | ||
b5369c58 | 51 | head-y := arch/riscv/cpu/start.o |
f94c44e5 | 52 | |
2fab2e9c | 53 | libs-y += arch/riscv/cpu/ |
f94c44e5 RC |
54 | libs-y += arch/riscv/cpu/$(CPU)/ |
55 | libs-y += arch/riscv/lib/ |