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riscv: support building double-float modules
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83d290c5 1# SPDX-License-Identifier: GPL-2.0+
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2#
3# Copyright (C) 2017 Andes Technology Corporation.
4# Rick Chen, Andes Technology Corporation <[email protected]>
f94c44e5 5
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6ifeq ($(CONFIG_ARCH_RV64I),y)
7 ARCH_BASE = rv64im
e67f34f7 8 ABI_BASE = lp64
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9endif
10ifeq ($(CONFIG_ARCH_RV32I),y)
11 ARCH_BASE = rv32im
e67f34f7 12 ABI_BASE = ilp32
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13endif
14ifeq ($(CONFIG_RISCV_ISA_A),y)
15 ARCH_A = a
16endif
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17ifeq ($(CONFIG_RISCV_ISA_F),y)
18 ARCH_F = f
19endif
20ifeq ($(CONFIG_RISCV_ISA_D),y)
21 ARCH_D = d
22 ABI_D = d
23endif
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24ifeq ($(CONFIG_RISCV_ISA_C),y)
25 ARCH_C = c
26endif
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27ifeq ($(CONFIG_CMODEL_MEDLOW),y)
28 CMODEL = medlow
29endif
30ifeq ($(CONFIG_CMODEL_MEDANY),y)
31 CMODEL = medany
32endif
0c074845 33
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34
35RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)
36ABI = $(ABI_BASE)$(ABI_D)
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37
38# Newer binutils versions default to ISA spec version 20191213 which moves some
39# instructions from the I extension to the Zicsr and Zifencei extensions.
40toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
41ifeq ($(toolchain-need-zicsr-zifencei),y)
42 RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
43endif
44
45ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
8176ea4d 46 -mcmodel=$(CMODEL)
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47
48PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
49CFLAGS_EFI += $(ARCH_FLAGS)
50
b5369c58 51head-y := arch/riscv/cpu/start.o
f94c44e5 52
2fab2e9c 53libs-y += arch/riscv/cpu/
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54libs-y += arch/riscv/cpu/$(CPU)/
55libs-y += arch/riscv/lib/
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