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7168da16 MY |
1 | U-Boot for UniPhier SoC family |
2 | ============================== | |
3 | ||
4 | ||
5 | Tested toolchains | |
6 | ----------------- | |
7 | ||
8 | (a) Ubuntu packages (CROSS_COMPILE=arm-linux-gnueabi-) | |
9 | ||
10 | If you are building U-Boot on Ubuntu, its standard package is recommended. | |
11 | You can install it as follows: | |
12 | ||
13 | $ sudo apt-get install gcc-arm-linux-gnueabi- | |
14 | ||
15 | (b) Linaro compilers (CROSS_COMPILE=arm-linux-gnueabihf-) | |
16 | ||
17 | You can download pre-built toolchains from: | |
18 | ||
19 | http://www.linaro.org/downloads/ | |
20 | ||
21 | (c) kernel.org compilers (CROSS_COMPILE=arm-unknown-linux-gnueabi-) | |
22 | ||
23 | You can download pre-built toolchains from: | |
24 | ||
25 | ftp://www.kernel.org/pub/tools/crosstool/files/bin/ | |
26 | ||
27 | ||
28 | Compile the source | |
29 | ------------------ | |
30 | ||
31 | PH1-Pro4: | |
32 | $ make ph1_pro4_defconfig | |
33 | $ make CROSS_COMPILE=arm-linux-gnueabi- | |
34 | ||
35 | PH1-LD4: | |
36 | $ make ph1_ld4_defconfig | |
37 | $ make CROSS_COMPILE=arm-linux-gnueabi- | |
38 | ||
39 | PH1-sLD8: | |
40 | $ make ph1_sld8_defconfig | |
41 | $ make CROSS_COMPILE=arm-linux-gnueabi- | |
42 | ||
43 | You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-" | |
44 | to use your favorite compiler. | |
45 | ||
46 | ||
47 | Burn U-Boot images to NAND | |
48 | -------------------------- | |
49 | ||
50 | Write two files to the NAND device as follows: | |
51 | - spl/u-boot-spl.bin at the offset address 0x00000000 | |
52 | - u-boot-dtb.img at the offset address 0x00010000 | |
53 | ||
54 | If a TFTP server is available, the images can be easily updated. | |
55 | Just copy the u-boot-spl.bin and u-boot-dtb.img to the TFTP public directory, | |
56 | and then run the following command at the U-Boot command line: | |
57 | ||
58 | => run nandupdate | |
59 | ||
60 | ||
61 | UniPhier specific commands | |
62 | -------------------------- | |
63 | ||
64 | - pinmon (enabled by CONFIG_CMD_PINMON) | |
65 | shows the boot mode pins that has been latched at the power-on reset | |
66 | ||
67 | - ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP) | |
68 | shows the DDR PHY parameters set by the PHY training | |
69 | ||
70 | ||
71 | Supported devices | |
72 | ----------------- | |
73 | ||
74 | - UART (on-chip) | |
75 | - NAND | |
1e7df7c4 MY |
76 | - USB 2.0 (EHCI) |
77 | - USB 3.0 (xHCI) | |
7168da16 MY |
78 | - LAN (on-board SMSC9118) |
79 | - I2C | |
80 | - EEPROM (connected to the on-board I2C bus) | |
81 | - Support card (SRAM, NOR flash, some peripherals) | |
82 | ||
83 | ||
84 | -- | |
85 | Masahiro Yamada <[email protected]> | |
86 | Feb. 2015 |