[J-u-boot.git] / include / configs / MPC8323ERDB.h

/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#undef DEBUG

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 family */
#define CONFIG_QE		1	/* Has QE */
#define CONFIG_MPC83XX		1	/* MPC83xx family */
#define CONFIG_MPC832X		1	/* MPC832x CPU specific */

#define CONFIG_PCI		1
#define CONFIG_83XX_GENERIC_PCI	1

/*
 * System Clock Setup
 */
#define CONFIG_83XX_CLKIN	66666667	/* in Hz */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
#endif

/*
 * Hardware Reset Configuration Word
 */
#define CFG_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_2X1 |\
	HRCWL_VCO_1X2 |\
	HRCWL_CSB_TO_CLKIN_2X1 |\
	HRCWL_CORE_TO_CSB_2_5X1 |\
	HRCWL_CE_PLL_VCO_DIV_2 |\
	HRCWL_CE_PLL_DIV_1X1 |\
	HRCWL_CE_TO_PLL_1X3)

#define CFG_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_BIG_ENDIAN |\
	HRCWH_LALE_NORMAL)

/*
 * System IO Config
 */
#define CFG_SICRL		0x00000000

#define CONFIG_BOARD_EARLY_INIT_F	/* call board_pre_init */

/*
 * IMMR new address
 */
#define CFG_IMMR		0xE0000000

/*
 * DDR Setup
 */
#define CFG_DDR_BASE		0x00000000	/* DDR is system memory */
#define CFG_SDRAM_BASE		CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
#define CFG_DDRCDR		0x73000002	/* DDR II voltage is 1.8V */

#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
/* Determine DDR configuration from I2C interface
 */
#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
#else
/* Manually set up DDR parameters
 */
#define CFG_DDR_SIZE		64	/* MB */
#define CFG_DDR_CS0_CONFIG	0x80840101
#define CFG_DDR_TIMING_0	0x00220802
#define CFG_DDR_TIMING_1	0x3935d322
#define CFG_DDR_TIMING_2	0x0f9048ca
#define CFG_DDR_TIMING_3	0x00000000
#define CFG_DDR_CLK_CNTL	0x02000000
#define CFG_DDR_MODE		0x44400232
#define CFG_DDR_MODE2		0x8000c000
#define CFG_DDR_INTERVAL	0x03200064
#define CFG_DDR_CS0_BNDS	0x00000003
#define CFG_DDR_SDRAM_CFG	0x43080000
#define CFG_DDR_SDRAM_CFG2	0x00401000
#endif

/*
 * Memory test
 */
#undef CFG_DRAM_TEST		/* memory test, takes time */
#define CFG_MEMTEST_START	0x00030000	/* memtest region */
#define CFG_MEMTEST_END		0x03f00000

/*
 * The reserved memory
 */
#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef  CFG_RAMBOOT
#endif

/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	0xE6000000	/* Initial RAM address */
#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM */
#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
#define CFG_LBC_LBCR		0x00000000

/*
 * FLASH on the Local Bus
 */
#define CFG_FLASH_CFI		/* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER	/* use the CFI driver */
#define CFG_FLASH_BASE		0xFE000000	/* FLASH base address */
#define CFG_FLASH_SIZE		16	/* FLASH size is 16M */

#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM	0x80000018	/* 32MB window size */

#define CFG_BR0_PRELIM	(CFG_FLASH_BASE |	/* Flash Base address */ \
			(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
			BR_V)			/* valid */
#define CFG_OR0_PRELIM		0xfe006ff7	/* 16MB Flash size */

#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
#define CFG_MAX_FLASH_SECT	128		/* sectors per device */

#undef CFG_FLASH_CHECKSUM

/*
 * SDRAM on the Local Bus
 */
#undef CFG_LB_SDRAM		/* The board has not SRDAM on local bus */

#ifdef CFG_LB_SDRAM
#define CFG_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

#define CFG_LBLAWBAR2_PRELIM	CFG_LBC_SDRAM_BASE
#define CFG_LBLAWAR2_PRELIM	0x80000019	/* 64MB */

/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 * the top 17 bits of BR2.
 */

#define CFG_BR2_PRELIM	0xf0001861	/*Port size=32bit, MSEL=SDRAM */

/*
 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *                 XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CFG_OR2_PRELIM	0xfc006901

#define CFG_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
#define CFG_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */

/*
 * LSDMR masks
 */
#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))

#define CFG_LBC_LSDMR_COMMON	0x0063b723

/*
 * SDRAM Controller configuration sequence.
 */
#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_PCHALL)
#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_NORMAL)

#endif

/*
 * Windows to access PIB via local bus
 */
#define CFG_LBLAWBAR3_PRELIM	0xf8008000	/* windows base 0xf8008000 */
#define CFG_LBLAWAR3_PRELIM	0x8000000f	/* windows size 64KB */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,8323@0"
#define OF_SOC			"soc8323@e0000000"
#define OF_QE			"qe@e0100000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc8323@e0000000/serial@4500"

/* I2C */
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
#define CONFIG_FSL_I2C
#define CFG_I2C_SPEED	400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE	0x7F
#define CFG_I2C_NOPROBES	{0x51}	/* Don't probe these addrs */
#define CFG_I2C_OFFSET	0x3000

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68 */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CFG_PCI1_MMIO_BASE	0x90000000
#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CFG_PCI1_IO_BASE		0xd0000000
#define CFG_PCI1_IO_PHYS		CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE		0x04000000	/* 64M */

#ifdef CONFIG_PCI

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP		/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */

#endif	/* CONFIG_PCI */


#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME		"Freescale GETH"

#define CONFIG_UEC_ETH1		/* ETH3 */

#ifdef CONFIG_UEC_ETH1
#define CFG_UEC1_UCC_NUM	2	/* UCC3 */
#define CFG_UEC1_RX_CLK		QE_CLK9
#define CFG_UEC1_TX_CLK		QE_CLK10
#define CFG_UEC1_ETH_TYPE	FAST_ETH
#define CFG_UEC1_PHY_ADDR	4
#define CFG_UEC1_INTERFACE_MODE	ENET_100_MII
#endif

#define CONFIG_UEC_ETH2		/* ETH4 */

#ifdef CONFIG_UEC_ETH2
#define CFG_UEC2_UCC_NUM	1	/* UCC2 */
#define CFG_UEC2_RX_CLK		QE_CLK16
#define CFG_UEC2_TX_CLK		QE_CLK3
#define CFG_UEC2_ETH_TYPE	FAST_ETH
#define CFG_UEC2_PHY_ADDR	0
#define CFG_UEC2_INTERFACE_MODE	ENET_100_MII
#endif

/*
 * Environment
 */
#ifndef CFG_RAMBOOT
	#define CFG_ENV_IS_IN_FLASH	1
	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
	#define CFG_ENV_SECT_SIZE	0x20000
	#define CFG_ENV_SIZE		0x2000
#else
	#define CFG_NO_FLASH		1	/* Flash is not usable now */
	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
	#define CFG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ASKENV

#if defined(CONFIG_PCI)
	#define CONFIG_CMD_PCI
#endif
#if defined(CFG_RAMBOOT)
	#undef CONFIG_CMD_ENV
	#undef CONFIG_CMD_LOADS
#endif

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP		/* undef to save memory */
#define CFG_LOAD_ADDR		0x2000000	/* default load address */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */

#if (CONFIG_CMD_KGDB)
	#define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
#else
	#define CFG_CBSIZE	256	/* Console I/O Buffer Size */
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Core HID Setup
 */
#define CFG_HID0_INIT		0x000000000
#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
#define CFG_HID2		HID2_HBE

/*
 * Cache Config
 */
#define CFG_DCACHE_SIZE		16384
#define CFG_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value */
#endif

/*
 * MMU Setup
 */

/* DDR: cache cacheable */
#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L	CFG_IBAT0L
#define CFG_DBAT0U	CFG_IBAT0U

/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT1U	(CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
#define CFG_DBAT1L	CFG_IBAT1L
#define CFG_DBAT1U	CFG_IBAT1U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CFG_IBAT2L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT2U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
#define CFG_DBAT2L	(CFG_FLASH_BASE | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT2U	CFG_IBAT2U

#define CFG_IBAT3L	(0)
#define CFG_IBAT3U	(0)
#define CFG_DBAT3L	CFG_IBAT3L
#define CFG_DBAT3U	CFG_IBAT3U

/* Stack in dcache: cacheable, no memory coherence */
#define CFG_IBAT4L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
#define CFG_IBAT4U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CFG_DBAT4L	CFG_IBAT4L
#define CFG_DBAT4U	CFG_IBAT4U

#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CFG_IBAT5L	(CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT5U	(CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT5L	CFG_IBAT5L
#define CFG_DBAT5U	CFG_IBAT5U
/* PCI MMIO space: cache-inhibit and guarded */
#define CFG_IBAT6L	(CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT6U	(CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT6L	CFG_IBAT6L
#define CFG_DBAT6U	CFG_IBAT6U
#else
#define CFG_IBAT5L	(0)
#define CFG_IBAT5U	(0)
#define CFG_IBAT6L	(0)
#define CFG_IBAT6U	(0)
#define CFG_DBAT5L	CFG_IBAT5L
#define CFG_DBAT5U	CFG_IBAT5U
#define CFG_DBAT6L	CFG_IBAT6L
#define CFG_DBAT6U	CFG_IBAT6U
#endif

/* Nothing in BAT7 */
#define CFG_IBAT7L	(0)
#define CFG_IBAT7U	(0)
#define CFG_DBAT7L	CFG_IBAT7L
#define CFG_DBAT7U	CFG_IBAT7U

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02	/* Software reboot */

#if (CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_ETHADDR	00:04:9f:ef:03:01
#define CONFIG_HAS_ETH1				/* add support for "eth1addr" */
#define CONFIG_ETH1ADDR	00:04:9f:ef:03:02

#define CONFIG_IPADDR		10.0.0.2
#define CONFIG_SERVERIP		10.0.0.1
#define CONFIG_GATEWAYIP	10.0.0.1
#define CONFIG_NETMASK		255.0.0.0
#define CONFIG_NETDEV		eth1

#define CONFIG_HOSTNAME		mpc8323erdb
#define CONFIG_ROOTPATH		/nfsroot
#define CONFIG_RAMDISKFILE	rootfs.ext2.gz.uboot
#define CONFIG_BOOTFILE		uImage
#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
#define CONFIG_FDTFILE		mpc832x_rdb.dtb

#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
#define CONFIG_BAUDRATE		115200

#define XMK_STR(x)	#x
#define MK_STR(x)	XMK_STR(x)

#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
	"tftpflash=tftp $loadaddr $uboot;"				\
		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
	"fdtaddr=400000\0"						\
	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0"			\
	"console=ttyS0\0"						\
	"setbootargs=setenv bootargs "					\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv rootdev /dev/nfs;"					\
	"run setbootargs;"						\
	"run setipargs;"						\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv rootdev /dev/ram;"					\
	"run setbootargs;"						\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#undef MK_STR
#undef XMK_STR

#endif	/* __CONFIG_H */
Commit	Line	Data
1c274c4e KP	1	/*
	2	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License version 2 as published
	6	* by the Free Software Foundation.
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	#undef DEBUG
	13
	14	/*
	15	* High Level Configuration Options
	16	*/
	17	#define CONFIG_E300 1 /* E300 family */
	18	#define CONFIG_QE 1 /* Has QE */
	19	#define CONFIG_MPC83XX 1 /* MPC83xx family */
	20	#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
	21
	22	#define CONFIG_PCI 1
	23	#define CONFIG_83XX_GENERIC_PCI 1
	24
	25	/*
	26	* System Clock Setup
	27	*/
	28	#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
	29
	30	#ifndef CONFIG_SYS_CLK_FREQ
	31	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
	32	#endif
	33
	34	/*
	35	* Hardware Reset Configuration Word
	36	*/
	37	#define CFG_HRCW_LOW (\
	38	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	39	HRCWL_DDR_TO_SCB_CLK_2X1 \|\
	40	HRCWL_VCO_1X2 \|\
	41	HRCWL_CSB_TO_CLKIN_2X1 \|\
	42	HRCWL_CORE_TO_CSB_2_5X1 \|\
	43	HRCWL_CE_PLL_VCO_DIV_2 \|\
	44	HRCWL_CE_PLL_DIV_1X1 \|\
	45	HRCWL_CE_TO_PLL_1X3)
	46
	47	#define CFG_HRCW_HIGH (\
	48	HRCWH_PCI_HOST \|\
	49	HRCWH_PCI1_ARBITER_ENABLE \|\
	50	HRCWH_CORE_ENABLE \|\
	51	HRCWH_FROM_0X00000100 \|\
	52	HRCWH_BOOTSEQ_DISABLE \|\
	53	HRCWH_SW_WATCHDOG_DISABLE \|\
	54	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	55	HRCWH_BIG_ENDIAN \|\
	56	HRCWH_LALE_NORMAL)
	57
	58	/*
	59	* System IO Config
	60	*/
	61	#define CFG_SICRL 0x00000000
	62
	63	#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
	64
65	/*
66	* IMMR new address
67	*/
68	#define CFG_IMMR 0xE0000000
69
70	/*
71	* DDR Setup
72	*/
73	#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
74	#define CFG_SDRAM_BASE CFG_DDR_BASE
75	#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
76	#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
77
78	#undef CONFIG_SPD_EEPROM
79	#if defined(CONFIG_SPD_EEPROM)
80	/* Determine DDR configuration from I2C interface
81	*/
82	#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
83	#else
84	/* Manually set up DDR parameters
85	*/
86	#define CFG_DDR_SIZE 64 /* MB */
87	#define CFG_DDR_CS0_CONFIG 0x80840101
88	#define CFG_DDR_TIMING_0 0x00220802
89	#define CFG_DDR_TIMING_1 0x3935d322
90	#define CFG_DDR_TIMING_2 0x0f9048ca
91	#define CFG_DDR_TIMING_3 0x00000000
92	#define CFG_DDR_CLK_CNTL 0x02000000
93	#define CFG_DDR_MODE 0x44400232
94	#define CFG_DDR_MODE2 0x8000c000
95	#define CFG_DDR_INTERVAL 0x03200064
96	#define CFG_DDR_CS0_BNDS 0x00000003
97	#define CFG_DDR_SDRAM_CFG 0x43080000
98	#define CFG_DDR_SDRAM_CFG2 0x00401000
99	#endif
100
101	/*
102	* Memory test
103	*/
104	#undef CFG_DRAM_TEST /* memory test, takes time */
105	#define CFG_MEMTEST_START 0x00030000 /* memtest region */
106	#define CFG_MEMTEST_END 0x03f00000
107
108	/*
109	* The reserved memory
110	*/
111	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
112
113	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
114	#define CFG_RAMBOOT
115	#else
116	#undef CFG_RAMBOOT
117	#endif
118
b2893e1f	119	/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
1c274c4e KP	120	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
	121	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
	122
	123	/*
	124	* Initial RAM Base Address Setup
	125	*/
	126	#define CFG_INIT_RAM_LOCK 1
	127	#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
	128	#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
	129	#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
	130	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	131
	132	/*
	133	* Local Bus Configuration & Clock Setup
	134	*/
	135	#define CFG_LCRR (LCRR_DBYP \| LCRR_CLKDIV_2)
	136	#define CFG_LBC_LBCR 0x00000000
	137
	138	/*
	139	* FLASH on the Local Bus
	140	*/
	141	#define CFG_FLASH_CFI /* use the Common Flash Interface */
	142	#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
	143	#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
	144	#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
	145
	146	#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
	147	#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
	148
	149	#define CFG_BR0_PRELIM (CFG_FLASH_BASE \| /* Flash Base address */ \
	150	(2 << BR_PS_SHIFT) \| /* 16 bit port size */ \
	151	BR_V) /* valid */
	152	#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
	153
	154	#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
	155	#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
	156
	157	#undef CFG_FLASH_CHECKSUM
	158
	159	/*
	160	* SDRAM on the Local Bus
	161	*/
	162	#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */
	163
	164	#ifdef CFG_LB_SDRAM
	165	#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
	166	#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
	167
	168	#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
	169	#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
	170
	171	/local bus BR2, OR2 definition for SDRAM if soldered on the EPB board /
	172	/*
	173	* Base Register 2 and Option Register 2 configure SDRAM.
	174	* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
	175	*
	176	* For BR2, need:
	177	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	178	* port size = 32-bits = BR2[19:20] = 11
	179	* no parity checking = BR2[21:22] = 00
	180	* SDRAM for MSEL = BR2[24:26] = 011
	181	* Valid = BR[31] = 1
	182	*
	183	* 0 4 8 12 16 20 24 28
184	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
185	*
186	* CFG_LBC_SDRAM_BASE should be masked and OR'ed into
187	* the top 17 bits of BR2.
188	*/
189
190	#define CFG_BR2_PRELIM 0xf0001861 /Port size=32bit, MSEL=SDRAM /
191
192	/*
193	* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
194	*
195	* For OR2, need:
196	* 64MB mask for AM, OR2[0:7] = 1111 1100
197	* XAM, OR2[17:18] = 11
198	* 9 columns OR2[19-21] = 010
199	* 13 rows OR2[23-25] = 100
200	* EAD set for extra time OR[31] = 1
201	*
202	* 0 4 8 12 16 20 24 28
203	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
204	*/
205
206	#define CFG_OR2_PRELIM 0xfc006901
207
208	#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
209	#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
210
211	/*
212	* LSDMR masks
213	*/
214	#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
215	#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
216	#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
217	#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
218	#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
219	#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
220	#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
221	#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
222
223	#define CFG_LBC_LSDMR_COMMON 0x0063b723
224
225	/*
226	* SDRAM Controller configuration sequence.
227	*/
228	#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
229	\| CFG_LBC_LSDMR_OP_PCHALL)
230	#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
231	\| CFG_LBC_LSDMR_OP_ARFRSH)
232	#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
233	\| CFG_LBC_LSDMR_OP_ARFRSH)
234	#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
235	\| CFG_LBC_LSDMR_OP_MRW)
236	#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
237	\| CFG_LBC_LSDMR_OP_NORMAL)
238
239	#endif
240
241	/*
242	* Windows to access PIB via local bus
243	*/
244	#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
245	#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
246
247	/*
248	* Serial Port
249	*/
250	#define CONFIG_CONS_INDEX 1
251	#undef CONFIG_SERIAL_SOFTWARE_FIFO
252	#define CFG_NS16550
253	#define CFG_NS16550_SERIAL
254	#define CFG_NS16550_REG_SIZE 1
255	#define CFG_NS16550_CLK get_bus_freq(0)
256
257	#define CFG_BAUDRATE_TABLE \
258	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
259
260	#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
261	#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
262
263	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
264	/* Use the HUSH parser */
265	#define CFG_HUSH_PARSER
266	#ifdef CFG_HUSH_PARSER
267	#define CFG_PROMPT_HUSH_PS2 "> "
268	#endif
269
270	/* pass open firmware flat tree */
271	#define CONFIG_OF_LIBFDT 1
272	#define CONFIG_OF_BOARD_SETUP 1
273
274	#define OF_CPU "PowerPC,8323@0"
275	#define OF_SOC "soc8323@e0000000"
276	#define OF_QE "qe@e0100000"
277	#define OF_TBCLK (bd->bi_busfreq / 4)
278	#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500"
279
280	/* I2C */
281	#define CONFIG_HARD_I2C /* I2C with hardware support */
282	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
283	#define CONFIG_FSL_I2C
284	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
285	#define CFG_I2C_SLAVE 0x7F
286	#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
287	#define CFG_I2C_OFFSET 0x3000
288
289	/*
290	* Config on-board RTC
291	*/
292	#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
293	#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
294
295	/*
296	* General PCI
297	* Addresses are mapped 1-1.
298	*/
299	#define CFG_PCI1_MEM_BASE 0x80000000
300	#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
301	#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
302	#define CFG_PCI1_MMIO_BASE 0x90000000
303	#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
304	#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
305	#define CFG_PCI1_IO_BASE 0xd0000000
306	#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
307	#define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */
308
309	#ifdef CONFIG_PCI
310
311	#define CONFIG_NET_MULTI
312	#define CONFIG_PCI_PNP /* do pci plug-and-play */
313
314	#undef CONFIG_EEPRO100
315	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
316	#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
317
318	#endif /* CONFIG_PCI */
319
320
321	#ifndef CONFIG_NET_MULTI
322	#define CONFIG_NET_MULTI 1
323	#endif
324
325	/*
326	* QE UEC ethernet configuration
327	*/
328	#define CONFIG_UEC_ETH
329	#define CONFIG_ETHPRIME "Freescale GETH"
330
331	#define CONFIG_UEC_ETH1 /* ETH3 */
332
333	#ifdef CONFIG_UEC_ETH1
334	#define CFG_UEC1_UCC_NUM 2 /* UCC3 */
335	#define CFG_UEC1_RX_CLK QE_CLK9
336	#define CFG_UEC1_TX_CLK QE_CLK10
337	#define CFG_UEC1_ETH_TYPE FAST_ETH
338	#define CFG_UEC1_PHY_ADDR 4
339	#define CFG_UEC1_INTERFACE_MODE ENET_100_MII
340	#endif
341
342	#define CONFIG_UEC_ETH2 /* ETH4 */
343
344	#ifdef CONFIG_UEC_ETH2
345	#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
346	#define CFG_UEC2_RX_CLK QE_CLK16
347	#define CFG_UEC2_TX_CLK QE_CLK3
348	#define CFG_UEC2_ETH_TYPE FAST_ETH
349	#define CFG_UEC2_PHY_ADDR 0
350	#define CFG_UEC2_INTERFACE_MODE ENET_100_MII
351	#endif
352
353	/*
354	* Environment
355	*/
356	#ifndef CFG_RAMBOOT
357	#define CFG_ENV_IS_IN_FLASH 1
b2893e1f TT	358	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
b2893e1f TT	359	#define CFG_ENV_SECT_SIZE 0x20000
1c274c4e KP	360	#define CFG_ENV_SIZE 0x2000
	361	#else
	362	#define CFG_NO_FLASH 1 /* Flash is not usable now */
	363	#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
	364	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
	365	#define CFG_ENV_SIZE 0x2000
	366	#endif
	367
	368	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	369	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	370
	371	/*
	372	* BOOTP options
	373	*/
	374	#define CONFIG_BOOTP_BOOTFILESIZE
	375	#define CONFIG_BOOTP_BOOTPATH
	376	#define CONFIG_BOOTP_GATEWAY
	377	#define CONFIG_BOOTP_HOSTNAME
	378
	379	/*
	380	* Command line configuration.
	381	*/
	382	#include <config_cmd_default.h>
	383
	384	#define CONFIG_CMD_PING
	385	#define CONFIG_CMD_I2C
	386	#define CONFIG_CMD_ASKENV
	387
	388	#if defined(CONFIG_PCI)
	389	#define CONFIG_CMD_PCI
	390	#endif
	391	#if defined(CFG_RAMBOOT)
	392	#undef CONFIG_CMD_ENV
	393	#undef CONFIG_CMD_LOADS
	394	#endif
	395
	396	#undef CONFIG_WATCHDOG /* watchdog disabled */
	397
	398	/*
	399	* Miscellaneous configurable options
	400	*/
	401	#define CFG_LONGHELP /* undef to save memory */
	402	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
	403	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	404
	405	#if (CONFIG_CMD_KGDB)
	406	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	407	#else
	408	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	409	#endif
	410
	411	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	412	#define CFG_MAXARGS 16 /* max number of command args */
	413	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	414	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
	415
	416	/*
	417	* For booting Linux, the board info and command line data
	418	* have to be in the first 8 MB of memory, since this is
	419	* the maximum mapped by the Linux kernel during initialization.
	420	*/
	421	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	422
	423	/*
424	* Core HID Setup
425	*/
426	#define CFG_HID0_INIT 0x000000000
427	#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
428	#define CFG_HID2 HID2_HBE
429
430	/*
431	* Cache Config
432	*/
433	#define CFG_DCACHE_SIZE 16384
434	#define CFG_CACHELINE_SIZE 32
435	#if defined(CONFIG_CMD_KGDB)
436	#define CFG_CACHELINE_SHIFT 5 /log base 2 of the above value /
437	#endif
438
439	/*
440	* MMU Setup
441	*/
442
443	/* DDR: cache cacheable */
444	#define CFG_IBAT0L (CFG_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
445	#define CFG_IBAT0U (CFG_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
446	#define CFG_DBAT0L CFG_IBAT0L
447	#define CFG_DBAT0U CFG_IBAT0U
448
449	/* IMMRBAR & PCI IO: cache-inhibit and guarded */
450	#define CFG_IBAT1L (CFG_IMMR \| BATL_PP_10 \| \
451	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
452	#define CFG_IBAT1U (CFG_IMMR \| BATU_BL_4M \| BATU_VS \| BATU_VP)
453	#define CFG_DBAT1L CFG_IBAT1L
454	#define CFG_DBAT1U CFG_IBAT1U
455
456	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
457	#define CFG_IBAT2L (CFG_FLASH_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
458	#define CFG_IBAT2U (CFG_FLASH_BASE \| BATU_BL_32M \| BATU_VS \| BATU_VP)
459	#define CFG_DBAT2L (CFG_FLASH_BASE \| BATL_PP_10 \| \
460	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
461	#define CFG_DBAT2U CFG_IBAT2U
462
463	#define CFG_IBAT3L (0)
464	#define CFG_IBAT3U (0)
465	#define CFG_DBAT3L CFG_IBAT3L
466	#define CFG_DBAT3U CFG_IBAT3U
467
468	/* Stack in dcache: cacheable, no memory coherence */
469	#define CFG_IBAT4L (CFG_INIT_RAM_ADDR \| BATL_PP_10)
470	#define CFG_IBAT4U (CFG_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
471	#define CFG_DBAT4L CFG_IBAT4L
472	#define CFG_DBAT4U CFG_IBAT4U
473
474	#ifdef CONFIG_PCI
475	/* PCI MEM space: cacheable */
476	#define CFG_IBAT5L (CFG_PCI1_MEM_PHYS \| BATL_PP_10 \| BATL_MEMCOHERENCE)
477	#define CFG_IBAT5U (CFG_PCI1_MEM_PHYS \| BATU_BL_256M \| BATU_VS \| BATU_VP)
478	#define CFG_DBAT5L CFG_IBAT5L
479	#define CFG_DBAT5U CFG_IBAT5U
480	/* PCI MMIO space: cache-inhibit and guarded */
481	#define CFG_IBAT6L (CFG_PCI1_MMIO_PHYS \| BATL_PP_10 \| \
482	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
483	#define CFG_IBAT6U (CFG_PCI1_MMIO_PHYS \| BATU_BL_256M \| BATU_VS \| BATU_VP)
484	#define CFG_DBAT6L CFG_IBAT6L
485	#define CFG_DBAT6U CFG_IBAT6U
486	#else
487	#define CFG_IBAT5L (0)
488	#define CFG_IBAT5U (0)
489	#define CFG_IBAT6L (0)
490	#define CFG_IBAT6U (0)
491	#define CFG_DBAT5L CFG_IBAT5L
492	#define CFG_DBAT5U CFG_IBAT5U
493	#define CFG_DBAT6L CFG_IBAT6L
494	#define CFG_DBAT6U CFG_IBAT6U
495	#endif
496
497	/* Nothing in BAT7 */
498	#define CFG_IBAT7L (0)
499	#define CFG_IBAT7U (0)
500	#define CFG_DBAT7L CFG_IBAT7L
501	#define CFG_DBAT7U CFG_IBAT7U
502
503	/*
504	* Internal Definitions
505	*
506	* Boot Flags
507	*/
508	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
509	#define BOOTFLAG_WARM 0x02 /* Software reboot */
510
511	#if (CONFIG_CMD_KGDB)
512	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
513	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
514	#endif
515
516	/*
517	* Environment Configuration
518	*/
519	#define CONFIG_ENV_OVERWRITE
520
521	#define CONFIG_ETHADDR 00:04:9f:ef:03:01
522	#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
523	#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
524
525	#define CONFIG_IPADDR 10.0.0.2
526	#define CONFIG_SERVERIP 10.0.0.1
527	#define CONFIG_GATEWAYIP 10.0.0.1
528	#define CONFIG_NETMASK 255.0.0.0
529	#define CONFIG_NETDEV eth1
530
531	#define CONFIG_HOSTNAME mpc8323erdb
532	#define CONFIG_ROOTPATH /nfsroot
533	#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
534	#define CONFIG_BOOTFILE uImage
535	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
536	#define CONFIG_FDTFILE mpc832x_rdb.dtb
537
538	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
539	#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
540	#define CONFIG_BAUDRATE 115200
541
542	#define XMK_STR(x) #x
543	#define MK_STR(x) XMK_STR(x)
544
545	#define CONFIG_EXTRA_ENV_SETTINGS \
546	"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
547	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
548	"tftpflash=tftp $loadaddr $uboot;" \
549	"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
550	"erase " MK_STR(TEXT_BASE) " +$filesize; " \
551	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
552	"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
553	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
554	"fdtaddr=400000\0" \
555	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
556	"ramdiskaddr=1000000\0" \
557	"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
558	"console=ttyS0\0" \
559	"setbootargs=setenv bootargs " \
560	"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
561	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
562	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
563	"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
564
565	#define CONFIG_NFSBOOTCOMMAND \
566	"setenv rootdev /dev/nfs;" \
567	"run setbootargs;" \
568	"run setipargs;" \
569	"tftp $loadaddr $bootfile;" \
570	"tftp $fdtaddr $fdtfile;" \
571	"bootm $loadaddr - $fdtaddr"
572
573	#define CONFIG_RAMBOOTCOMMAND \
574	"setenv rootdev /dev/ram;" \
575	"run setbootargs;" \
576	"tftp $ramdiskaddr $ramdiskfile;" \
577	"tftp $loadaddr $bootfile;" \
578	"tftp $fdtaddr $fdtfile;" \
579	"bootm $loadaddr $ramdiskaddr $fdtaddr"
580
581	#undef MK_STR
582	#undef XMK_STR
583
584	#endif /* __CONFIG_H */