[J-u-boot.git] / board / a3m071 / is46r16320d.h

/*
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#define SDRAM_DDR		/* is DDR */

#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */

/* SDRAM Config Standard timing */
#define SDRAM_MODE	0x008d0000
#define SDRAM_EMODE	0x40010000
#define SDRAM_CONTROL	0x70430f00
#define SDRAM_CONFIG1	0x33622930
#define SDRAM_CONFIG2	0x46670000
#define SDRAM_TAPDELAY	0x10000000

#else
#error CONFIG_MPC5200 not defined
#endif
Commit	Line	Data
d4451d35 SR	1	/*
	2	* (C) Copyright 2004
	3	* Mark Jonas, Freescale Semiconductor, [email protected].
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
d4451d35 SR	6	*/
	7
	8	#define SDRAM_DDR /* is DDR */
	9
	10	#if defined(CONFIG_MPC5200)
	11	/* Settings for XLB = 132 MHz */
	12	/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */
	13
	14	/* SDRAM Config Standard timing */
	15	#define SDRAM_MODE 0x008d0000
	16	#define SDRAM_EMODE 0x40010000
	17	#define SDRAM_CONTROL 0x70430f00
	18	#define SDRAM_CONFIG1 0x33622930
	19	#define SDRAM_CONFIG2 0x46670000
	20	#define SDRAM_TAPDELAY 0x10000000
	21
	22	#else
	23	#error CONFIG_MPC5200 not defined
	24	#endif