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The patch introduces the CRITICAL feature of POST tests. If the test
[J-u-boot.git] / include / asm-m68k / immap_5445x.h
CommitLineData
8ae158cd
TL		 1/*
2 * MCF5445x Internal Memory Map
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew ([email protected])
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __IMMAP_5445X__
27#define __IMMAP_5445X__
28
29/* Module Base Addresses */
30#define MMAP_SCM1 0xFC000000
31#define MMAP_XBS 0xFC004000
32#define MMAP_FBCS 0xFC008000
33#define MMAP_FEC0 0xFC030000
34#define MMAP_FEC1 0xFC034000
35#define MMAP_RTC 0xFC03C000
d2b16493 36#define MMAP_SCM2 0xFC040000
8ae158cd
TL		 37#define MMAP_EDMA 0xFC044000
38#define MMAP_INTC0 0xFC048000
39#define MMAP_INTC1 0xFC04C000
40#define MMAP_IACK 0xFC054000
41#define MMAP_I2C 0xFC058000
42#define MMAP_DSPI 0xFC05C000
43#define MMAP_UART0 0xFC060000
44#define MMAP_UART1 0xFC064000
45#define MMAP_UART2 0xFC068000
46#define MMAP_DTMR0 0xFC070000
47#define MMAP_DTMR1 0xFC074000
48#define MMAP_DTMR2 0xFC078000
49#define MMAP_DTMR3 0xFC07C000
50#define MMAP_PIT0 0xFC080000
51#define MMAP_PIT1 0xFC084000
52#define MMAP_PIT2 0xFC088000
53#define MMAP_PIT3 0xFC08C000
54#define MMAP_EPORT 0xFC094000
55#define MMAP_WTM 0xFC098000
56#define MMAP_SBF 0xFC0A0000
57#define MMAP_RCM 0xFC0A0000
58#define MMAP_CCM 0xFC0A0000
59#define MMAP_GPIO 0xFC0A4000
60#define MMAP_PCI 0xFC0A8000
61#define MMAP_PCIARB 0xFC0AC000
62#define MMAP_RNG 0xFC0B4000
63#define MMAP_SDRAM 0xFC0B8000
64#define MMAP_SSI 0xFC0BC000
65#define MMAP_PLL 0xFC0C4000
66#define MMAP_ATA 0x90000000
d2b16493
TL		 67#define MMAP_USBHW 0xFC0B0000
68#define MMAP_USBCAPS 0xFC0B0100
69#define MMAP_USBEHCI 0xFC0B0140
70#define MMAP_USBOTG 0xFC0B01A0
71
72#include <asm/coldfire/crossbar.h>
73#include <asm/coldfire/dspi.h>
74#include <asm/coldfire/edma.h>
75#include <asm/coldfire/flexbus.h>
76#include <asm/coldfire/ssi.h>
77
78/* ATA */
8ae158cd
TL		 79typedef struct atac {
80 /* PIO */
81 u8 toff; /* 0x00 */
82 u8 ton; /* 0x01 */
83 u8 t1; /* 0x02 */
84 u8 t2w; /* 0x03 */
85 u8 t2r; /* 0x04 */
86 u8 ta; /* 0x05 */
87 u8 trd; /* 0x06 */
88 u8 t4; /* 0x07 */
89 u8 t9; /* 0x08 */
90
91 /* DMA */
92 u8 tm; /* 0x09 */
93 u8 tn; /* 0x0A */
94 u8 td; /* 0x0B */
95 u8 tk; /* 0x0C */
96 u8 tack; /* 0x0D */
97 u8 tenv; /* 0x0E */
98 u8 trp; /* 0x0F */
99 u8 tzah; /* 0x10 */
100 u8 tmli; /* 0x11 */
101 u8 tdvh; /* 0x12 */
102 u8 tdzfs; /* 0x13 */
103 u8 tdvs; /* 0x14 */
104 u8 tcvh; /* 0x15 */
105 u8 tss; /* 0x16 */
106 u8 tcyc; /* 0x17 */
107
108 /* FIFO */
109 u32 fifo32; /* 0x18 */
110 u16 fifo16; /* 0x1C */
111 u8 rsvd0[2];
112 u8 ffill; /* 0x20 */
113 u8 rsvd1[3];
114
115 /* ATA */
116 u8 cr; /* 0x24 */
117 u8 rsvd2[3];
118 u8 isr; /* 0x28 */
119 u8 rsvd3[3];
120 u8 ier; /* 0x2C */
121 u8 rsvd4[3];
122 u8 icr; /* 0x30 */
123 u8 rsvd5[3];
124 u8 falarm; /* 0x34 */
125 u8 rsvd6[106];
126} atac_t;
127
d2b16493 128/* Interrupt Controller (INTC) */
8ae158cd
TL		 129typedef struct int0_ctrl {
130 u32 iprh0; /* 0x00 Pending Register High */
131 u32 iprl0; /* 0x04 Pending Register Low */
132 u32 imrh0; /* 0x08 Mask Register High */
133 u32 imrl0; /* 0x0C Mask Register Low */
134 u32 frch0; /* 0x10 Force Register High */
135 u32 frcl0; /* 0x14 Force Register Low */
136 u16 res1; /* 0x18 - 0x19 */
137 u16 icfg0; /* 0x1A Configuration Register */
138 u8 simr0; /* 0x1C Set Interrupt Mask */
139 u8 cimr0; /* 0x1D Clear Interrupt Mask */
140 u8 clmask0; /* 0x1E Current Level Mask */
141 u8 slmask; /* 0x1F Saved Level Mask */
142 u32 res2[8]; /* 0x20 - 0x3F */
143 u8 icr0[64]; /* 0x40 - 0x7F Control registers */
144 u32 res3[24]; /* 0x80 - 0xDF */
145 u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
146 u8 res4[3]; /* 0xE1 - 0xE3 */
147 u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
148 u8 res5[3]; /* 0xE5 - 0xE7 */
149 u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
150 u8 res6[3]; /* 0xE9 - 0xEB */
151 u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
152 u8 res7[3]; /* 0xED - 0xEF */
153 u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
154 u8 res8[3]; /* 0xF1 - 0xF3 */
155 u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
156 u8 res9[3]; /* 0xF5 - 0xF7 */
157 u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
158 u8 resa[3]; /* 0xF9 - 0xFB */
159 u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
160 u8 resb[3]; /* 0xFD - 0xFF */
161} int0_t;
162
163typedef struct int1_ctrl {
164 /* Interrupt Controller 1 */
165 u32 iprh1; /* 0x00 Pending Register High */
166 u32 iprl1; /* 0x04 Pending Register Low */
167 u32 imrh1; /* 0x08 Mask Register High */
168 u32 imrl1; /* 0x0C Mask Register Low */
169 u32 frch1; /* 0x10 Force Register High */
170 u32 frcl1; /* 0x14 Force Register Low */
171 u16 res1; /* 0x18 */
172 u16 icfg1; /* 0x1A Configuration Register */
173 u8 simr1; /* 0x1C Set Interrupt Mask */
174 u8 cimr1; /* 0x1D Clear Interrupt Mask */
175 u16 res2; /* 0x1E - 0x1F */
176 u32 res3[8]; /* 0x20 - 0x3F */
177 u8 icr1[64]; /* 0x40 - 0x7F */
178 u32 res4[24]; /* 0x80 - 0xDF */
179 u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
180 u8 res5[3]; /* 0xE1 - 0xE3 */
181 u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
182 u8 res6[3]; /* 0xE5 - 0xE7 */
183 u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
184 u8 res7[3]; /* 0xE9 - 0xEB */
185 u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
186 u8 res8[3]; /* 0xED - 0xEF */
187 u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
188 u8 res9[3]; /* 0xF1 - 0xF3 */
189 u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
190 u8 resa[3]; /* 0xF5 - 0xF7 */
191 u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
192 u8 resb[3]; /* 0xF9 - 0xFB */
193 u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
194 u8 resc[3]; /* 0xFD - 0xFF */
195} int1_t;
196
d2b16493 197/* Global Interrupt Acknowledge (IACK) */
8ae158cd
TL		 198typedef struct iack {
199 u8 resv0[0xE0];
200 u8 gswiack;
201 u8 resv1[0x3];
202 u8 gl1iack;
203 u8 resv2[0x3];
204 u8 gl2iack;
205 u8 resv3[0x3];
206 u8 gl3iack;
207 u8 resv4[0x3];
208 u8 gl4iack;
209 u8 resv5[0x3];
210 u8 gl5iack;
211 u8 resv6[0x3];
212 u8 gl6iack;
213 u8 resv7[0x3];
214 u8 gl7iack;
215} iack_t;
216
d2b16493 217/* Edge Port Module (EPORT) */
8ae158cd
TL		 218typedef struct eport {
219 u16 eppar;
220 u8 epddr;
221 u8 epier;
222 u8 epdr;
223 u8 eppdr;
224 u8 epfr;
225} eport_t;
226
d2b16493 227/* Watchdog Timer Modules (WTM) */
8ae158cd
TL		 228typedef struct wtm {
229 u16 wcr;
230 u16 wmr;
231 u16 wcntr;
232 u16 wsr;
233} wtm_t;
234
d2b16493 235/* Serial Boot Facility (SBF) */
8ae158cd
TL		 236typedef struct sbf {
237 u8 resv0[0x18];
238 u16 sbfsr; /* Serial Boot Facility Status Register */
239 u8 resv1[0x6];
240 u16 sbfcr; /* Serial Boot Facility Control Register */
241} sbf_t;
242
d2b16493 243/* Reset Controller Module (RCM) */
8ae158cd
TL		 244typedef struct rcm {
245 u8 rcr;
246 u8 rsr;
247} rcm_t;
248
d2b16493 249/* Chip Configuration Module (CCM) */
8ae158cd
TL		 250typedef struct ccm {
251 u8 ccm_resv0[0x4];
252 u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
253 u8 resv1[0x2];
254 u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
255 u16 cir; /* Chip Identification Register (Read-only) */
256 u8 resv2[0x4];
257 u16 misccr; /* Miscellaneous Control Register */
258 u16 cdr; /* Clock Divider Register */
259 u16 uocsr; /* USB On-the-Go Controller Status Register */
260} ccm_t;
261
d2b16493 262/* General Purpose I/O Module (GPIO) */
8ae158cd
TL		 263typedef struct gpio {
264 u8 podr_fec0h; /* FEC0 High Port Output Data Register */
265 u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
266 u8 podr_ssi; /* SSI Port Output Data Register */
267 u8 podr_fbctl; /* Flexbus Control Port Output Data Register */
268 u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */
269 u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
270 u8 podr_dma; /* DMA Port Output Data Register */
271 u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */
272 u8 resv0[0x1];
273 u8 podr_uart; /* UART Port Output Data Register */
274 u8 podr_dspi; /* DSPI Port Output Data Register */
275 u8 podr_timer; /* Timer Port Output Data Register */
276 u8 podr_pci; /* PCI Port Output Data Register */
277 u8 podr_usb; /* USB Port Output Data Register */
278 u8 podr_atah; /* ATA High Port Output Data Register */
279 u8 podr_atal; /* ATA Low Port Output Data Register */
280 u8 podr_fec1h; /* FEC1 High Port Output Data Register */
281 u8 podr_fec1l; /* FEC1 Low Port Output Data Register */
282 u8 resv1[0x2];
283 u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */
284 u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */
285 u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */
286 u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */
287 u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */
288 u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */
289 u8 pddr_ssi; /* SSI Port Data Direction Register */
290 u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */
291 u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */
292 u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */
293 u8 pddr_dma; /* DMA Port Data Direction Register */
294 u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */
295 u8 resv2[0x1];
296 u8 pddr_uart; /* UART Port Data Direction Register */
297 u8 pddr_dspi; /* DSPI Port Data Direction Register */
298 u8 pddr_timer; /* Timer Port Data Direction Register */
299 u8 pddr_pci; /* PCI Port Data Direction Register */
300 u8 pddr_usb; /* USB Port Data Direction Register */
301 u8 pddr_atah; /* ATA High Port Data Direction Register */
302 u8 pddr_atal; /* ATA Low Port Data Direction Register */
303 u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */
304 u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */
305 u8 resv3[0x2];
306 u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */
307 u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */
308 u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */
309 u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */
310 u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */
311 u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */
312 u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */
313 u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */
314 u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */
315 u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */
316 u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */
317 u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */
318 u8 resv4[0x1];
319 u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */
320 u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */
321 u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */
322 u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */
323 u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */
324 u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */
325 u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */
326 u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */
327 u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */
328 u8 resv5[0x2];
329 u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */
330 u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */
331 u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
332 u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */
333 u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */
334 u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */
335 u8 pclrr_ssi; /* SSI Port Clear Output Data Register */
336 u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */
337 u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */
338 u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */
339 u8 pclrr_dma; /* DMA Port Clear Output Data Register */
340 u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */
341 u8 resv6[0x1];
342 u8 pclrr_uart; /* UART Port Clear Output Data Register */
343 u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */
344 u8 pclrr_timer; /* Timer Port Clear Output Data Register */
345 u8 pclrr_pci; /* PCI Port Clear Output Data Register */
346 u8 pclrr_usb; /* USB Port Clear Output Data Register */
347 u8 pclrr_atah; /* ATA High Port Clear Output Data Register */
348 u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */
349 u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */
350 u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */
351 u8 resv7[0x2];
352 u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */
353 u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */
354 u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */
355 u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */
356 u8 par_fec; /* FEC Pin Assignment Register */
357 u8 par_dma; /* DMA Pin Assignment Register */
358 u8 par_fbctl; /* Flexbus Control Pin Assignment Register */
359 u8 par_dspi; /* DSPI Pin Assignment Register */
360 u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */
361 u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */
362 u8 par_timer; /* Time Pin Assignment Register */
363 u8 par_usb; /* USB Pin Assignment Register */
364 u8 resv8[0x1];
365 u8 par_uart; /* UART Pin Assignment Register */
366 u16 par_feci2c; /* FEC / I2C Pin Assignment Register */
367 u16 par_ssi; /* SSI Pin Assignment Register */
368 u16 par_ata; /* ATA Pin Assignment Register */
369 u8 par_irq; /* IRQ Pin Assignment Register */
370 u8 resv9[0x1];
371 u16 par_pci; /* PCI Pin Assignment Register */
372 u8 mscr_sdram; /* SDRAM Mode Select Control Register */
373 u8 mscr_pci; /* PCI Mode Select Control Register */
374 u8 resv10[0x2];
375 u8 dscr_i2c; /* I2C Drive Strength Control Register */
376 u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */
377 u8 dscr_fec; /* FEC Drive Strength Control Register */
378 u8 dscr_uart; /* UART Drive Strength Control Register */
379 u8 dscr_dspi; /* DSPI Drive Strength Control Register */
380 u8 dscr_timer; /* TIMER Drive Strength Control Register */
381 u8 dscr_ssi; /* SSI Drive Strength Control Register */
382 u8 dscr_dma; /* DMA Drive Strength Control Register */
383 u8 dscr_debug; /* DEBUG Drive Strength Control Register */
384 u8 dscr_reset; /* RESET Drive Strength Control Register */
385 u8 dscr_irq; /* IRQ Drive Strength Control Register */
386 u8 dscr_usb; /* USB Drive Strength Control Register */
387 u8 dscr_ata; /* ATA Drive Strength Control Register */
388} gpio_t;
389
d2b16493 390/* Random Number Generator (RNG) */
8ae158cd
TL		 391typedef struct rng {
392 u32 rngcr;
393 u32 rngsr;
394 u32 rnger;
395 u32 rngout;
396} rng_t;
397
d2b16493 398/* SDRAM Controller (SDRAMC) */
8ae158cd
TL		 399typedef struct sdramc {
400 u32 sdmr; /* SDRAM Mode/Extended Mode Register */
401 u32 sdcr; /* SDRAM Control Register */
402 u32 sdcfg1; /* SDRAM Configuration Register 1 */
403 u32 sdcfg2; /* SDRAM Chip Select Register */
404 u8 resv0[0x100];
405 u32 sdcs0; /* SDRAM Mode/Extended Mode Register */
406 u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
407} sdramc_t;
408
d2b16493 409/* Phase Locked Loop (PLL) */
8ae158cd
TL		 410typedef struct pll {
411 u32 pcr; /* PLL Control Register */
412 u32 psr; /* PLL Status Register */
413} pll_t;
414
415typedef struct pci {
416 u32 idr; /* 0x00 Device Id / Vendor Id Register */
417 u32 scr; /* 0x04 Status / command Register */
418 u32 ccrir; /* 0x08 Class Code / Revision Id Register */
419 u32 cr1; /* 0x0c Configuration 1 Register */
420 u32 bar0; /* 0x10 Base address register 0 Register */
421 u32 bar1; /* 0x14 Base address register 1 Register */
422 u32 bar2; /* 0x18 Base address register 2 Register */
423 u32 bar3; /* 0x1c Base address register 3 Register */
424 u32 bar4; /* 0x20 Base address register 4 Register */
425 u32 bar5; /* 0x24 Base address register 5 Register */
426 u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */
427 u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */
428 u32 erbar; /* 0x30 Expansion ROM Base Address Register */
429 u32 cpr; /* 0x34 Capabilities Pointer Register */
430 u32 rsvd1; /* 0x38 */
431 u32 cr2; /* 0x3c Configuration Register 2 */
432 u32 rsvd2[8]; /* 0x40 - 0x5f */
433
434 /* General control / status registers */
435 u32 gscr; /* 0x60 Global Status / Control Register */
436 u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */
437 u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */
438 u32 tcr1; /* 0x6c Target Control 1 Register */
439 u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */
440 u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */
441 u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */
442 u32 rsvd3; /* 0x7c */
443 u32 iwcr; /* 0x80 Initiator Window Configuration Register */
444 u32 icr; /* 0x84 Initiator Control Register */
445 u32 isr; /* 0x88 Initiator Status Register */
446 u32 tcr2; /* 0x8c Target Control 2 Register */
447 u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */
448 u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */
449 u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */
450 u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */
451 u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */
452 u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */
453 u32 intr; /* 0xa8 Interrupt Register */
454 u32 rsvd4[19]; /* 0xac - 0xf7 */
455 u32 car; /* 0xf8 Configuration Address Register */
456} pci_t;
457
458typedef struct pci_arbiter {
459 /* Pci Arbiter Registers */
460 union {
461 u32 acr; /* Arbiter Control Register */
462 u32 asr; /* Arbiter Status Register */
463 };
464} pciarb_t;
465
466/* Register read/write struct */
467typedef struct scm1 {
468 u32 mpr; /* 0x00 Master Privilege Register */
469 u32 rsvd1[7];
470 u32 pacra; /* 0x20 Peripheral Access Control Register A */
471 u32 pacrb; /* 0x24 Peripheral Access Control Register B */
472 u32 pacrc; /* 0x28 Peripheral Access Control Register C */
473 u32 pacrd; /* 0x2C Peripheral Access Control Register D */
474 u32 rsvd2[4];
475 u32 pacre; /* 0x40 Peripheral Access Control Register E */
476 u32 pacrf; /* 0x44 Peripheral Access Control Register F */
477 u32 pacrg; /* 0x48 Peripheral Access Control Register G */
478} scm1_t;
d2b16493
TL		 479
480typedef struct scm2 {
481 u8 rsvd1[19]; /* 0x00 - 0x12 */
482 u8 wcr; /* 0x13 */
483 u16 rsvd2; /* 0x14 - 0x15 */
484 u16 cwcr; /* 0x16 */
485 u8 rsvd3[3]; /* 0x18 - 0x1A */
486 u8 cwsr; /* 0x1B */
487 u8 rsvd4[3]; /* 0x1C - 0x1E */
488 u8 scmisr; /* 0x1F */
489 u32 rsvd5; /* 0x20 - 0x23 */
490 u8 bcr; /* 0x24 */
491 u8 rsvd6[74]; /* 0x25 - 0x6F */
492 u32 cfadr; /* 0x70 */
493 u8 rsvd7; /* 0x74 */
494 u8 cfier; /* 0x75 */
495 u8 cfloc; /* 0x76 */
496 u8 cfatr; /* 0x77 */
497 u32 rsvd8; /* 0x78 - 0x7B */
498 u32 cfdtr; /* 0x7C */
499} scm2_t;
8ae158cd
TL		 500
501typedef struct rtcex {
502 u32 rsvd1[3];
503 u32 gocu;
504 u32 gocl;
505} rtcex_t;
506#endif /* __IMMAP_5445X__ */
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