[J-u-boot.git] / board / samsung / common / board.c

/*
 * (C) Copyright 2013 SAMSUNG Electronics
 * Rajeshwari Shinde <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <cros_ec.h>
#include <errno.h>
#include <fdtdec.h>
#include <spi.h>
#include <tmu.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/board.h>
#include <asm/arch/cpu.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
#include <power/pmic.h>
#include <asm/arch/sromc.h>
#include <power/max77686_pmic.h>

DECLARE_GLOBAL_DATA_PTR;

struct local_info {
	struct cros_ec_dev *cros_ec_dev;	/* Pointer to cros_ec device */
	int cros_ec_err;			/* Error for cros_ec, 0 if ok */
};

static struct local_info local;

#if defined CONFIG_EXYNOS_TMU
/* Boot Time Thermal Analysis for SoC temperature threshold breach */
static void boot_temp_check(void)
{
	int temp;

	switch (tmu_monitor(&temp)) {
	case TMU_STATUS_NORMAL:
		break;
	case TMU_STATUS_TRIPPED:
		/*
		 * Status TRIPPED ans WARNING means corresponding threshold
		 * breach
		 */
		puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
		set_ps_hold_ctrl();
		hang();
		break;
	case TMU_STATUS_WARNING:
		puts("EXYNOS_TMU: WARNING! Temperature very high\n");
		break;
	case TMU_STATUS_INIT:
		/*
		 * TMU_STATUS_INIT means something is wrong with temperature
		 * sensing and TMU status was changed back from NORMAL to INIT.
		 */
		puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n");
		break;
	default:
		debug("EXYNOS_TMU: Unknown TMU state\n");
	}
}
#endif

int board_init(void)
{
	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
#if defined CONFIG_EXYNOS_TMU
	if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
		debug("%s: Failed to init TMU\n", __func__);
		return -1;
	}
	boot_temp_check();
#endif

#ifdef CONFIG_EXYNOS_SPI
	spi_init();
#endif
	return exynos_init();
}

int dram_init(void)
{
	int i;
	u32 addr;

	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
		gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
	}
	return 0;
}

void dram_init_banksize(void)
{
	int i;
	u32 addr, size;

	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
		size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);

		gd->bd->bi_dram[i].start = addr;
		gd->bd->bi_dram[i].size = size;
	}
}

static int board_uart_init(void)
{
	int err, uart_id, ret = 0;

	for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
		err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
		if (err) {
			debug("UART%d not configured\n",
			      (uart_id - PERIPH_ID_UART0));
			ret |= err;
		}
	}
	return ret;
}

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
	int err;

	err = board_uart_init();
	if (err) {
		debug("UART init failed\n");
		return err;
	}

#ifdef CONFIG_SYS_I2C_INIT_BOARD
	board_i2c_init(gd->fdt_blob);
#endif

	return err;
}
#endif

struct cros_ec_dev *board_get_cros_ec_dev(void)
{
	return local.cros_ec_dev;
}

#ifdef CONFIG_CROS_EC
static int board_init_cros_ec_devices(const void *blob)
{
	local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
	if (local.cros_ec_err)
		return -1;  /* Will report in board_late_init() */

	return 0;
}
#endif

#if defined(CONFIG_POWER)
#ifdef CONFIG_POWER_MAX77686
static int pmic_reg_update(struct pmic *p, int reg, uint regval)
{
	u32 val;
	int ret = 0;

	ret = pmic_reg_read(p, reg, &val);
	if (ret) {
		debug("%s: PMIC %d register read failed\n", __func__, reg);
		return -1;
	}
	val |= regval;
	ret = pmic_reg_write(p, reg, val);
	if (ret) {
		debug("%s: PMIC %d register write failed\n", __func__, reg);
		return -1;
	}
	return 0;
}

static int max77686_init(void)
{
	struct pmic *p;

	if (pmic_init(I2C_PMIC))
		return -1;

	p = pmic_get("MAX77686_PMIC");
	if (!p)
		return -ENODEV;

	if (pmic_probe(p))
		return -1;

	if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
		return -1;

	if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
			    MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
		return -1;

	/* VDD_MIF */
	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
			   MAX77686_BUCK1OUT_1V)) {
		debug("%s: PMIC %d register write failed\n", __func__,
		      MAX77686_REG_PMIC_BUCK1OUT);
		return -1;
	}

	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
			    MAX77686_BUCK1CTRL_EN))
		return -1;

	/* VDD_ARM */
	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
			   MAX77686_BUCK2DVS1_1_3V)) {
		debug("%s: PMIC %d register write failed\n", __func__,
		      MAX77686_REG_PMIC_BUCK2DVS1);
		return -1;
	}

	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
			    MAX77686_BUCK2CTRL_ON))
		return -1;

	/* VDD_INT */
	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
			   MAX77686_BUCK3DVS1_1_0125V)) {
		debug("%s: PMIC %d register write failed\n", __func__,
		      MAX77686_REG_PMIC_BUCK3DVS1);
		return -1;
	}

	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
			    MAX77686_BUCK3CTRL_ON))
		return -1;

	/* VDD_G3D */
	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
			   MAX77686_BUCK4DVS1_1_2V)) {
		debug("%s: PMIC %d register write failed\n", __func__,
		      MAX77686_REG_PMIC_BUCK4DVS1);
		return -1;
	}

	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
			    MAX77686_BUCK3CTRL_ON))
		return -1;

	/* VDD_LDO2 */
	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
			    MAX77686_LD02CTRL1_1_5V | EN_LDO))
		return -1;

	/* VDD_LDO3 */
	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
			    MAX77686_LD03CTRL1_1_8V | EN_LDO))
		return -1;

	/* VDD_LDO5 */
	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
			    MAX77686_LD05CTRL1_1_8V | EN_LDO))
		return -1;

	/* VDD_LDO10 */
	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
			    MAX77686_LD10CTRL1_1_8V | EN_LDO))
		return -1;

	return 0;
}
#endif

int power_init_board(void)
{
	int ret = 0;

	set_ps_hold_ctrl();

#ifdef CONFIG_POWER_MAX77686
	ret = max77686_init();
#endif

	return ret;
}
#endif

#ifdef CONFIG_OF_CONTROL
static int decode_sromc(const void *blob, struct fdt_sromc *config)
{
	int err;
	int node;

	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
	if (node < 0) {
		debug("Could not find SROMC node\n");
		return node;
	}

	config->bank = fdtdec_get_int(blob, node, "bank", 0);
	config->width = fdtdec_get_int(blob, node, "width", 2);

	err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
			FDT_SROM_TIMING_COUNT);
	if (err < 0) {
		debug("Could not decode SROMC configuration Error: %s\n",
		      fdt_strerror(err));
		return -FDT_ERR_NOTFOUND;
	}
	return 0;
}

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SMC911X
	u32 smc_bw_conf, smc_bc_conf;
	struct fdt_sromc config;
	fdt_addr_t base_addr;
	int node;

	node = decode_sromc(gd->fdt_blob, &config);
	if (node < 0) {
		debug("%s: Could not find sromc configuration\n", __func__);
		return 0;
	}
	node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
	if (node < 0) {
		debug("%s: Could not find lan9215 configuration\n", __func__);
		return 0;
	}

	/* We now have a node, so any problems from now on are errors */
	base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
	if (base_addr == FDT_ADDR_T_NONE) {
		debug("%s: Could not find lan9215 address\n", __func__);
		return -1;
	}

	/* Ethernet needs data bus width of 16 bits */
	if (config.width != 2) {
		debug("%s: Unsupported bus width %d\n", __func__,
		      config.width);
		return -1;
	}
	smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
			| SROMC_BYTE_ENABLE(config.bank);

	smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |
			SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
			SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
			SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
			SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |
			SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
			SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);

	/* Select and configure the SROMC bank */
	exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
	s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
	return smc911x_initialize(0, base_addr);
#endif
	return 0;
}

#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
	int ret;

	/* dwmmc initializattion for available channels */
	ret = exynos_dwmmc_init(gd->fdt_blob);
	if (ret)
		debug("dwmmc init failed\n");

	return ret;
}
#endif
#endif

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
	stdio_print_current_devices();

	if (local.cros_ec_err) {
		/* Force console on */
		gd->flags &= ~GD_FLG_SILENT;

		printf("cros-ec communications failure %d\n",
		       local.cros_ec_err);
		puts("\nPlease reset with Power+Refresh\n\n");
		panic("Cannot init cros-ec device");
		return -1;
	}
	return 0;
}
#endif

int arch_early_init_r(void)
{
#ifdef CONFIG_CROS_EC
	if (board_init_cros_ec_devices(gd->fdt_blob)) {
		printf("%s: Failed to init EC\n", __func__);
		return 0;
	}
#endif

	return 0;
}
Commit	Line	Data
71ebb335 RS	1	/*
	2	* (C) Copyright 2013 SAMSUNG Electronics
	3	* Rajeshwari Shinde <[email protected]>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <cros_ec.h>
	10	#include <errno.h>
	11	#include <fdtdec.h>
	12	#include <spi.h>
	13	#include <tmu.h>
	14	#include <netdev.h>
	15	#include <asm/io.h>
	16	#include <asm/arch/board.h>
	17	#include <asm/arch/cpu.h>
	18	#include <asm/arch/dwmmc.h>
	19	#include <asm/arch/gpio.h>
	20	#include <asm/arch/mmc.h>
	21	#include <asm/arch/pinmux.h>
	22	#include <asm/arch/power.h>
	23	#include <power/pmic.h>
	24	#include <asm/arch/sromc.h>
	25	#include <power/max77686_pmic.h>
	26
	27	DECLARE_GLOBAL_DATA_PTR;
	28
	29	struct local_info {
	30	struct cros_ec_dev cros_ec_dev; / Pointer to cros_ec device */
	31	int cros_ec_err; /* Error for cros_ec, 0 if ok */
	32	};
	33
	34	static struct local_info local;
	35
	36	#if defined CONFIG_EXYNOS_TMU
	37	/* Boot Time Thermal Analysis for SoC temperature threshold breach */
	38	static void boot_temp_check(void)
	39	{
	40	int temp;
	41
	42	switch (tmu_monitor(&temp)) {
	43	case TMU_STATUS_NORMAL:
	44	break;
	45	case TMU_STATUS_TRIPPED:
	46	/*
	47	* Status TRIPPED ans WARNING means corresponding threshold
	48	* breach
	49	*/
	50	puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
	51	set_ps_hold_ctrl();
	52	hang();
	53	break;
	54	case TMU_STATUS_WARNING:
	55	puts("EXYNOS_TMU: WARNING! Temperature very high\n");
	56	break;
	57	case TMU_STATUS_INIT:
	58	/*
	59	* TMU_STATUS_INIT means something is wrong with temperature
	60	* sensing and TMU status was changed back from NORMAL to INIT.
	61	*/
	62	puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n");
	63	break;
	64	default:
65	debug("EXYNOS_TMU: Unknown TMU state\n");
66	}
67	}
68	#endif
69
70	int board_init(void)
71	{
72	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
73	#if defined CONFIG_EXYNOS_TMU
74	if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
75	debug("%s: Failed to init TMU\n", __func__);
76	return -1;
77	}
78	boot_temp_check();
79	#endif
80
81	#ifdef CONFIG_EXYNOS_SPI
82	spi_init();
83	#endif
84	return exynos_init();
85	}
86
87	int dram_init(void)
88	{
89	int i;
90	u32 addr;
91
92	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
93	addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
94	gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
95	}
96	return 0;
97	}
98
99	void dram_init_banksize(void)
100	{
101	int i;
102	u32 addr, size;
103
104	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
105	addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
106	size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
107
108	gd->bd->bi_dram[i].start = addr;
109	gd->bd->bi_dram[i].size = size;
110	}
111	}
112
113	static int board_uart_init(void)
114	{
115	int err, uart_id, ret = 0;
116
117	for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
118	err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
119	if (err) {
120	debug("UART%d not configured\n",
121	(uart_id - PERIPH_ID_UART0));
122	ret \|= err;
123	}
124	}
125	return ret;
126	}
127
128	#ifdef CONFIG_BOARD_EARLY_INIT_F
129	int board_early_init_f(void)
130	{
131	int err;
132
133	err = board_uart_init();
134	if (err) {
135	debug("UART init failed\n");
136	return err;
137	}
138
139	#ifdef CONFIG_SYS_I2C_INIT_BOARD
140	board_i2c_init(gd->fdt_blob);
141	#endif
142
143	return err;
144	}
145	#endif
146
147	struct cros_ec_dev *board_get_cros_ec_dev(void)
148	{
149	return local.cros_ec_dev;
150	}
151
e106bd9b	152	#ifdef CONFIG_CROS_EC
71ebb335 RS	153	static int board_init_cros_ec_devices(const void *blob)
	154	{
	155	local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
	156	if (local.cros_ec_err)
	157	return -1; /* Will report in board_late_init() */
	158
	159	return 0;
	160	}
e106bd9b	161	#endif
71ebb335 RS	162
	163	#if defined(CONFIG_POWER)
	164	#ifdef CONFIG_POWER_MAX77686
	165	static int pmic_reg_update(struct pmic *p, int reg, uint regval)
	166	{
	167	u32 val;
	168	int ret = 0;
	169
	170	ret = pmic_reg_read(p, reg, &val);
	171	if (ret) {
	172	debug("%s: PMIC %d register read failed\n", __func__, reg);
	173	return -1;
	174	}
	175	val \|= regval;
	176	ret = pmic_reg_write(p, reg, val);
	177	if (ret) {
	178	debug("%s: PMIC %d register write failed\n", __func__, reg);
	179	return -1;
	180	}
	181	return 0;
	182	}
	183
	184	static int max77686_init(void)
	185	{
	186	struct pmic *p;
	187
	188	if (pmic_init(I2C_PMIC))
	189	return -1;
	190
	191	p = pmic_get("MAX77686_PMIC");
	192	if (!p)
	193	return -ENODEV;
	194
	195	if (pmic_probe(p))
	196	return -1;
	197
	198	if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
	199	return -1;
	200
	201	if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
	202	MAX77686_BBCHOSTEN \| MAX77686_BBCVS_3_5V))
	203	return -1;
	204
	205	/* VDD_MIF */
	206	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
	207	MAX77686_BUCK1OUT_1V)) {
	208	debug("%s: PMIC %d register write failed\n", __func__,
	209	MAX77686_REG_PMIC_BUCK1OUT);
	210	return -1;
	211	}
	212
	213	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
	214	MAX77686_BUCK1CTRL_EN))
	215	return -1;
	216
	217	/* VDD_ARM */
	218	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
	219	MAX77686_BUCK2DVS1_1_3V)) {
	220	debug("%s: PMIC %d register write failed\n", __func__,
	221	MAX77686_REG_PMIC_BUCK2DVS1);
	222	return -1;
	223	}
	224
	225	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
226	MAX77686_BUCK2CTRL_ON))
227	return -1;
228
229	/* VDD_INT */
230	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
231	MAX77686_BUCK3DVS1_1_0125V)) {
232	debug("%s: PMIC %d register write failed\n", __func__,
233	MAX77686_REG_PMIC_BUCK3DVS1);
234	return -1;
235	}
236
237	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
238	MAX77686_BUCK3CTRL_ON))
239	return -1;
240
241	/* VDD_G3D */
242	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
243	MAX77686_BUCK4DVS1_1_2V)) {
244	debug("%s: PMIC %d register write failed\n", __func__,
245	MAX77686_REG_PMIC_BUCK4DVS1);
246	return -1;
247	}
248
249	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
250	MAX77686_BUCK3CTRL_ON))
251	return -1;
252
253	/* VDD_LDO2 */
254	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
255	MAX77686_LD02CTRL1_1_5V \| EN_LDO))
256	return -1;
257
258	/* VDD_LDO3 */
259	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
260	MAX77686_LD03CTRL1_1_8V \| EN_LDO))
261	return -1;
262
263	/* VDD_LDO5 */
264	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
265	MAX77686_LD05CTRL1_1_8V \| EN_LDO))
266	return -1;
267
268	/* VDD_LDO10 */
269	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
270	MAX77686_LD10CTRL1_1_8V \| EN_LDO))
271	return -1;
272
273	return 0;
274	}
275	#endif
276
277	int power_init_board(void)
278	{
279	int ret = 0;
280
281	set_ps_hold_ctrl();
282
283	#ifdef CONFIG_POWER_MAX77686
284	ret = max77686_init();
285	#endif
286
287	return ret;
288	}
289	#endif
290
291	#ifdef CONFIG_OF_CONTROL
292	static int decode_sromc(const void blob, struct fdt_sromc config)
293	{
294	int err;
295	int node;
296
297	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
298	if (node < 0) {
299	debug("Could not find SROMC node\n");
300	return node;
301	}
302
303	config->bank = fdtdec_get_int(blob, node, "bank", 0);
304	config->width = fdtdec_get_int(blob, node, "width", 2);
305
306	err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
307	FDT_SROM_TIMING_COUNT);
308	if (err < 0) {
309	debug("Could not decode SROMC configuration Error: %s\n",
310	fdt_strerror(err));
311	return -FDT_ERR_NOTFOUND;
312	}
313	return 0;
314	}
315
316	int board_eth_init(bd_t *bis)
317	{
318	#ifdef CONFIG_SMC911X
319	u32 smc_bw_conf, smc_bc_conf;
320	struct fdt_sromc config;
321	fdt_addr_t base_addr;
322	int node;
323
324	node = decode_sromc(gd->fdt_blob, &config);
325	if (node < 0) {
326	debug("%s: Could not find sromc configuration\n", __func__);
327	return 0;
328	}
329	node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
330	if (node < 0) {
331	debug("%s: Could not find lan9215 configuration\n", __func__);
332	return 0;
333	}
334
335	/* We now have a node, so any problems from now on are errors */
336	base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
337	if (base_addr == FDT_ADDR_T_NONE) {
338	debug("%s: Could not find lan9215 address\n", __func__);
339	return -1;
340	}
341
342	/* Ethernet needs data bus width of 16 bits */
343	if (config.width != 2) {
344	debug("%s: Unsupported bus width %d\n", __func__,
345	config.width);
346	return -1;
347	}
348	smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
349	\| SROMC_BYTE_ENABLE(config.bank);
350
351	smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) \|
352	SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) \|
353	SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) \|
354	SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) \|
355	SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) \|
356	SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) \|
357	SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
358
359	/* Select and configure the SROMC bank */
360	exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
361	s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
362	return smc911x_initialize(0, base_addr);
363	#endif
364	return 0;
365	}
366
367	#ifdef CONFIG_GENERIC_MMC
368	int board_mmc_init(bd_t *bis)
369	{
370	int ret;
371
372	/* dwmmc initializattion for available channels */
373	ret = exynos_dwmmc_init(gd->fdt_blob);
374	if (ret)
375	debug("dwmmc init failed\n");
376
377	return ret;
378	}
379	#endif
380	#endif
381
382	#ifdef CONFIG_BOARD_LATE_INIT
383	int board_late_init(void)
384	{
385	stdio_print_current_devices();
386
387	if (local.cros_ec_err) {
388	/* Force console on */
389	gd->flags &= ~GD_FLG_SILENT;
390
391	printf("cros-ec communications failure %d\n",
392	local.cros_ec_err);
393	puts("\nPlease reset with Power+Refresh\n\n");
394	panic("Cannot init cros-ec device");
395	return -1;
396	}
397	return 0;
398	}
399	#endif
400
401	int arch_early_init_r(void)
402	{
403	#ifdef CONFIG_CROS_EC
404	if (board_init_cros_ec_devices(gd->fdt_blob)) {
405	printf("%s: Failed to init EC\n", __func__);
406	return 0;
407	}
408	#endif
409
410	return 0;
411	}