[J-u-boot.git] / include / configs / imx31_phycore.h

/*
 * (C) Copyright 2004
 * Texas Instruments.
 * Richard Woodruff <[email protected]>
 * Kshitij Gupta <[email protected]>
 *
 * Configuration settings for the phyCORE-i.MX31 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

/* High Level Configuration Options */
#define CONFIG_ARM1136			/* This is an arm1136 CPU core */
#define CONFIG_MX31			/* in a mx31 */
#define CONFIG_MX31_HCLK_FREQ	26000000
#define CONFIG_MX31_CLK32	32000

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 512 * 1024)

/*
 * Hardware drivers
 */

#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE		I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_CLK_OFFSET	I2C2_CLK_OFFSET
#define CONFIG_SYS_I2C_SPEED		100000

#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE		UART1_BASE

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200

/***********************************************************
 * Command definition
 ***********************************************************/

#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C

#define CONFIG_BOOTDELAY	3

#define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:128k(uboot)ro," \
					"1536k(kernel),-(root)"

#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		192.168.23.168
#define CONFIG_SERVERIP		192.168.23.2

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"	\
	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
	"bootargs_flash=setenv bootargs $(bootargs) "			\
		"root=/dev/mtdblock2 rootfstype=jffs2\0"		\
	"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0"	\
	"bootcmd=run bootcmd_net\0"					\
	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;"	\
		"tftpboot 0x80000000 $(uimage);bootm\0"			\
	"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;"	\
		"bootm 0x80000000\0"					\
	"unlock=yes\0"							\
	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
	"prg_uboot=tftpboot 0x80000000 $(uboot);"			\
		"protect off 0xa0000000 +0x20000;"			\
		"erase 0xa0000000 +0x20000;"				\
		"cp.b 0x80000000 0xa0000000 $(filesize)\0"		\
	"prg_kernel=tftpboot 0x80000000 $(uimage);"			\
		"erase 0xa0040000 +0x180000;"				\
		"cp.b 0x80000000 0xa0040000 $(filesize)\0"		\
	"prg_jffs2=tftpboot 0x80000000 $(jffs2);"			\
		"erase 0xa01c0000 0xa1ffffff;"				\
		"cp.b 0x80000000 0xa01c0000 $(filesize)\0"		\
	"videomode=video=ctfb:x:240,y:320,depth:16,mode:0,"		\
		"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1,"		\
		"sync:1241513985,vmode:0\0"


#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE	0xa8000000
#define CONFIG_SMC911X_32_BIT

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_PROMPT		"uboot> "
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE		256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					 sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS		16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x10000

#define CONFIG_SYS_LOAD_ADDR		0 /* default load address */

#define CONFIG_SYS_HZ			1000

#define CONFIG_CMDLINE_EDITING

/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 * 1024) /* regular stack */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			0x80000000
#define PHYS_SDRAM_1_SIZE		(128 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_TEXT_BASE		0xA0000000

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
						CONFIG_SYS_GBL_DATA_OFFSET)

/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		0xa0000000
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	259	/* max # of sectors/chip */
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_OFFSET			0x00	/* env. starts here */
#define CONFIG_ENV_SIZE				4096
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10 ms delay */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* byte addr. lenght */

/*
 * CFI FLASH driver setup
 */
#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER		/* Use drivers/mtd/cfi_flash.c */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */

/*
 * Timeout for Flash Erase and Flash Write
 * timeout values are in ticks
 */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ)

/*
 * JFFS2 partitions
 */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV	"nor0"

/* EET platform additions */
#ifdef CONFIG_IMX31_PHYCORE_EET
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_MXC_GPIO

#define CONFIG_HARD_SPI
#define CONFIG_MXC_SPI
#define CONFIG_CMD_SPI

#define CONFIG_S6E63D6

#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MX3
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
5ad86216 SH	1	/*
	2	* (C) Copyright 2004
	3	* Texas Instruments.
	4	* Richard Woodruff <[email protected]>
	5	* Kshitij Gupta <[email protected]>
	6	*
7064122c	7	* Configuration settings for the phyCORE-i.MX31 board.
5ad86216 SH	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
953ee4d0 FE	31	#include <asm/arch/imx-regs.h>
953ee4d0 FE	32
6ac1c903 AG	33	/* High Level Configuration Options */
	34	#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
	35	#define CONFIG_MX31 /* in a mx31 */
5ad86216 SH	36	#define CONFIG_MX31_HCLK_FREQ 26000000
	37	#define CONFIG_MX31_CLK32 32000
	38
	39	#define CONFIG_DISPLAY_CPUINFO
	40	#define CONFIG_DISPLAY_BOARDINFO
	41
6ac1c903 AG	42	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	43	#define CONFIG_SETUP_MEMORY_TAGS
	44	#define CONFIG_INITRD_TAG
5ad86216 SH	45
	46	/*
	47	* Size of malloc() pool
	48	*/
62a22dca	49	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
5ad86216 SH	50
	51	/*
	52	* Hardware drivers
	53	*/
	54
6ac1c903 AG	55	#define CONFIG_HARD_I2C
6ac1c903 AG	56	#define CONFIG_I2C_MXC
de6f604d TK	57	#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
de6f604d TK	58	#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
6d0f6bcf	59	#define CONFIG_SYS_I2C_SPEED 100000
5ad86216	60
6ac1c903	61	#define CONFIG_MXC_UART
40f6fffe	62	#define CONFIG_MXC_UART_BASE UART1_BASE
5ad86216 SH	63
	64	/* allow to overwrite serial and ethaddr */
	65	#define CONFIG_ENV_OVERWRITE
	66	#define CONFIG_CONS_INDEX 1
	67	#define CONFIG_BAUDRATE 115200
5ad86216 SH	68
	69	/***********************************************************
	70	* Command definition
	71	***********************************************************/
	72
	73	#include <config_cmd_default.h>
	74
	75	#define CONFIG_CMD_PING
	76	#define CONFIG_CMD_EEPROM
	77	#define CONFIG_CMD_I2C
	78
	79	#define CONFIG_BOOTDELAY 3
	80
6ac1c903 AG	81	#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro," \
6ac1c903 AG	82	"1536k(kernel),-(root)"
5ad86216 SH	83
	84	#define CONFIG_NETMASK 255.255.255.0
	85	#define CONFIG_IPADDR 192.168.23.168
	86	#define CONFIG_SERVERIP 192.168.23.2
	87
6ac1c903 AG	88	#define CONFIG_EXTRA_ENV_SETTINGS \
	89	"bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
	90	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
	91	"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
	92	"bootargs_flash=setenv bootargs $(bootargs) " \
	93	"root=/dev/mtdblock2 rootfstype=jffs2\0" \
	94	"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
	95	"bootcmd=run bootcmd_net\0" \
	96	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \
	97	"tftpboot 0x80000000 $(uimage);bootm\0" \
	98	"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \
	99	"bootm 0x80000000\0" \
	100	"unlock=yes\0" \
	101	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	102	"prg_uboot=tftpboot 0x80000000 $(uboot);" \
	103	"protect off 0xa0000000 +0x20000;" \
	104	"erase 0xa0000000 +0x20000;" \
	105	"cp.b 0x80000000 0xa0000000 $(filesize)\0" \
	106	"prg_kernel=tftpboot 0x80000000 $(uimage);" \
	107	"erase 0xa0040000 +0x180000;" \
	108	"cp.b 0x80000000 0xa0040000 $(filesize)\0" \
	109	"prg_jffs2=tftpboot 0x80000000 $(jffs2);" \
	110	"erase 0xa01c0000 0xa1ffffff;" \
	111	"cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
	112	"videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \
	113	"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \
	114	"sync:1241513985,vmode:0\0"
	115
	116
	117	#define CONFIG_SMC911X
736fead8	118	#define CONFIG_SMC911X_BASE 0xa8000000
6ac1c903	119	#define CONFIG_SMC911X_32_BIT
5ad86216 SH	120
	121	/*
	122	* Miscellaneous configurable options
	123	*/
6d0f6bcf JCPV	124	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	125	#define CONFIG_SYS_PROMPT "uboot> "
6ac1c903 AG	126	/* Console I/O Buffer Size */
6ac1c903 AG	127	#define CONFIG_SYS_CBSIZE 256
5ad86216	128	/* Print Buffer Size */
6ac1c903 AG	129	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	130	sizeof(CONFIG_SYS_PROMPT) + 16)
	131	/* max number of command args */
	132	#define CONFIG_SYS_MAXARGS 16
	133	/* Boot Argument Buffer Size */
	134	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
5ad86216	135
6d0f6bcf JCPV	136	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
6d0f6bcf JCPV	137	#define CONFIG_SYS_MEMTEST_END 0x10000
5ad86216	138
6d0f6bcf	139	#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
5ad86216	140
6d0f6bcf	141	#define CONFIG_SYS_HZ 1000
5ad86216	142
6ac1c903	143	#define CONFIG_CMDLINE_EDITING
5ad86216	144
6ac1c903	145	/*
5ad86216 SH	146	* Stack sizes
	147	*
	148	* The stack sizes are set up in start.S using the settings below
	149	*/
	150	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
	151
6ac1c903	152	/*
5ad86216 SH	153	* Physical Memory Map
5ad86216 SH	154	*/
6ac1c903 AG	155	#define CONFIG_NR_DRAM_BANKS 1
	156	#define PHYS_SDRAM_1 0x80000000
	157	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
953ee4d0 FE	158	#define CONFIG_BOARD_EARLY_INIT_F
	159	#define CONFIG_SYS_TEXT_BASE 0xA0000000
	160
	161	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	162	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	163	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	164	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	165	GENERATED_GBL_DATA_SIZE)
	166	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	167	CONFIG_SYS_GBL_DATA_OFFSET)
5ad86216	168
6ac1c903	169	/*
5ad86216 SH	170	* FLASH and environment organization
5ad86216 SH	171	*/
6d0f6bcf	172	#define CONFIG_SYS_FLASH_BASE 0xa0000000
6ac1c903 AG	173	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
	174	#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */
	175	/* Monitor at beginning of flash */
	176	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	177
	178	#define CONFIG_ENV_IS_IN_EEPROM
	179	#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */
	180	#define CONFIG_ENV_SIZE 4096
6d0f6bcf	181	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
6ac1c903 AG	182	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
	183	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */
	184	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */
5ad86216	185
6ac1c903	186	/*
5ad86216 SH	187	* CFI FLASH driver setup
5ad86216 SH	188	*/
6ac1c903 AG	189	#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
	190	#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */
	191	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
	192	#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
5ad86216	193
6ac1c903 AG	194	/*
	195	* Timeout for Flash Erase and Flash Write
	196	* timeout values are in ticks
	197	*/
	198	#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ)
	199	#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ)
5ad86216 SH	200
	201	/*
	202	* JFFS2 partitions
	203	*/
68d7d651	204	#undef CONFIG_CMD_MTDPARTS
5ad86216 SH	205	#define CONFIG_JFFS2_DEV "nor0"
5ad86216 SH	206
a2bb7105 GL	207	/* EET platform additions */
a2bb7105 GL	208	#ifdef CONFIG_IMX31_PHYCORE_EET
9660e442	209	#define CONFIG_BOARD_LATE_INIT
a2bb7105	210
c4ea1424	211	#define CONFIG_MXC_GPIO
a2bb7105	212
6ac1c903 AG	213	#define CONFIG_HARD_SPI
6ac1c903 AG	214	#define CONFIG_MXC_SPI
a2bb7105 GL	215	#define CONFIG_CMD_SPI
a2bb7105 GL	216
6ac1c903	217	#define CONFIG_S6E63D6
a2bb7105	218
62a22dca HR	219	#define CONFIG_VIDEO
	220	#define CONFIG_CFB_CONSOLE
	221	#define CONFIG_VIDEO_MX3
	222	#define CONFIG_VIDEO_LOGO
	223	#define CONFIG_VIDEO_SW_CURSOR
	224	#define CONFIG_VGA_AS_SINGLE_DEVICE
	225	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	226	#define CONFIG_SPLASH_SCREEN
	227	#define CONFIG_CMD_BMP
	228	#define CONFIG_BMP_16BPP
a2bb7105 GL	229	#endif
a2bb7105 GL	230
5ad86216	231	#endif /* __CONFIG_H */