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mxc_i2c: specify i2c base address in config file
[J-u-boot.git] / arch / arm / include / asm / arch-mx31 / imx-regs.h
CommitLineData
9b56f4f0
SH		 1/*
2 *
3 * (c) 2007 Pengutronix, Sascha Hauer <[email protected]>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
a770975a
FE		 24#ifndef __ASM_ARCH_MX31_IMX_REGS_H
25#define __ASM_ARCH_MX31_IMX_REGS_H
9b56f4f0 26
c816dcb1
ML		 27#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
28#include <asm/types.h>
29
30/* Clock control module registers */
31struct clock_control_regs {
32 u32 ccmr;
33 u32 pdr0;
34 u32 pdr1;
35 u32 rcsr;
36 u32 mpctl;
37 u32 upctl;
38 u32 spctl;
39 u32 cosr;
40 u32 cgr0;
41 u32 cgr1;
42 u32 cgr2;
43 u32 wimr0;
44 u32 ldc;
45 u32 dcvr0;
46 u32 dcvr1;
47 u32 dcvr2;
48 u32 dcvr3;
49 u32 ltr0;
50 u32 ltr1;
51 u32 ltr2;
52 u32 ltr3;
53 u32 ltbr0;
54 u32 ltbr1;
55 u32 pmcr0;
56 u32 pmcr1;
57 u32 pdr2;
58};
59
ac87c17d
SB		 60struct cspi_regs {
61 u32 rxdata;
62 u32 txdata;
63 u32 ctrl;
64 u32 intr;
65 u32 dma;
66 u32 stat;
67 u32 period;
68 u32 test;
69};
70
2cf36ae7
SB		 71/* Watchdog Timer (WDOG) registers */
72#define WDOG_ENABLE (1 << 2)
73#define WDOG_WT_SHIFT 8
610b53e2
FE		 74#define WDOG_WDZST (1 << 0)
75
2cf36ae7
SB		 76struct wdog_regs {
77 u16 wcr; /* Control */
78 u16 wsr; /* Service */
79 u16 wrsr; /* Reset Status */
80};
81
4adaf9bf
FE		 82/* IIM Control Registers */
83struct iim_regs {
84 u32 iim_stat;
85 u32 iim_statm;
86 u32 iim_err;
87 u32 iim_emask;
88 u32 iim_fctl;
89 u32 iim_ua;
90 u32 iim_la;
91 u32 iim_sdat;
92 u32 iim_prev;
93 u32 iim_srev;
94 u32 iim_prog_p;
95 u32 iim_scs0;
96 u32 iim_scs1;
97 u32 iim_scs2;
98 u32 iim_scs3;
99};
100
ce93dc9b
FE		 101struct iomuxc_regs {
102 u32 unused1;
103 u32 unused2;
104 u32 gpr;
105};
106
4adaf9bf
FE		 107struct mx3_cpu_type {
108 u8 srev;
2f22045b 109 u32 v;
4adaf9bf 110};
2cf36ae7 111
f76888c2
SB		 112#define IOMUX_PADNUM_MASK 0x1ff
113#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
114
115/*
116 * various IOMUX pad functions
117 */
118enum iomux_pad_config {
119 PAD_CTL_NOLOOPBACK = 0x0 << 9,
120 PAD_CTL_LOOPBACK = 0x1 << 9,
121 PAD_CTL_PKE_NONE = 0x0 << 8,
122 PAD_CTL_PKE_ENABLE = 0x1 << 8,
123 PAD_CTL_PUE_KEEPER = 0x0 << 7,
124 PAD_CTL_PUE_PUD = 0x1 << 7,
125 PAD_CTL_100K_PD = 0x0 << 5,
126 PAD_CTL_100K_PU = 0x1 << 5,
127 PAD_CTL_47K_PU = 0x2 << 5,
128 PAD_CTL_22K_PU = 0x3 << 5,
129 PAD_CTL_HYS_CMOS = 0x0 << 4,
130 PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
131 PAD_CTL_ODE_CMOS = 0x0 << 3,
132 PAD_CTL_ODE_OpenDrain = 0x1 << 3,
133 PAD_CTL_DRV_NORMAL = 0x0 << 1,
134 PAD_CTL_DRV_HIGH = 0x1 << 1,
135 PAD_CTL_DRV_MAX = 0x2 << 1,
136 PAD_CTL_SRE_SLOW = 0x0 << 0,
137 PAD_CTL_SRE_FAST = 0x1 << 0
138};
139
140/*
141 * This enumeration is constructed based on the Section
142 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
143 * value is constructed based on the rules described above.
144 */
145
146enum iomux_pins {
147 MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0),
148 MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1),
149 MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2),
150 MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3),
151 MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4),
152 MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5),
153 MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6),
154 MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7),
155 MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8),
156 MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9),
157 MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10),
158 MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11),
159 MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12),
160 MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13),
161 MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14),
162 MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15),
163 MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16),
164 MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17),
165 MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18),
166 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
167 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
168 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
169 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
170 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
171 MX31_PIN_READ = IOMUX_PIN(0xff, 24),
172 MX31_PIN_WRITE = IOMUX_PIN(0xff, 25),
173 MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26),
174 MX31_PIN_SER_RS = IOMUX_PIN(89, 27),
175 MX31_PIN_LCS1 = IOMUX_PIN(88, 28),
176 MX31_PIN_LCS0 = IOMUX_PIN(87, 29),
177 MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30),
178 MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31),
179 MX31_PIN_SD_D_I = IOMUX_PIN(84, 32),
180 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
181 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
182 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
183 MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36),
184 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
185 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
186 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
187 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
188 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
189 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
190 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
191 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
192 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
193 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
194 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
195 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
196 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
197 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
198 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
199 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
200 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
201 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
202 MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55),
203 MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56),
204 MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57),
205 MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58),
206 MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59),
207 MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60),
208 MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61),
209 MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62),
210 MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63),
211 MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64),
212 MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65),
213 MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66),
214 MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67),
215 MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68),
216 MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69),
217 MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70),
218 MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71),
219 MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72),
220 MX31_PIN_USB_BYP = IOMUX_PIN(31, 73),
221 MX31_PIN_USB_OC = IOMUX_PIN(30, 74),
222 MX31_PIN_USB_PWR = IOMUX_PIN(29, 75),
223 MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76),
224 MX31_PIN_DE_B = IOMUX_PIN(0xff, 77),
225 MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78),
226 MX31_PIN_TDO = IOMUX_PIN(0xff, 79),
227 MX31_PIN_TDI = IOMUX_PIN(0xff, 80),
228 MX31_PIN_TMS = IOMUX_PIN(0xff, 81),
229 MX31_PIN_TCK = IOMUX_PIN(0xff, 82),
230 MX31_PIN_RTCK = IOMUX_PIN(0xff, 83),
231 MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84),
232 MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85),
233 MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86),
234 MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87),
235 MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88),
236 MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89),
237 MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90),
238 MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91),
239 MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92),
240 MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93),
241 MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94),
242 MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95),
243 MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96),
244 MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97),
245 MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98),
246 MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99),
247 MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100),
248 MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101),
249 MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102),
250 MX31_PIN_TXD2 = IOMUX_PIN(28, 103),
251 MX31_PIN_RXD2 = IOMUX_PIN(27, 104),
252 MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105),
253 MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106),
254 MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107),
255 MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108),
256 MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109),
257 MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110),
258 MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111),
259 MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112),
260 MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113),
261 MX31_PIN_CTS1 = IOMUX_PIN(39, 114),
262 MX31_PIN_RTS1 = IOMUX_PIN(38, 115),
263 MX31_PIN_TXD1 = IOMUX_PIN(37, 116),
264 MX31_PIN_RXD1 = IOMUX_PIN(36, 117),
265 MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118),
266 MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119),
267 MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120),
268 MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121),
269 MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122),
270 MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123),
271 MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124),
272 MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125),
273 MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126),
274 MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127),
275 MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),
276 MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129),
277 MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130),
278 MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131),
279 MX31_PIN_SFS6 = IOMUX_PIN(26, 132),
280 MX31_PIN_SCK6 = IOMUX_PIN(25, 133),
281 MX31_PIN_SRXD6 = IOMUX_PIN(24, 134),
282 MX31_PIN_STXD6 = IOMUX_PIN(23, 135),
283 MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136),
284 MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137),
285 MX31_PIN_SRXD5 = IOMUX_PIN(22, 138),
286 MX31_PIN_STXD5 = IOMUX_PIN(21, 139),
287 MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140),
288 MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141),
289 MX31_PIN_SRXD4 = IOMUX_PIN(20, 142),
290 MX31_PIN_STXD4 = IOMUX_PIN(19, 143),
291 MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144),
292 MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145),
293 MX31_PIN_SRXD3 = IOMUX_PIN(18, 146),
294 MX31_PIN_STXD3 = IOMUX_PIN(17, 147),
295 MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148),
296 MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149),
297 MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150),
298 MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151),
299 MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152),
300 MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153),
301 MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154),
302 MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155),
303 MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156),
304 MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157),
305 MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158),
306 MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159),
307 MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160),
308 MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161),
309 MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162),
310 MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163),
311 MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164),
312 MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165),
313 MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166),
314 MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167),
315 MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168),
316 MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169),
317 MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170),
318 MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171),
319 MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172),
320 MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173),
321 MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174),
322 MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175),
323 MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176),
324 MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177),
325 MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178),
326 MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179),
327 MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180),
328 MX31_PIN_D0 = IOMUX_PIN(0xff, 181),
329 MX31_PIN_D1 = IOMUX_PIN(0xff, 182),
330 MX31_PIN_D2 = IOMUX_PIN(0xff, 183),
331 MX31_PIN_D3 = IOMUX_PIN(0xff, 184),
332 MX31_PIN_D4 = IOMUX_PIN(0xff, 185),
333 MX31_PIN_D5 = IOMUX_PIN(0xff, 186),
334 MX31_PIN_D6 = IOMUX_PIN(0xff, 187),
335 MX31_PIN_D7 = IOMUX_PIN(0xff, 188),
336 MX31_PIN_D8 = IOMUX_PIN(0xff, 189),
337 MX31_PIN_D9 = IOMUX_PIN(0xff, 190),
338 MX31_PIN_D10 = IOMUX_PIN(0xff, 191),
339 MX31_PIN_D11 = IOMUX_PIN(0xff, 192),
340 MX31_PIN_D12 = IOMUX_PIN(0xff, 193),
341 MX31_PIN_D13 = IOMUX_PIN(0xff, 194),
342 MX31_PIN_D14 = IOMUX_PIN(0xff, 195),
343 MX31_PIN_D15 = IOMUX_PIN(0xff, 196),
344 MX31_PIN_NFRB = IOMUX_PIN(16, 197),
345 MX31_PIN_NFCE_B = IOMUX_PIN(15, 198),
346 MX31_PIN_NFWP_B = IOMUX_PIN(14, 199),
347 MX31_PIN_NFCLE = IOMUX_PIN(13, 200),
348 MX31_PIN_NFALE = IOMUX_PIN(12, 201),
349 MX31_PIN_NFRE_B = IOMUX_PIN(11, 202),
350 MX31_PIN_NFWE_B = IOMUX_PIN(10, 203),
351 MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204),
352 MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205),
353 MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206),
354 MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207),
355 MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208),
356 MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209),
357 MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210),
358 MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211),
359 MX31_PIN_SDWE = IOMUX_PIN(0xff, 212),
360 MX31_PIN_CAS = IOMUX_PIN(0xff, 213),
361 MX31_PIN_RAS = IOMUX_PIN(0xff, 214),
362 MX31_PIN_RW = IOMUX_PIN(0xff, 215),
363 MX31_PIN_BCLK = IOMUX_PIN(0xff, 216),
364 MX31_PIN_LBA = IOMUX_PIN(0xff, 217),
365 MX31_PIN_ECB = IOMUX_PIN(0xff, 218),
366 MX31_PIN_CS5 = IOMUX_PIN(0xff, 219),
367 MX31_PIN_CS4 = IOMUX_PIN(0xff, 220),
368 MX31_PIN_CS3 = IOMUX_PIN(0xff, 221),
369 MX31_PIN_CS2 = IOMUX_PIN(0xff, 222),
370 MX31_PIN_CS1 = IOMUX_PIN(0xff, 223),
371 MX31_PIN_CS0 = IOMUX_PIN(0xff, 224),
372 MX31_PIN_OE = IOMUX_PIN(0xff, 225),
373 MX31_PIN_EB1 = IOMUX_PIN(0xff, 226),
374 MX31_PIN_EB0 = IOMUX_PIN(0xff, 227),
375 MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228),
376 MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229),
377 MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230),
378 MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231),
379 MX31_PIN_SD31 = IOMUX_PIN(0xff, 232),
380 MX31_PIN_SD30 = IOMUX_PIN(0xff, 233),
381 MX31_PIN_SD29 = IOMUX_PIN(0xff, 234),
382 MX31_PIN_SD28 = IOMUX_PIN(0xff, 235),
383 MX31_PIN_SD27 = IOMUX_PIN(0xff, 236),
384 MX31_PIN_SD26 = IOMUX_PIN(0xff, 237),
385 MX31_PIN_SD25 = IOMUX_PIN(0xff, 238),
386 MX31_PIN_SD24 = IOMUX_PIN(0xff, 239),
387 MX31_PIN_SD23 = IOMUX_PIN(0xff, 240),
388 MX31_PIN_SD22 = IOMUX_PIN(0xff, 241),
389 MX31_PIN_SD21 = IOMUX_PIN(0xff, 242),
390 MX31_PIN_SD20 = IOMUX_PIN(0xff, 243),
391 MX31_PIN_SD19 = IOMUX_PIN(0xff, 244),
392 MX31_PIN_SD18 = IOMUX_PIN(0xff, 245),
393 MX31_PIN_SD17 = IOMUX_PIN(0xff, 246),
394 MX31_PIN_SD16 = IOMUX_PIN(0xff, 247),
395 MX31_PIN_SD15 = IOMUX_PIN(0xff, 248),
396 MX31_PIN_SD14 = IOMUX_PIN(0xff, 249),
397 MX31_PIN_SD13 = IOMUX_PIN(0xff, 250),
398 MX31_PIN_SD12 = IOMUX_PIN(0xff, 251),
399 MX31_PIN_SD11 = IOMUX_PIN(0xff, 252),
400 MX31_PIN_SD10 = IOMUX_PIN(0xff, 253),
401 MX31_PIN_SD9 = IOMUX_PIN(0xff, 254),
402 MX31_PIN_SD8 = IOMUX_PIN(0xff, 255),
403 MX31_PIN_SD7 = IOMUX_PIN(0xff, 256),
404 MX31_PIN_SD6 = IOMUX_PIN(0xff, 257),
405 MX31_PIN_SD5 = IOMUX_PIN(0xff, 258),
406 MX31_PIN_SD4 = IOMUX_PIN(0xff, 259),
407 MX31_PIN_SD3 = IOMUX_PIN(0xff, 260),
408 MX31_PIN_SD2 = IOMUX_PIN(0xff, 261),
409 MX31_PIN_SD1 = IOMUX_PIN(0xff, 262),
410 MX31_PIN_SD0 = IOMUX_PIN(0xff, 263),
411 MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264),
412 MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265),
413 MX31_PIN_A25 = IOMUX_PIN(0xff, 266),
414 MX31_PIN_A24 = IOMUX_PIN(0xff, 267),
415 MX31_PIN_A23 = IOMUX_PIN(0xff, 268),
416 MX31_PIN_A22 = IOMUX_PIN(0xff, 269),
417 MX31_PIN_A21 = IOMUX_PIN(0xff, 270),
418 MX31_PIN_A20 = IOMUX_PIN(0xff, 271),
419 MX31_PIN_A19 = IOMUX_PIN(0xff, 272),
420 MX31_PIN_A18 = IOMUX_PIN(0xff, 273),
421 MX31_PIN_A17 = IOMUX_PIN(0xff, 274),
422 MX31_PIN_A16 = IOMUX_PIN(0xff, 275),
423 MX31_PIN_A14 = IOMUX_PIN(0xff, 276),
424 MX31_PIN_A15 = IOMUX_PIN(0xff, 277),
425 MX31_PIN_A13 = IOMUX_PIN(0xff, 278),
426 MX31_PIN_A12 = IOMUX_PIN(0xff, 279),
427 MX31_PIN_A11 = IOMUX_PIN(0xff, 280),
428 MX31_PIN_MA10 = IOMUX_PIN(0xff, 281),
429 MX31_PIN_A10 = IOMUX_PIN(0xff, 282),
430 MX31_PIN_A9 = IOMUX_PIN(0xff, 283),
431 MX31_PIN_A8 = IOMUX_PIN(0xff, 284),
432 MX31_PIN_A7 = IOMUX_PIN(0xff, 285),
433 MX31_PIN_A6 = IOMUX_PIN(0xff, 286),
434 MX31_PIN_A5 = IOMUX_PIN(0xff, 287),
435 MX31_PIN_A4 = IOMUX_PIN(0xff, 288),
436 MX31_PIN_A3 = IOMUX_PIN(0xff, 289),
437 MX31_PIN_A2 = IOMUX_PIN(0xff, 290),
438 MX31_PIN_A1 = IOMUX_PIN(0xff, 291),
439 MX31_PIN_A0 = IOMUX_PIN(0xff, 292),
440 MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293),
441 MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294),
442 MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295),
443 MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296),
444 MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297),
445 MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298),
446 MX31_PIN_CKIL = IOMUX_PIN(0xff, 299),
447 MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300),
448 MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301),
449 MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302),
450 MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303),
451 MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304),
452 MX31_PIN_CLKO = IOMUX_PIN(0xff, 305),
453 MX31_PIN_POR_B = IOMUX_PIN(0xff, 306),
454 MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307),
455 MX31_PIN_CKIH = IOMUX_PIN(0xff, 308),
456 MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309),
457 MX31_PIN_SRX0 = IOMUX_PIN(34, 310),
458 MX31_PIN_STX0 = IOMUX_PIN(33, 311),
459 MX31_PIN_SVEN0 = IOMUX_PIN(32, 312),
460 MX31_PIN_SRST0 = IOMUX_PIN(67, 313),
461 MX31_PIN_SCLK0 = IOMUX_PIN(66, 314),
462 MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315),
463 MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316),
464 MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317),
465 MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318),
466 MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319),
467 MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320),
468 MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321),
469 MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322),
470 MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323),
471 MX31_PIN_PWMO = IOMUX_PIN(9, 324),
472 MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325),
473 MX31_PIN_COMPARE = IOMUX_PIN(8, 326),
474 MX31_PIN_CAPTURE = IOMUX_PIN(7, 327),
475};
c4ea1424 476
6d0fb3db
FE		 477/*
478 * various IOMUX general purpose functions
479 */
480enum iomux_gp_func {
481 MUX_PGP_FIRI = 1 << 0,
482 MUX_DDR_MODE = 1 << 1,
483 MUX_PGP_CSPI_BB = 1 << 2,
484 MUX_PGP_ATA_1 = 1 << 3,
485 MUX_PGP_ATA_2 = 1 << 4,
486 MUX_PGP_ATA_3 = 1 << 5,
487 MUX_PGP_ATA_4 = 1 << 6,
488 MUX_PGP_ATA_5 = 1 << 7,
489 MUX_PGP_ATA_6 = 1 << 8,
490 MUX_PGP_ATA_7 = 1 << 9,
491 MUX_PGP_ATA_8 = 1 << 10,
492 MUX_PGP_UH2 = 1 << 11,
493 MUX_SDCTL_CSD0_SEL = 1 << 12,
494 MUX_SDCTL_CSD1_SEL = 1 << 13,
495 MUX_CSPI1_UART3 = 1 << 14,
496 MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
497 MUX_TAMPER_DETECT_EN = 1 << 16,
498 MUX_PGP_USB_4WIRE = 1 << 17,
499 MUX_PGP_USB_COMMON = 1 << 18,
500 MUX_SDHC_MEMSTICK1 = 1 << 19,
501 MUX_SDHC_MEMSTICK2 = 1 << 20,
502 MUX_PGP_SPLL_BYP = 1 << 21,
503 MUX_PGP_UPLL_BYP = 1 << 22,
504 MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
505 MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
506 MUX_CSPI3_UART5_SEL = 1 << 25,
507 MUX_PGP_ATA_9 = 1 << 26,
508 MUX_PGP_USB_SUSPEND = 1 << 27,
509 MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
510 MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
511 MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
512 MUX_CLKO_DDR_MODE = 1 << 31,
513};
514
c816dcb1
ML		 515/* Bit definitions for RCSR register in CCM */
516#define CCM_RCSR_NF16B (1 << 31)
517#define CCM_RCSR_NFMS (1 << 30)
518
47c5455a
HR		 519/* WEIM CS control registers */
520struct mx31_weim_cscr {
521 u32 upper;
522 u32 lower;
523 u32 additional;
524 u32 reserved;
525};
526
527struct mx31_weim {
528 struct mx31_weim_cscr cscr[6];
529};
530
a6d9de43
HR		 531/* ESD control registers */
532struct esdc_regs {
533 u32 ctl0;
534 u32 cfg0;
535 u32 ctl1;
536 u32 cfg1;
537 u32 misc;
538 u32 dly[5];
539 u32 dlyl;
540};
541
c816dcb1
ML		 542#endif
543
9b56f4f0
SH		 544#define __REG(x) (*((volatile u32 *)(x)))
545#define __REG16(x) (*((volatile u16 *)(x)))
546#define __REG8(x) (*((volatile u8 *)(x)))
547
548#define CCM_BASE 0x53f80000
549#define CCM_CCMR (CCM_BASE + 0x00)
550#define CCM_PDR0 (CCM_BASE + 0x04)
551#define CCM_PDR1 (CCM_BASE + 0x08)
552#define CCM_RCSR (CCM_BASE + 0x0c)
553#define CCM_MPCTL (CCM_BASE + 0x10)
68553364 554#define CCM_UPCTL (CCM_BASE + 0x14)
9b56f4f0
SH		 555#define CCM_SPCTL (CCM_BASE + 0x18)
556#define CCM_COSR (CCM_BASE + 0x1C)
38254f45
GL		 557#define CCM_CGR0 (CCM_BASE + 0x20)
558#define CCM_CGR1 (CCM_BASE + 0x24)
559#define CCM_CGR2 (CCM_BASE + 0x28)
9b56f4f0
SH		 560
561#define CCMR_MDS (1 << 7)
562#define CCMR_SBYCS (1 << 4)
563#define CCMR_MPE (1 << 3)
564#define CCMR_PRCS_MASK (3 << 1)
565#define CCMR_FPM (1 << 1)
566#define CCMR_CKIH (2 << 1)
567
4adaf9bf
FE		 568#define MX31_IIM_BASE_ADDR 0x5001C000
569
9b56f4f0
SH		 570#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
571#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
572#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
573#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
574#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
575#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
576#define PDR0_MCU_PODF(x) ((x) & 0x7)
577
578#define PLL_PD(x) (((x) & 0xf) << 26)
579#define PLL_MFD(x) (((x) & 0x3ff) << 16)
580#define PLL_MFI(x) (((x) & 0xf) << 10)
581#define PLL_MFN(x) (((x) & 0x3ff) << 0)
582
f0029198
HR		 583#define GET_PDR0_CSI_PODF(x) (((x) >> 23) & 0x1ff)
584#define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f)
585#define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7)
586#define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7)
587#define GET_PDR0_IPG_PODF(x) (((x) >> 6) & 0x3)
588#define GET_PDR0_MAX_PODF(x) (((x) >> 3) & 0x7)
589#define GET_PDR0_MCU_PODF(x) ((x) & 0x7)
590
591#define GET_PLL_PD(x) (((x) >> 26) & 0xf)
592#define GET_PLL_MFD(x) (((x) >> 16) & 0x3ff)
593#define GET_PLL_MFI(x) (((x) >> 10) & 0xf)
594#define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff)
595
596
d08e5ca3
ML		 597#define WEIM_ESDCTL0 0xB8001000
598#define WEIM_ESDCFG0 0xB8001004
599#define WEIM_ESDCTL1 0xB8001008
600#define WEIM_ESDCFG1 0xB800100C
601#define WEIM_ESDMISC 0xB8001010
602
40f6fffe
SB		 603#define UART1_BASE 0x43F90000
604#define UART2_BASE 0x43F94000
605#define UART3_BASE 0x5000C000
606#define UART4_BASE 0x43FB0000
607#define UART5_BASE 0x43FB4000
608
de6f604d
TK		 609#define I2C1_BASE_ADDR 0x43f80000
610#define I2C1_CLK_OFFSET 26
611#define I2C2_BASE_ADDR 0x43F98000
612#define I2C2_CLK_OFFSET 28
613#define I2C3_BASE_ADDR 0x43f84000
614#define I2C3_CLK_OFFSET 30
615
d08e5ca3
ML		 616#define ESDCTL_SDE (1 << 31)
617#define ESDCTL_CMD_RW (0 << 28)
618#define ESDCTL_CMD_PRECHARGE (1 << 28)
619#define ESDCTL_CMD_AUTOREFRESH (2 << 28)
620#define ESDCTL_CMD_LOADMODEREG (3 << 28)
621#define ESDCTL_CMD_MANUALREFRESH (4 << 28)
622#define ESDCTL_ROW_13 (2 << 24)
623#define ESDCTL_ROW(x) ((x) << 24)
624#define ESDCTL_COL_9 (1 << 20)
625#define ESDCTL_COL(x) ((x) << 20)
626#define ESDCTL_DSIZ(x) ((x) << 16)
627#define ESDCTL_SREFR(x) ((x) << 13)
628#define ESDCTL_PWDT(x) ((x) << 10)
629#define ESDCTL_FP(x) ((x) << 8)
630#define ESDCTL_BL(x) ((x) << 7)
631#define ESDCTL_PRCT(x) ((x) << 0)
632
a6d9de43
HR		 633#define ESDCTL_BASE_ADDR 0xB8001000
634
47c5455a
HR		 635/* 13 fields of the upper CS control register */
636#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
637 cnc, wsc, ew, wws, edc) \
638 ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\
639 (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\
640 (wws) << 4 | (edc) << 0)
641/* 12 fields of the lower CS control register */
642#define CSCR_L(oea, oen, ebwa, ebwn, \
643 csa, ebc, dsz, csn, psr, cre, wrap, csen) \
644 ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
645 (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
646 (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
647/* 14 fields of the additional CS control register */
648#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
649 wwu, age, cnc2, fce) \
650 ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
651 (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
652 (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
653 (age) << 2 | (cnc2) << 1 | (fce) << 0)
654
9b56f4f0 655#define WEIM_BASE 0xb8002000
9b56f4f0
SH		 656
657#define IOMUXC_BASE 0x43FAC000
9b56f4f0
SH		 658#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
659#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
660
661#define IPU_BASE 0x53fc0000
662#define IPU_CONF IPU_BASE
663
664#define IPU_CONF_PXL_ENDIAN (1<<8)
665#define IPU_CONF_DU_EN (1<<7)
666#define IPU_CONF_DI_EN (1<<6)
667#define IPU_CONF_ADC_EN (1<<5)
668#define IPU_CONF_SDC_EN (1<<4)
669#define IPU_CONF_PF_EN (1<<3)
670#define IPU_CONF_ROT_EN (1<<2)
671#define IPU_CONF_IC_EN (1<<1)
672#define IPU_CONF_SCI_EN (1<<0)
673
8449f287
ML		 674#define ARM_PPMRR 0x40000015
675
9b56f4f0
SH		 676#define WDOG_BASE 0x53FDC000
677
54dc5173
IY		 678/*
679 * GPIO
680 */
c4ea1424
SB		 681#define GPIO1_BASE_ADDR 0x53FCC000
682#define GPIO2_BASE_ADDR 0x53FD0000
683#define GPIO3_BASE_ADDR 0x53FA4000
54dc5173
IY		 684#define GPIO_DR 0x00000000 /* data register */
685#define GPIO_GDIR 0x00000004 /* direction register */
686#define GPIO_PSR 0x00000008 /* pad status register */
687
9b56f4f0
SH		 688/*
689 * Signal Multiplexing (IOMUX)
690 */
691
692/* bits in the SW_MUX_CTL registers */
693#define MUX_CTL_OUT_GPIO_DR (0 << 4)
694#define MUX_CTL_OUT_FUNC (1 << 4)
695#define MUX_CTL_OUT_ALT1 (2 << 4)
696#define MUX_CTL_OUT_ALT2 (3 << 4)
697#define MUX_CTL_OUT_ALT3 (4 << 4)
698#define MUX_CTL_OUT_ALT4 (5 << 4)
699#define MUX_CTL_OUT_ALT5 (6 << 4)
700#define MUX_CTL_OUT_ALT6 (7 << 4)
701#define MUX_CTL_IN_NONE (0 << 0)
702#define MUX_CTL_IN_GPIO (1 << 0)
703#define MUX_CTL_IN_FUNC (2 << 0)
704#define MUX_CTL_IN_ALT1 (4 << 0)
705#define MUX_CTL_IN_ALT2 (8 << 0)
706
707#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
708#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
709#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
710#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
711
712/* Register offsets based on IOMUXC_BASE */
713/* 0x00 .. 0x7b */
d121d201
HR		 714#define MUX_CTL_CSPI3_MISO 0x0c
715#define MUX_CTL_CSPI3_SCLK 0x0d
716#define MUX_CTL_CSPI3_SPI_RDY 0x0e
717#define MUX_CTL_CSPI3_MOSI 0x13
718
fa47a286
HR		 719#define MUX_CTL_SD1_DATA1 0x18
720#define MUX_CTL_SD1_DATA2 0x19
721#define MUX_CTL_SD1_DATA3 0x1a
722#define MUX_CTL_SD1_CMD 0x1d
723#define MUX_CTL_SD1_CLK 0x1e
724#define MUX_CTL_SD1_DATA0 0x1f
725
f76888c2
SB		 726#define MUX_CTL_USBH2_DATA1 0x40
727#define MUX_CTL_USBH2_DIR 0x44
728#define MUX_CTL_USBH2_STP 0x45
729#define MUX_CTL_USBH2_NXT 0x46
730#define MUX_CTL_USBH2_DATA0 0x47
731#define MUX_CTL_USBH2_CLK 0x4B
d121d201
HR		 732
733#define MUX_CTL_TXD2 0x70
734#define MUX_CTL_RTS2 0x71
735#define MUX_CTL_CTS2 0x72
736#define MUX_CTL_RXD2 0x77
737
9b56f4f0
SH		 738#define MUX_CTL_RTS1 0x7c
739#define MUX_CTL_CTS1 0x7d
740#define MUX_CTL_DTR_DCE1 0x7e
741#define MUX_CTL_DSR_DCE1 0x7f
742#define MUX_CTL_CSPI2_SCLK 0x80
743#define MUX_CTL_CSPI2_SPI_RDY 0x81
744#define MUX_CTL_RXD1 0x82
745#define MUX_CTL_TXD1 0x83
746#define MUX_CTL_CSPI2_MISO 0x84
38254f45
GL		 747#define MUX_CTL_CSPI2_SS0 0x85
748#define MUX_CTL_CSPI2_SS1 0x86
749#define MUX_CTL_CSPI2_SS2 0x87
a2bb7105
GL		 750#define MUX_CTL_CSPI1_SS2 0x88
751#define MUX_CTL_CSPI1_SCLK 0x89
752#define MUX_CTL_CSPI1_SPI_RDY 0x8a
9b56f4f0 753#define MUX_CTL_CSPI2_MOSI 0x8b
a2bb7105
GL		 754#define MUX_CTL_CSPI1_MOSI 0x8c
755#define MUX_CTL_CSPI1_MISO 0x8d
756#define MUX_CTL_CSPI1_SS0 0x8e
757#define MUX_CTL_CSPI1_SS1 0x8f
70e23264
SB		 758#define MUX_CTL_STXD6 0x90
759#define MUX_CTL_SRXD6 0x91
760#define MUX_CTL_SCK6 0x92
761#define MUX_CTL_SFS6 0x93
9b56f4f0 762
f76888c2
SB		 763#define MUX_CTL_STXD3 0x9C
764#define MUX_CTL_SRXD3 0x9D
765#define MUX_CTL_SCK3 0x9E
766#define MUX_CTL_SFS3 0x9F
767
efb95910
SB		 768#define MUX_CTL_NFC_WP 0xD0
769#define MUX_CTL_NFC_CE 0xD1
770#define MUX_CTL_NFC_RB 0xD2
771#define MUX_CTL_NFC_WE 0xD4
772#define MUX_CTL_NFC_RE 0xD5
773#define MUX_CTL_NFC_ALE 0xD6
774#define MUX_CTL_NFC_CLE 0xD7
775
776
70e23264
SB		 777#define MUX_CTL_CAPTURE 0x150
778#define MUX_CTL_COMPARE 0x151
779
5276a358
ML		 780/*
781 * Helper macros for the MUX_[contact name]__[pin function] macros
9b56f4f0 782 */
5276a358
ML		 783#define IOMUX_MODE_POS 9
784#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
9b56f4f0 785
5276a358
ML		 786/*
787 * These macros can be used in mx31_gpio_mux() and have the form
788 * MUX_[contact name]__[pin function]
789 */
790#define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
791#define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
792#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
793#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
794
d121d201
HR		 795#define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC)
796#define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC)
797#define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC)
798#define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC)
799
5276a358
ML		 800#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
801#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
802#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
803#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
804#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
805#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
806 IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
807#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
808
a2bb7105
GL		 809#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
810#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
811#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
812#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
813#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
814#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
815 IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
816#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
817
5276a358
ML		 818#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
819#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
9b56f4f0 820
d08e5ca3
ML		 821/* PAD control registers for SDR/DDR */
822#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
823#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)
824#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)
825#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)
826#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)
827#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)
828#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)
829#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288)
830#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C)
831#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290)
832#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294)
833#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298)
834#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C)
835#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0)
836#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4)
837#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8)
838#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC)
839#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0)
840#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4)
841#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8)
842#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC)
843#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0)
844#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4)
845#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8)
846#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC)
847#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0)
848#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4)
849#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8)
850#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC)
851
b5dc9b30
GL		 852/*
853 * Memory regions and CS
854 */
855#define IPU_MEM_BASE 0x70000000
856#define CSD0_BASE 0x80000000
857#define CSD1_BASE 0x90000000
858#define CS0_BASE 0xA0000000
859#define CS1_BASE 0xA8000000
860#define CS2_BASE 0xB0000000
861#define CS3_BASE 0xB2000000
862#define CS4_BASE 0xB4000000
863#define CS4_PSRAM_BASE 0xB5000000
864#define CS5_BASE 0xB6000000
865#define PCMCIA_MEM_BASE 0xC0000000
9b56f4f0 866
40c642bc
ML		 867/*
868 * NAND controller
869 */
870#define NFC_BASE_ADDR 0xB8000000
871
fa47a286
HR		 872/* SD card controller */
873#define SDHC1_BASE_ADDR 0x50004000
874#define SDHC2_BASE_ADDR 0x50008000
875
eab40f81
SB		 876/*
877 * Internal RAM (16KB)
878 */
879#define IRAM_BASE_ADDR 0x1FFFC000
880#define IRAM_SIZE (16 * 1024)
881
f76888c2 882#define MX31_AIPS1_BASE_ADDR 0x43f00000
dddb7c9f 883#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)
f76888c2
SB		 884
885/* USB portsc */
886/* values for portsc field */
887#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
888#define MXC_EHCI_FORCE_FS (1 << 24)
889#define MXC_EHCI_UTMI_8BIT (0 << 28)
890#define MXC_EHCI_UTMI_16BIT (1 << 28)
891#define MXC_EHCI_SERIAL (1 << 29)
892#define MXC_EHCI_MODE_UTMI (0 << 30)
893#define MXC_EHCI_MODE_PHILIPS (1 << 30)
894#define MXC_EHCI_MODE_ULPI (2 << 30)
895#define MXC_EHCI_MODE_SERIAL (3 << 30)
896
897/* values for flags field */
898#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
899#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
900#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
901#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
902#define MXC_EHCI_INTERFACE_MASK (0xf)
903
904#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
905#define MXC_EHCI_TTL_ENABLED (1 << 6)
906
907#define MXC_EHCI_INTERNAL_PHY (1 << 7)
908#define MXC_EHCI_IPPUE_DOWN (1 << 8)
909#define MXC_EHCI_IPPUE_UP (1 << 9)
910
08c61a58
EN		 911/*
912 * CSPI register definitions
913 */
914#define MXC_CSPI
915#define MXC_CSPICTRL_EN (1 << 0)
916#define MXC_CSPICTRL_MODE (1 << 1)
917#define MXC_CSPICTRL_XCH (1 << 2)
918#define MXC_CSPICTRL_SMC (1 << 3)
919#define MXC_CSPICTRL_POL (1 << 4)
920#define MXC_CSPICTRL_PHA (1 << 5)
921#define MXC_CSPICTRL_SSCTL (1 << 6)
922#define MXC_CSPICTRL_SSPOL (1 << 7)
923#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
924#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
925#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
926#define MXC_CSPICTRL_TC (1 << 8)
927#define MXC_CSPICTRL_RXOVF (1 << 6)
928#define MXC_CSPICTRL_MAXBITS 0x1f
929
930#define MXC_CSPIPERIOD_32KHZ (1 << 15)
931#define MAX_SPI_BYTES 4
932
933#define MXC_SPI_BASE_ADDRESSES \
934 0x43fa4000, \
935 0x50010000, \
936 0x53f84000,
937
a770975a 938#endif /* __ASM_ARCH_MX31_IMX_REGS_H */
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