[J-u-boot.git] / board / mpc8540eval / mpc8540eval.c

/*
 * (C) Copyright 2002,2003, Motorola Inc.
 * Xianghua Xiao, ([email protected])
 *
 * (C) Copyright 2002 Scott McNutt <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>

extern long int spd_sdram (void);

long int fixed_sdram (void);

int board_pre_init (void)
{
#if defined(CONFIG_PCI)
	volatile immap_t *immr = (immap_t *)CFG_IMMR;
	volatile ccsr_pcix_t *pci = &immr->im_pcix;

	pci->peer &= 0xffffffdf; /* disable master abort */
#endif
	return 0;
}

int checkboard (void)
{
	sys_info_t sysinfo;

	get_sys_info (&sysinfo);

	printf ("Board: Freescale MPC8540EVAL Board\n");
	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
		|| (CFG_LBC_LCRR & 0x0f) == 8) {
		printf ("\tLBC: %lu MHz\n",
			sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
	} else {
		printf("\tLBC: unknown\n");
	}
	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
	return (0);
}

long int initdram (int board_type)
{
	long dram_size = 0;
	extern long spd_sdram (void);
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
#if !defined(CONFIG_RAM_AS_FLASH)
	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
	sys_info_t sysinfo;
	uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
	volatile ccsr_gur_t *gur= &immap->im_gur;
#endif

#if defined(CONFIG_DDR_DLL)
	uint temp_ddrdll = 0;

	/* Work around to stabilize DDR DLL */
	temp_ddrdll = gur->ddrdllcr;
	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
	asm("sync;isync;msync");
#endif

#if defined(CONFIG_SPD_EEPROM)
	dram_size = spd_sdram ();
#else
	dram_size = fixed_sdram ();
#endif

#if defined(CFG_RAMBOOT)
	return dram_size;
#endif

#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
	get_sys_info(&sysinfo);
	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
	} else {
		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
		udelay(200);
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
		asm("sync;isync;msync");
	}
	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
	lbc->br2 = CFG_BR2_PRELIM;
	lbc->lbcr = CFG_LBC_LBCR;
	lbc->lsdmr = CFG_LBC_LSDMR_1;
	asm("sync");
	* (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CFG_LBC_LSDMR_2;
	asm("sync");
	* (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CFG_LBC_LSDMR_3;
	asm("sync");
	* (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CFG_LBC_LSDMR_4;
	asm("sync");
	* (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CFG_LBC_LSDMR_5;
	asm("sync");
	lbc->lsrt = CFG_LBC_LSRT;
	asm("sync");
	lbc->mrtpr = CFG_LBC_MRTPR;
	asm("sync");
#endif

#if defined(CONFIG_DDR_ECC)
	{
		/* Initialize all of memory for ECC, then
		 * enable errors */
		uint *p = 0;
		uint i = 0;
		volatile immap_t *immap = (immap_t *)CFG_IMMR;
		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
		dma_init();
		for (*p = 0; p < (uint *)(8 * 1024); p++) {
			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
			*p = (unsigned int)0xdeadbeef;
			if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
		}

		/* 8K */
		dma_xfer((uint *)0x2000,0x2000,(uint *)0);
		/* 16K */
		dma_xfer((uint *)0x4000,0x4000,(uint *)0);
		/* 32K */
		dma_xfer((uint *)0x8000,0x8000,(uint *)0);
		/* 64K */
		dma_xfer((uint *)0x10000,0x10000,(uint *)0);
		/* 128k */
		dma_xfer((uint *)0x20000,0x20000,(uint *)0);
		/* 256k */
		dma_xfer((uint *)0x40000,0x40000,(uint *)0);
		/* 512k */
		dma_xfer((uint *)0x80000,0x80000,(uint *)0);
		/* 1M */
		dma_xfer((uint *)0x100000,0x100000,(uint *)0);
		/* 2M */
		dma_xfer((uint *)0x200000,0x200000,(uint *)0);
		/* 4M */
		dma_xfer((uint *)0x400000,0x400000,(uint *)0);

		for (i = 1; i < dram_size / 0x800000; i++) {
			dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
		}

		/* Enable errors for ECC */
		ddr->err_disable = 0x00000000;
		asm("sync;isync;msync");
	}
#endif

	return dram_size;
}

#if defined(CFG_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) CFG_MEMTEST_START;
	uint *pend = (uint *) CFG_MEMTEST_END;
	uint *p;

	printf("SDRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("SDRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("SDRAM test passed.\n");
	return 0;
}
#endif

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_ddr_t *ddr= &immap->im_ddr;

	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
	ddr->sdram_mode = CFG_DDR_MODE;
	ddr->sdram_interval = CFG_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC)
	ddr->err_disable = 0x0000000D;
	ddr->err_sbe = 0x00ff0000;
#endif
	asm("sync;isync;msync");
	udelay(500);
#if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
#else
	ddr->sdram_cfg = CFG_DDR_CONTROL;
#endif
	asm("sync; isync; msync");
	udelay(500);
#endif
	return (CFG_SDRAM_SIZE * 1024 * 1024);
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */
Commit	Line	Data
b0e32949 LW	1	/*
	2	* (C) Copyright 2002,2003, Motorola Inc.
	3	* Xianghua Xiao, ([email protected])
	4	*
	5	* (C) Copyright 2002 Scott McNutt <[email protected]>
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
b0e32949 LW	26	#include <common.h>
	27	#include <asm/processor.h>
	28	#include <asm/immap_85xx.h>
	29	#include <spd.h>
	30
de1d0a69	31	extern long int spd_sdram (void);
b0e32949 LW	32
	33	long int fixed_sdram (void);
	34
b0e32949 LW	35	int board_pre_init (void)
	36	{
	37	#if defined(CONFIG_PCI)
	38	volatile immap_t immr = (immap_t )CFG_IMMR;
	39	volatile ccsr_pcix_t *pci = &immr->im_pcix;
	40
	41	pci->peer &= 0xffffffdf; /* disable master abort */
	42	#endif
	43	return 0;
	44	}
	45
	46	int checkboard (void)
	47	{
	48	sys_info_t sysinfo;
	49
	50	get_sys_info (&sysinfo);
	51
	52	printf ("Board: Freescale MPC8540EVAL Board\n");
	53	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
	54	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
	55	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
	56	if((CFG_LBC_LCRR & 0x0f) == 2 \|\| (CFG_LBC_LCRR & 0x0f) == 4 \
	57	\|\| (CFG_LBC_LCRR & 0x0f) == 8) {
de1d0a69 JL	58	printf ("\tLBC: %lu MHz\n",
de1d0a69 JL	59	sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
b0e32949 LW	60	} else {
	61	printf("\tLBC: unknown\n");
	62	}
	63	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
	64	return (0);
	65	}
	66
	67	long int initdram (int board_type)
	68	{
	69	long dram_size = 0;
	70	extern long spd_sdram (void);
	71	volatile immap_t immap = (immap_t )CFG_IMMR;
	72	#if !defined(CONFIG_RAM_AS_FLASH)
	73	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
	74	sys_info_t sysinfo;
	75	uint temp_lbcdll = 0;
	76	#endif
	77	#if !defined(CONFIG_RAM_AS_FLASH) \|\| defined(CONFIG_DDR_DLL)
	78	volatile ccsr_gur_t *gur= &immap->im_gur;
	79	#endif
	80
	81	#if defined(CONFIG_DDR_DLL)
	82	uint temp_ddrdll = 0;
	83
	84	/* Work around to stabilize DDR DLL */
	85	temp_ddrdll = gur->ddrdllcr;
	86	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) \| 0x80000000;
	87	asm("sync;isync;msync");
	88	#endif
	89
	90	#if defined(CONFIG_SPD_EEPROM)
	91	dram_size = spd_sdram ();
	92	#else
	93	dram_size = fixed_sdram ();
	94	#endif
	95
	96	#if defined(CFG_RAMBOOT)
	97	return dram_size;
	98	#endif
	99
	100	#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
	101	get_sys_info(&sysinfo);
	102	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
	103	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
	104	lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)\| 0x80000000;
	105	} else {
	106	lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
	107	udelay(200);
	108	temp_lbcdll = gur->lbcdllcr;
	109	gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) \| 0x80000000;
	110	asm("sync;isync;msync");
	111	}
	112	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
	113	lbc->br2 = CFG_BR2_PRELIM;
	114	lbc->lbcr = CFG_LBC_LBCR;
	115	lbc->lsdmr = CFG_LBC_LSDMR_1;
	116	asm("sync");
	117	* (ulong *)0 = 0x000000ff;
	118	lbc->lsdmr = CFG_LBC_LSDMR_2;
	119	asm("sync");
	120	* (ulong *)0 = 0x000000ff;
	121	lbc->lsdmr = CFG_LBC_LSDMR_3;
	122	asm("sync");
	123	* (ulong *)0 = 0x000000ff;
124	lbc->lsdmr = CFG_LBC_LSDMR_4;
125	asm("sync");
126	* (ulong *)0 = 0x000000ff;
127	lbc->lsdmr = CFG_LBC_LSDMR_5;
128	asm("sync");
129	lbc->lsrt = CFG_LBC_LSRT;
130	asm("sync");
131	lbc->mrtpr = CFG_LBC_MRTPR;
132	asm("sync");
133	#endif
134
135	#if defined(CONFIG_DDR_ECC)
136	{
137	/* Initialize all of memory for ECC, then
138	* enable errors */
139	uint *p = 0;
140	uint i = 0;
141	volatile immap_t immap = (immap_t )CFG_IMMR;
142	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
143	dma_init();
144	for (p = 0; p < (uint )(8 * 1024); p++) {
145	if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
146	*p = (unsigned int)0xdeadbeef;
147	if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
148	}
149
150	/* 8K */
151	dma_xfer((uint )0x2000,0x2000,(uint )0);
152	/* 16K */
153	dma_xfer((uint )0x4000,0x4000,(uint )0);
154	/* 32K */
155	dma_xfer((uint )0x8000,0x8000,(uint )0);
156	/* 64K */
157	dma_xfer((uint )0x10000,0x10000,(uint )0);
158	/* 128k */
159	dma_xfer((uint )0x20000,0x20000,(uint )0);
160	/* 256k */
161	dma_xfer((uint )0x40000,0x40000,(uint )0);
162	/* 512k */
163	dma_xfer((uint )0x80000,0x80000,(uint )0);
164	/* 1M */
165	dma_xfer((uint )0x100000,0x100000,(uint )0);
166	/* 2M */
167	dma_xfer((uint )0x200000,0x200000,(uint )0);
168	/* 4M */
169	dma_xfer((uint )0x400000,0x400000,(uint )0);
170
171	for (i = 1; i < dram_size / 0x800000; i++) {
172	dma_xfer((uint )(0x800000i),0x800000,(uint *)0);
173	}
174
175	/* Enable errors for ECC */
176	ddr->err_disable = 0x00000000;
177	asm("sync;isync;msync");
178	}
179	#endif
180
181	return dram_size;
182	}
183
b0e32949 LW	184	#if defined(CFG_DRAM_TEST)
	185	int testdram (void)
	186	{
	187	uint pstart = (uint ) CFG_MEMTEST_START;
	188	uint pend = (uint ) CFG_MEMTEST_END;
	189	uint *p;
	190
	191	printf("SDRAM test phase 1:\n");
	192	for (p = pstart; p < pend; p++)
	193	*p = 0xaaaaaaaa;
	194
	195	for (p = pstart; p < pend; p++) {
	196	if (*p != 0xaaaaaaaa) {
	197	printf ("SDRAM test fails at: %08x\n", (uint) p);
	198	return 1;
	199	}
	200	}
	201
	202	printf("SDRAM test phase 2:\n");
	203	for (p = pstart; p < pend; p++)
	204	*p = 0x55555555;
	205
	206	for (p = pstart; p < pend; p++) {
	207	if (*p != 0x55555555) {
	208	printf ("SDRAM test fails at: %08x\n", (uint) p);
	209	return 1;
	210	}
	211	}
	212
	213	printf("SDRAM test passed.\n");
	214	return 0;
	215	}
	216	#endif
	217
b0e32949 LW	218	#if !defined(CONFIG_SPD_EEPROM)
	219	/*************************************************************************
	220	* fixed sdram init -- doesn't use serial presence detect.
	221	************************************************************************/
	222	long int fixed_sdram (void)
	223	{
de1d0a69	224	#ifndef CFG_RAMBOOT
b0e32949 LW	225	volatile immap_t immap = (immap_t )CFG_IMMR;
	226	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
	227
	228	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
	229	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
	230	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
	231	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
	232	ddr->sdram_mode = CFG_DDR_MODE;
	233	ddr->sdram_interval = CFG_DDR_INTERVAL;
de1d0a69	234	#if defined (CONFIG_DDR_ECC)
b0e32949 LW	235	ddr->err_disable = 0x0000000D;
b0e32949 LW	236	ddr->err_sbe = 0x00ff0000;
de1d0a69	237	#endif
b0e32949 LW	238	asm("sync;isync;msync");
b0e32949 LW	239	udelay(500);
de1d0a69	240	#if defined (CONFIG_DDR_ECC)
b0e32949 LW	241	/* Enable ECC checking */
b0e32949 LW	242	ddr->sdram_cfg = (CFG_DDR_CONTROL \| 0x20000000);
de1d0a69	243	#else
b0e32949	244	ddr->sdram_cfg = CFG_DDR_CONTROL;
de1d0a69	245	#endif
b0e32949 LW	246	asm("sync; isync; msync");
b0e32949 LW	247	udelay(500);
de1d0a69	248	#endif
b0e32949 LW	249	return (CFG_SDRAM_SIZE * 1024 * 1024);
	250	}
	251	#endif /* !defined(CONFIG_SPD_EEPROM) */