[J-u-boot.git] / board / technexion / pico-imx7d / spl.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2018 Technexion Ltd.
 *
 * Author: Richard Hu <[email protected]>
 */

#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-mx7/mx7-ddr.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <spl.h>

#if defined(CONFIG_SPL_BUILD)

#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
	/* Break into full U-Boot on 'c' */
	if (serial_tstc() && serial_getc() == 'c')
		return 1;

	return 0;
}
#endif

static struct ddrc ddrc_regs_val = {
	.mstr		= 0x01040001,
	.rfshtmg	= 0x00400046,
	.init1		= 0x00690000,
	.init0		= 0x00020083,
	.init3		= 0x09300004,
	.init4		= 0x04080000,
	.init5		= 0x00100004,
	.rankctl	= 0x0000033F,
	.dramtmg0	= 0x09081109,
	.dramtmg1	= 0x0007020d,
	.dramtmg2	= 0x03040407,
	.dramtmg3	= 0x00002006,
	.dramtmg4	= 0x04020205,
	.dramtmg5	= 0x03030202,
	.dramtmg8	= 0x00000803,
	.zqctl0		= 0x00800020,
	.dfitmg0	= 0x02098204,
	.dfitmg1	= 0x00030303,
	.dfiupd0	= 0x80400003,
	.dfiupd1	= 0x00100020,
	.dfiupd2	= 0x80100004,
	.addrmap4	= 0x00000F0F,
	.odtcfg		= 0x06000604,
	.odtmap		= 0x00000001,
	.rfshtmg	= 0x00400046,
	.dramtmg0	= 0x09081109,
	.addrmap0	= 0x0000001f,
	.addrmap1	= 0x00080808,
	.addrmap2	= 0x00000000,
	.addrmap3	= 0x00000000,
	.addrmap4	= 0x00000f0f,
	.addrmap5	= 0x07070707,
	.addrmap6	= 0x0f0f0707,
};

static struct ddrc_mp ddrc_mp_val = {
	.pctrl_0	= 0x00000001,
};

static struct ddr_phy ddr_phy_regs_val = {
	.phy_con0	= 0x17420f40,
	.phy_con1	= 0x10210100,
	.phy_con4	= 0x00060807,
	.mdll_con0	= 0x1010007e,
	.drvds_con0	= 0x00000d6e,
	.cmd_sdll_con0	= 0x00000010,
	.offset_lp_con0	= 0x0000000f,
	.offset_rd_con0	= 0x08080808,
	.offset_wr_con0	= 0x08080808,
};

static struct mx7_calibration calib_param = {
	.num_val	= 5,
	.values		= {
		0x0E407304,
		0x0E447304,
		0x0E447306,
		0x0E447304,
		0x0E447304,
	},
};

static void gpr_init(void)
{
	struct iomuxc_gpr_base_regs *gpr_regs =
		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
	writel(0x4F400005, &gpr_regs->gpr[1]);
}

/*
 * Revision Detection
 *
 *   GPIO1_12           GPIO1_13
 *     0                0           1GB DDR3
 *     0                1           2GB DDR3
 *     1                0           512MB DDR3
 */

static int imx7d_pico_detect_board(void)
{
	gpio_direction_input(IMX_GPIO_NR(1, 12));
	gpio_direction_input(IMX_GPIO_NR(1, 13));

	return gpio_get_value(IMX_GPIO_NR(1, 12)) << 1 |
	       gpio_get_value(IMX_GPIO_NR(1, 13));
}

static void ddr_init(void)
{
	switch (imx7d_pico_detect_board()) {
	case 0:
		ddrc_regs_val.addrmap6	= 0x0f070707;
		break;
	case 1:
		ddrc_regs_val.addrmap0	= 0x0000001f;
		ddrc_regs_val.addrmap1	= 0x00181818;
		ddrc_regs_val.addrmap4	= 0x00000f0f;
		ddrc_regs_val.addrmap5	= 0x04040404;
		ddrc_regs_val.addrmap6	= 0x04040404;
		break;
	}

	mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
		     &calib_param);
}

void board_init_f(ulong dummy)
{
	arch_cpu_init();
	gpr_init();
	board_early_init_f();
	timer_init();
	preloader_console_init();
	ddr_init();
	memset(__bss_start, 0, __bss_end - __bss_start);
	board_init_r(NULL, 0);
}

void reset_cpu(void)
{
}

#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)

static iomux_v3_cfg_t const usdhc3_pads[] = {
	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};

static struct fsl_esdhc_cfg usdhc_cfg[1] = {
	{USDHC3_BASE_ADDR},
};

int board_mmc_getcd(struct mmc *mmc)
{
	/* Assume uSDHC3 emmc is always present */
	return 1;
}

int board_mmc_init(struct bd_info *bis)
{
	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
#endif
Commit	Line	Data
d5b7177f FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2018 Technexion Ltd.
	4	*
	5	* Author: Richard Hu <[email protected]>
	6	*/
	7
c3dc39a2	8	#include <common.h>
9a3b4ceb	9	#include <cpu_func.h>
691d719d	10	#include <init.h>
4e267b92	11	#include <asm/arch/clock.h>
d5b7177f FE	12	#include <asm/arch/imx-regs.h>
d5b7177f FE	13	#include <asm/arch/crm_regs.h>
4e267b92	14	#include <asm/arch/mx7-pins.h>
d5b7177f FE	15	#include <asm/arch/sys_proto.h>
d5b7177f FE	16	#include <asm/arch-mx7/mx7-ddr.h>
4e267b92	17	#include <asm/mach-imx/iomux-v3.h>
d5b7177f	18	#include <asm/gpio.h>
506df9dc	19	#include <asm/sections.h>
e37ac717	20	#include <fsl_esdhc_imx.h>
d5b7177f FE	21	#include <spl.h>
	22
	23	#if defined(CONFIG_SPL_BUILD)
78d30a1b FE	24
	25	#ifdef CONFIG_SPL_OS_BOOT
	26	int spl_start_uboot(void)
	27	{
b446ce29 FE	28	/* Break into full U-Boot on 'c' */
	29	if (serial_tstc() && serial_getc() == 'c')
	30	return 1;
	31
78d30a1b FE	32	return 0;
	33	}
	34	#endif
	35
d5b7177f FE	36	static struct ddrc ddrc_regs_val = {
	37	.mstr = 0x01040001,
	38	.rfshtmg = 0x00400046,
	39	.init1 = 0x00690000,
	40	.init0 = 0x00020083,
	41	.init3 = 0x09300004,
	42	.init4 = 0x04080000,
	43	.init5 = 0x00100004,
	44	.rankctl = 0x0000033F,
	45	.dramtmg0 = 0x09081109,
	46	.dramtmg1 = 0x0007020d,
	47	.dramtmg2 = 0x03040407,
	48	.dramtmg3 = 0x00002006,
	49	.dramtmg4 = 0x04020205,
	50	.dramtmg5 = 0x03030202,
	51	.dramtmg8 = 0x00000803,
	52	.zqctl0 = 0x00800020,
	53	.dfitmg0 = 0x02098204,
	54	.dfitmg1 = 0x00030303,
	55	.dfiupd0 = 0x80400003,
	56	.dfiupd1 = 0x00100020,
	57	.dfiupd2 = 0x80100004,
	58	.addrmap4 = 0x00000F0F,
	59	.odtcfg = 0x06000604,
	60	.odtmap = 0x00000001,
	61	.rfshtmg = 0x00400046,
	62	.dramtmg0 = 0x09081109,
	63	.addrmap0 = 0x0000001f,
	64	.addrmap1 = 0x00080808,
068027b1 FE	65	.addrmap2 = 0x00000000,
068027b1 FE	66	.addrmap3 = 0x00000000,
d5b7177f FE	67	.addrmap4 = 0x00000f0f,
	68	.addrmap5 = 0x07070707,
	69	.addrmap6 = 0x0f0f0707,
	70	};
	71
	72	static struct ddrc_mp ddrc_mp_val = {
	73	.pctrl_0 = 0x00000001,
	74	};
	75
	76	static struct ddr_phy ddr_phy_regs_val = {
	77	.phy_con0 = 0x17420f40,
	78	.phy_con1 = 0x10210100,
	79	.phy_con4 = 0x00060807,
	80	.mdll_con0 = 0x1010007e,
	81	.drvds_con0 = 0x00000d6e,
	82	.cmd_sdll_con0 = 0x00000010,
	83	.offset_lp_con0 = 0x0000000f,
	84	.offset_rd_con0 = 0x08080808,
	85	.offset_wr_con0 = 0x08080808,
	86	};
	87
	88	static struct mx7_calibration calib_param = {
	89	.num_val = 5,
	90	.values = {
	91	0x0E407304,
	92	0x0E447304,
	93	0x0E447306,
	94	0x0E447304,
	95	0x0E447304,
	96	},
	97	};
	98
	99	static void gpr_init(void)
	100	{
	101	struct iomuxc_gpr_base_regs *gpr_regs =
	102	(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
	103	writel(0x4F400005, &gpr_regs->gpr[1]);
	104	}
	105
068027b1 FE	106	/*
	107	* Revision Detection
	108	*
	109	* GPIO1_12 GPIO1_13
	110	* 0 0 1GB DDR3
	111	* 0 1 2GB DDR3
	112	* 1 0 512MB DDR3
	113	*/
	114
	115	static int imx7d_pico_detect_board(void)
d5b7177f FE	116	{
d5b7177f FE	117	gpio_direction_input(IMX_GPIO_NR(1, 12));
068027b1 FE	118	gpio_direction_input(IMX_GPIO_NR(1, 13));
	119
	120	return gpio_get_value(IMX_GPIO_NR(1, 12)) << 1 \|
	121	gpio_get_value(IMX_GPIO_NR(1, 13));
d5b7177f FE	122	}
	123
	124	static void ddr_init(void)
	125	{
068027b1 FE	126	switch (imx7d_pico_detect_board()) {
068027b1 FE	127	case 0:
d5b7177f	128	ddrc_regs_val.addrmap6 = 0x0f070707;
068027b1 FE	129	break;
	130	case 1:
	131	ddrc_regs_val.addrmap0 = 0x0000001f;
	132	ddrc_regs_val.addrmap1 = 0x00181818;
	133	ddrc_regs_val.addrmap4 = 0x00000f0f;
	134	ddrc_regs_val.addrmap5 = 0x04040404;
	135	ddrc_regs_val.addrmap6 = 0x04040404;
	136	break;
	137	}
d5b7177f FE	138
	139	mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
	140	&calib_param);
	141	}
	142
	143	void board_init_f(ulong dummy)
	144	{
	145	arch_cpu_init();
	146	gpr_init();
	147	board_early_init_f();
	148	timer_init();
	149	preloader_console_init();
	150	ddr_init();
	151	memset(__bss_start, 0, __bss_end - __bss_start);
	152	board_init_r(NULL, 0);
	153	}
	154
35b65dd8	155	void reset_cpu(void)
d5b7177f FE	156	{
d5b7177f FE	157	}
4e267b92 JO	158
	159	#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM \| PAD_CTL_SRE_SLOW \| \
	160	PAD_CTL_HYS \| PAD_CTL_PUE \| PAD_CTL_PUS_PU47KOHM)
	161
	162	static iomux_v3_cfg_t const usdhc3_pads[] = {
	163	MX7D_PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	164	MX7D_PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	165	MX7D_PAD_SD3_DATA0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	166	MX7D_PAD_SD3_DATA1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	167	MX7D_PAD_SD3_DATA2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	168	MX7D_PAD_SD3_DATA3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	169	MX7D_PAD_SD3_DATA4__SD3_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	170	MX7D_PAD_SD3_DATA5__SD3_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	171	MX7D_PAD_SD3_DATA6__SD3_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	172	MX7D_PAD_SD3_DATA7__SD3_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	173	MX7D_PAD_GPIO1_IO14__GPIO1_IO14 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	174	};
	175
	176	static struct fsl_esdhc_cfg usdhc_cfg[1] = {
	177	{USDHC3_BASE_ADDR},
	178	};
	179
	180	int board_mmc_getcd(struct mmc *mmc)
	181	{
	182	/* Assume uSDHC3 emmc is always present */
	183	return 1;
	184	}
	185
b75d8dc5	186	int board_mmc_init(struct bd_info *bis)
4e267b92 JO	187	{
	188	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	189	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	190	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
	191	}
d5b7177f	192	#endif