[J-u-boot.git] / board / kontron / pitx_imx8m / spl.c

// SPDX-License-Identifier: GPL-2.0+

#include <common.h>
#include <errno.h>
#include <fsl_esdhc_imx.h>
#include <hang.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/sections.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>

#include "pitx_misc.h"

extern struct dram_timing_info dram_timing_2gb;
extern struct dram_timing_info dram_timing_4gb;

DECLARE_GLOBAL_DATA_PTR;


static void spl_dram_init(void)
{
	struct dram_timing_info *dram_timing;
	int variant = 0, size;

	variant = get_pitx_board_variant();

	switch(variant) {
	case 2:
		dram_timing = &dram_timing_2gb;
		size = 2;
		break;
	case 3:
		dram_timing = &dram_timing_4gb;
		size = 4;
		break;
	default:
		printf("Unknown DDR type (%d)\n", variant);
		return;
	};

	/* ddr init */
	ddr_init(dram_timing);
}

#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
static struct i2c_pads_info i2c_pad_info1 = {
	.scl = {
		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
		.gp = IMX_GPIO_NR(5, 14),
	},
	.sda = {
		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
		.gp = IMX_GPIO_NR(5, 15),
	},
};

#if CONFIG_IS_ENABLED(MMC)
#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;

	switch (cfg->esdhc_base) {
	case USDHC1_BASE_ADDR:
		/* the eMMC does not have a CD pin */
		return 1;
	case USDHC2_BASE_ADDR:
		return !gpio_get_value(USDHC2_CD_GPIO);
	}

	return 0;
}


#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
			 PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)

static iomux_v3_cfg_t const usdhc1_pads[] = {
	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const usdhc2_pads[] = {
	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
};

static struct fsl_esdhc_cfg usdhc_cfg[2] = {
	{USDHC1_BASE_ADDR, 0, 8},
	{USDHC2_BASE_ADDR, 0, 4},
};

int board_mmc_init(struct bd_info *bis)
{
	int i, ret;
	/*
	 * According to the board_mmc_init() the following map is done:
	 * (U-Boot device node)    (Physical Port)
	 * mmc0                    USDHC1
	 * mmc1                    USDHC2
	 */
	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
		switch (i) {
		case 0:
			init_clk_usdhc(0);
			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
							 ARRAY_SIZE(usdhc1_pads));
			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
			gpio_direction_output(USDHC1_PWR_GPIO, 0);
			udelay(500);
			gpio_direction_output(USDHC1_PWR_GPIO, 1);
			break;
		case 1:
			init_clk_usdhc(1);
			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
							 ARRAY_SIZE(usdhc2_pads));
			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
			gpio_direction_output(USDHC2_PWR_GPIO, 0);
			udelay(500);
			gpio_direction_output(USDHC2_PWR_GPIO, 1);
			break;
		default:
			printf("Warning: you configured more USDHC controllers "
				"(%d) than supported by the board\n", i + 1);
			return -EINVAL;
		}

		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		if (ret)
			return ret;
	}

	return 0;
}

const char *spl_board_loader_name(u32 boot_device)
{
	switch (boot_device) {
	case BOOT_DEVICE_MMC1:
		return "eMMC";
	case BOOT_DEVICE_MMC2:
		return "SD card";
	default:
		return NULL;
	}
}
#endif

#if CONFIG_IS_ENABLED(POWER_LEGACY)
#define I2C_PMIC	0

static int pfuze_mode_init(struct pmic *p, u32 mode)
{
	unsigned char offset, i, switch_num;
	u32 id;
	int ret;

	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
	id = id & 0xf;

	if (id == 0) {
		switch_num = 6;
		offset = PFUZE100_SW1CMODE;
	} else if (id == 1) {
		switch_num = 4;
		offset = PFUZE100_SW2MODE;
	} else {
		printf("Not supported, id=%d\n", id);
		return -EINVAL;
	}

	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
	if (ret < 0) {
		printf("Set SW1AB mode error!\n");
		return ret;
	}

	for (i = 0; i < switch_num - 1; i++) {
		ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
		if (ret < 0) {
			printf("Set switch 0x%x mode error!\n",
			       offset + i * SWITCH_SIZE);
			return ret;
		}
	}

	return ret;
}

int power_init_board(void)
{
	struct pmic *p;
	int ret;
	unsigned int reg;

	ret = power_pfuze100_init(I2C_PMIC);
	if (ret)
		return -ENODEV;

	p = pmic_get("PFUZE100");
	ret = pmic_probe(p);
	if (ret)
		return -ENODEV;

	pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
	if ((reg & 0x3f) != 0x18) {
		reg &= ~0x3f;
		reg |= 0x18;
		pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
	}

	ret = pfuze_mode_init(p, APS_PFM);
	if (ret < 0)
		return ret;

	/* set SW3A standby mode to off */
	pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
	reg &= ~0xf;
	reg |= APS_OFF;
	pmic_reg_write(p, PFUZE100_SW3AMODE, reg);

	return 0;
}
#endif

void board_init_f(ulong dummy)
{
	int ret;

	/* Clear global data */
	memset((void *)gd, 0, sizeof(gd_t));

	arch_cpu_init();

	init_uart_clk(2);

	board_early_init_f();

	timer_init();

	preloader_console_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	ret = spl_init();
	if (ret) {
		debug("spl_init() failed: %d\n", ret);
		hang();
	}

	enable_tzc380();

	setup_i2c(0, 100000, 0x7f, &i2c_pad_info1);

#if CONFIG_IS_ENABLED(POWER_LEGACY)
	power_init_board();
#endif

	spl_dram_init();

	board_init_r(NULL, 0);
}
Commit	Line	Data
16c7369e HT	1	// SPDX-License-Identifier: GPL-2.0+
	2
	3	#include <common.h>
	4	#include <errno.h>
	5	#include <fsl_esdhc_imx.h>
	6	#include <hang.h>
	7	#include <init.h>
	8	#include <log.h>
	9	#include <spl.h>
	10	#include <asm/arch/ddr.h>
	11	#include <asm/arch/imx8mq_pins.h>
	12	#include <asm/arch/sys_proto.h>
	13	#include <asm/arch/clock.h>
	14	#include <asm/global_data.h>
	15	#include <asm/io.h>
	16	#include <asm/mach-imx/iomux-v3.h>
	17	#include <asm/mach-imx/gpio.h>
	18	#include <asm/mach-imx/mxc_i2c.h>
506df9dc	19	#include <asm/sections.h>
16c7369e HT	20	#include <linux/delay.h>
	21	#include <power/pmic.h>
	22	#include <power/pfuze100_pmic.h>
	23
	24	#include "pitx_misc.h"
	25
	26	extern struct dram_timing_info dram_timing_2gb;
	27	extern struct dram_timing_info dram_timing_4gb;
	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31
	32	static void spl_dram_init(void)
	33	{
	34	struct dram_timing_info *dram_timing;
	35	int variant = 0, size;
	36
	37	variant = get_pitx_board_variant();
	38
	39	switch(variant) {
	40	case 2:
	41	dram_timing = &dram_timing_2gb;
	42	size = 2;
	43	break;
	44	case 3:
	45	dram_timing = &dram_timing_4gb;
	46	size = 4;
	47	break;
	48	default:
	49	printf("Unknown DDR type (%d)\n", variant);
	50	return;
	51	};
	52
	53	/* ddr init */
	54	ddr_init(dram_timing);
	55	}
	56
	57	#define I2C_PAD_CTRL (PAD_CTL_DSE6 \| PAD_CTL_HYS \| PAD_CTL_PUE)
	58	#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
	59	static struct i2c_pads_info i2c_pad_info1 = {
	60	.scl = {
	61	.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL \| PC,
	62	.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 \| PC,
	63	.gp = IMX_GPIO_NR(5, 14),
	64	},
	65	.sda = {
	66	.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA \| PC,
	67	.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 \| PC,
	68	.gp = IMX_GPIO_NR(5, 15),
	69	},
	70	};
	71
	72	#if CONFIG_IS_ENABLED(MMC)
	73	#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
	74	#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
	75	#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
	76
	77	int board_mmc_getcd(struct mmc *mmc)
	78	{
	79	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
16c7369e HT	80
	81	switch (cfg->esdhc_base) {
	82	case USDHC1_BASE_ADDR:
	83	/* the eMMC does not have a CD pin */
3240d011	84	return 1;
16c7369e	85	case USDHC2_BASE_ADDR:
3240d011	86	return !gpio_get_value(USDHC2_CD_GPIO);
16c7369e HT	87	}
16c7369e HT	88
3240d011	89	return 0;
16c7369e HT	90	}
	91
	92
	93	#define USDHC_PAD_CTRL (PAD_CTL_DSE6 \| PAD_CTL_HYS \| PAD_CTL_PUE \| \
	94	PAD_CTL_FSEL2)
	95	#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE \| PAD_CTL_DSE1)
	96
	97	static iomux_v3_cfg_t const usdhc1_pads[] = {
	98	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	99	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	100	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	101	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	102	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	103	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	104	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	105	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	106	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	107	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	108	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	109	};
	110
	111	static iomux_v3_cfg_t const usdhc2_pads[] = {
	112	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	113	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	114	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	115	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	116	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
	117	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	118	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 \| MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
	119	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 \| MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
	120	};
	121
	122	static struct fsl_esdhc_cfg usdhc_cfg[2] = {
	123	{USDHC1_BASE_ADDR, 0, 8},
	124	{USDHC2_BASE_ADDR, 0, 4},
	125	};
	126
	127	int board_mmc_init(struct bd_info *bis)
	128	{
	129	int i, ret;
	130	/*
	131	* According to the board_mmc_init() the following map is done:
	132	* (U-Boot device node) (Physical Port)
	133	* mmc0 USDHC1
	134	* mmc1 USDHC2
	135	*/
6cc04547	136	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
16c7369e HT	137	switch (i) {
	138	case 0:
	139	init_clk_usdhc(0);
	140	usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
	141	imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
	142	ARRAY_SIZE(usdhc1_pads));
	143	gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
	144	gpio_direction_output(USDHC1_PWR_GPIO, 0);
	145	udelay(500);
	146	gpio_direction_output(USDHC1_PWR_GPIO, 1);
	147	break;
	148	case 1:
	149	init_clk_usdhc(1);
	150	usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
	151	imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
	152	ARRAY_SIZE(usdhc2_pads));
	153	gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
	154	gpio_direction_output(USDHC2_PWR_GPIO, 0);
	155	udelay(500);
	156	gpio_direction_output(USDHC2_PWR_GPIO, 1);
	157	break;
	158	default:
	159	printf("Warning: you configured more USDHC controllers "
	160	"(%d) than supported by the board\n", i + 1);
	161	return -EINVAL;
	162	}
	163
	164	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
	165	if (ret)
	166	return ret;
	167	}
	168
	169	return 0;
	170	}
	171
	172	const char *spl_board_loader_name(u32 boot_device)
	173	{
	174	switch (boot_device) {
	175	case BOOT_DEVICE_MMC1:
	176	return "eMMC";
	177	case BOOT_DEVICE_MMC2:
	178	return "SD card";
	179	default:
	180	return NULL;
	181	}
	182	}
	183	#endif
	184
	185	#if CONFIG_IS_ENABLED(POWER_LEGACY)
	186	#define I2C_PMIC 0
	187
	188	static int pfuze_mode_init(struct pmic *p, u32 mode)
	189	{
	190	unsigned char offset, i, switch_num;
	191	u32 id;
	192	int ret;
	193
	194	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
	195	id = id & 0xf;
	196
	197	if (id == 0) {
	198	switch_num = 6;
	199	offset = PFUZE100_SW1CMODE;
	200	} else if (id == 1) {
201	switch_num = 4;
202	offset = PFUZE100_SW2MODE;
203	} else {
204	printf("Not supported, id=%d\n", id);
205	return -EINVAL;
206	}
207
208	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
209	if (ret < 0) {
210	printf("Set SW1AB mode error!\n");
211	return ret;
212	}
213
214	for (i = 0; i < switch_num - 1; i++) {
215	ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
216	if (ret < 0) {
217	printf("Set switch 0x%x mode error!\n",
218	offset + i * SWITCH_SIZE);
219	return ret;
220	}
221	}
222
223	return ret;
224	}
225
226	int power_init_board(void)
227	{
228	struct pmic *p;
229	int ret;
230	unsigned int reg;
231
232	ret = power_pfuze100_init(I2C_PMIC);
233	if (ret)
234	return -ENODEV;
235
236	p = pmic_get("PFUZE100");
237	ret = pmic_probe(p);
238	if (ret)
239	return -ENODEV;
240
241	pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
242	if ((reg & 0x3f) != 0x18) {
243	reg &= ~0x3f;
244	reg \|= 0x18;
245	pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
246	}
247
248	ret = pfuze_mode_init(p, APS_PFM);
249	if (ret < 0)
250	return ret;
251
252	/* set SW3A standby mode to off */
253	pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
254	reg &= ~0xf;
255	reg \|= APS_OFF;
256	pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
257
258	return 0;
259	}
260	#endif
261
262	void board_init_f(ulong dummy)
263	{
264	int ret;
265
266	/* Clear global data */
267	memset((void *)gd, 0, sizeof(gd_t));
268
269	arch_cpu_init();
270
271	init_uart_clk(2);
272
273	board_early_init_f();
274
275	timer_init();
276
277	preloader_console_init();
278
279	/* Clear the BSS. */
280	memset(__bss_start, 0, __bss_end - __bss_start);
281
282	ret = spl_init();
283	if (ret) {
284	debug("spl_init() failed: %d\n", ret);
285	hang();
286	}
287
288	enable_tzc380();
289
290	setup_i2c(0, 100000, 0x7f, &i2c_pad_info1);
291
292	#if CONFIG_IS_ENABLED(POWER_LEGACY)
293	power_init_board();
294	#endif
295
296	spl_dram_init();
297
298	board_init_r(NULL, 0);
299	}