[J-u-boot.git] / board / freescale / imx93_evk / spl.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2022 NXP
 */

#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <hang.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx93_pins.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch-mx7ulp/gpio.h>
#include <asm/mach-imx/syscounter.h>
#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <linux/delay.h>
#include <asm/arch/clock.h>
#include <asm/arch/ccm_regs.h>
#include <asm/arch/ddr.h>
#include <power/pmic.h>
#include <power/pca9450.h>
#include <asm/arch/trdc.h>

DECLARE_GLOBAL_DATA_PTR;

int spl_board_boot_device(enum boot_device boot_dev_spl)
{
	return BOOT_DEVICE_BOOTROM;
}

void spl_board_init(void)
{
	puts("Normal Boot\n");
}

void spl_dram_init(void)
{
	ddr_init(&dram_timing);
}

#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
int power_init_board(void)
{
	struct udevice *dev;
	int ret;

	ret = pmic_get("pmic@25", &dev);
	if (ret == -ENODEV) {
		puts("No pca9450@25\n");
		return 0;
	}
	if (ret != 0)
		return ret;

	/* BUCKxOUT_DVS0/1 control BUCK123 output */
	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);

	/* enable DVS control through PMIC_STBY_REQ */
	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);

	if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) {
		/* 0.75v for Low drive mode
		 */
		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c);
		pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c);
	} else {
		/* 0.9v for Over drive mode
		 */
		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
		pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
	}

	/* set standby voltage to 0.65v */
	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);

	/* I2C_LT_EN*/
	pmic_reg_write(dev, 0xa, 0x3);
	return 0;
}
#endif

extern int imx9_probe_mu(void *ctx, struct event *event);
void board_init_f(ulong dummy)
{
	int ret;

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	timer_init();

	arch_cpu_init();

	board_early_init_f();

	spl_early_init();

	preloader_console_init();

	ret = imx9_probe_mu(NULL, NULL);
	if (ret) {
		printf("Fail to init Sentinel API\n");
	} else {
		printf("SOC: 0x%x\n", gd->arch.soc_rev);
		printf("LC: 0x%x\n", gd->arch.lifecycle);
	}

	power_init_board();

	if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
		set_arm_clk(get_cpu_speed_grade_hz());

	/* Init power of mix */
	soc_power_init();

	/* Setup TRDC for DDR access */
	trdc_init();

	/* DDR initialization */
	spl_dram_init();

	/* Put M33 into CPUWAIT for following kick */
	ret = m33_prepare();
	if (!ret)
		printf("M33 prepare ok\n");

	board_init_r(NULL, 0);
}
Commit	Line	Data
86a17970 PF	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright 2022 NXP
	4	*/
	5
	6	#include <common.h>
	7	#include <command.h>
	8	#include <cpu_func.h>
	9	#include <hang.h>
	10	#include <image.h>
	11	#include <init.h>
	12	#include <log.h>
	13	#include <spl.h>
	14	#include <asm/global_data.h>
	15	#include <asm/io.h>
	16	#include <asm/arch/imx93_pins.h>
	17	#include <asm/arch/clock.h>
	18	#include <asm/arch/sys_proto.h>
	19	#include <asm/mach-imx/boot_mode.h>
	20	#include <asm/mach-imx/mxc_i2c.h>
	21	#include <asm/arch-mx7ulp/gpio.h>
	22	#include <asm/mach-imx/syscounter.h>
506df9dc	23	#include <asm/sections.h>
86a17970 PF	24	#include <dm/uclass.h>
	25	#include <dm/device.h>
	26	#include <dm/uclass-internal.h>
	27	#include <dm/device-internal.h>
	28	#include <linux/delay.h>
	29	#include <asm/arch/clock.h>
	30	#include <asm/arch/ccm_regs.h>
	31	#include <asm/arch/ddr.h>
	32	#include <power/pmic.h>
	33	#include <power/pca9450.h>
	34	#include <asm/arch/trdc.h>
	35
	36	DECLARE_GLOBAL_DATA_PTR;
	37
	38	int spl_board_boot_device(enum boot_device boot_dev_spl)
	39	{
	40	return BOOT_DEVICE_BOOTROM;
	41	}
	42
	43	void spl_board_init(void)
	44	{
	45	puts("Normal Boot\n");
	46	}
	47
	48	void spl_dram_init(void)
	49	{
	50	ddr_init(&dram_timing);
	51	}
	52
	53	#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
	54	int power_init_board(void)
	55	{
	56	struct udevice *dev;
	57	int ret;
	58
	59	ret = pmic_get("pmic@25", &dev);
	60	if (ret == -ENODEV) {
	61	puts("No pca9450@25\n");
	62	return 0;
	63	}
	64	if (ret != 0)
	65	return ret;
	66
	67	/* BUCKxOUT_DVS0/1 control BUCK123 output */
	68	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
	69
d59b9c38 PF	70	/* enable DVS control through PMIC_STBY_REQ */
	71	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
	72
	73	if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) {
	74	/* 0.75v for Low drive mode
	75	*/
	76	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c);
	77	pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c);
	78	} else {
	79	/* 0.9v for Over drive mode
	80	*/
	81	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
	82	pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
	83	}
	84
	85	/* set standby voltage to 0.65v */
	86	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
86a17970 PF	87
	88	/* I2C_LT_EN*/
	89	pmic_reg_write(dev, 0xa, 0x3);
86a17970 PF	90	return 0;
	91	}
	92	#endif
	93
	94	extern int imx9_probe_mu(void ctx, struct event event);
	95	void board_init_f(ulong dummy)
	96	{
	97	int ret;
	98
	99	/* Clear the BSS. */
	100	memset(__bss_start, 0, __bss_end - __bss_start);
	101
	102	timer_init();
	103
	104	arch_cpu_init();
	105
	106	board_early_init_f();
	107
	108	spl_early_init();
	109
	110	preloader_console_init();
	111
	112	ret = imx9_probe_mu(NULL, NULL);
	113	if (ret) {
	114	printf("Fail to init Sentinel API\n");
	115	} else {
	116	printf("SOC: 0x%x\n", gd->arch.soc_rev);
	117	printf("LC: 0x%x\n", gd->arch.lifecycle);
	118	}
d59b9c38	119
86a17970 PF	120	power_init_board();
86a17970 PF	121
d59b9c38 PF	122	if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
d59b9c38 PF	123	set_arm_clk(get_cpu_speed_grade_hz());
feaf8e0c	124
86a17970 PF	125	/* Init power of mix */
	126	soc_power_init();
	127
	128	/* Setup TRDC for DDR access */
	129	trdc_init();
	130
	131	/* DDR initialization */
	132	spl_dram_init();
	133
	134	/* Put M33 into CPUWAIT for following kick */
	135	ret = m33_prepare();
	136	if (!ret)
	137	printf("M33 prepare ok\n");
	138
	139	board_init_r(NULL, 0);
	140	}