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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
5c952cf0 WD |
2 | /* |
3 | * (C) Copyright 2004, Psyent Corporation <www.psyent.com> | |
4 | * Scott McNutt <[email protected]> | |
5c952cf0 WD |
5 | */ |
6 | ||
7 | #include <common.h> | |
09140113 | 8 | #include <command.h> |
bcae80e9 | 9 | #include <cpu.h> |
1eb69ae4 | 10 | #include <cpu_func.h> |
bcae80e9 TC |
11 | #include <dm.h> |
12 | #include <errno.h> | |
7fe32b34 | 13 | #include <event.h> |
691d719d | 14 | #include <init.h> |
36bf446b | 15 | #include <irq_func.h> |
f956ad98 | 16 | #include <asm/cache.h> |
401d1c4f | 17 | #include <asm/global_data.h> |
cd93d625 | 18 | #include <asm/system.h> |
5c952cf0 | 19 | |
5ff10aa7 TC |
20 | DECLARE_GLOBAL_DATA_PTR; |
21 | ||
5ff10aa7 TC |
22 | #ifdef CONFIG_DISPLAY_CPUINFO |
23 | int print_cpuinfo(void) | |
5c952cf0 | 24 | { |
ca844dd8 TC |
25 | printf("CPU: Nios-II\n"); |
26 | return 0; | |
5c952cf0 | 27 | } |
5ff10aa7 | 28 | #endif /* CONFIG_DISPLAY_CPUINFO */ |
5c952cf0 | 29 | |
4909f0e1 TC |
30 | #ifdef CONFIG_ALTERA_SYSID |
31 | int checkboard(void) | |
32 | { | |
33 | display_sysid(); | |
34 | return 0; | |
35 | } | |
36 | #endif | |
37 | ||
09140113 | 38 | int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) |
5c952cf0 | 39 | { |
7a6a7d10 TC |
40 | disable_interrupts(); |
41 | /* indirect call to go beyond 256MB limitation of toolchain */ | |
121e36da | 42 | nios2_callr(gd->arch.reset_addr); |
7a6a7d10 | 43 | return 0; |
5c952cf0 | 44 | } |
f956ad98 | 45 | |
b8112091 TC |
46 | /* |
47 | * COPY EXCEPTION TRAMPOLINE -- copy the tramp to the | |
48 | * exception address. Define CONFIG_ROM_STUBS to prevent | |
49 | * the copy (e.g. exception in flash or in other | |
50 | * softare/firmware component). | |
51 | */ | |
52 | #ifndef CONFIG_ROM_STUBS | |
53 | static void copy_exception_trampoline(void) | |
54 | { | |
55 | extern int _except_start, _except_end; | |
56 | void *except_target = (void *)gd->arch.exception_addr; | |
57 | ||
58 | if (&_except_start != except_target) { | |
59 | memcpy(except_target, &_except_start, | |
60 | &_except_end - &_except_start); | |
61 | flush_cache(gd->arch.exception_addr, | |
62 | &_except_end - &_except_start); | |
63 | } | |
64 | } | |
65 | #endif | |
66 | ||
f72d0d4a | 67 | static int nios_cpu_setup(void) |
5ff10aa7 | 68 | { |
bcae80e9 TC |
69 | struct udevice *dev; |
70 | int ret; | |
71 | ||
3f603cbb | 72 | ret = uclass_first_device_err(UCLASS_CPU, &dev); |
bcae80e9 TC |
73 | if (ret) |
74 | return ret; | |
bcae80e9 | 75 | |
aa6e94de | 76 | gd->ram_size = CFG_SYS_SDRAM_SIZE; |
b8112091 TC |
77 | #ifndef CONFIG_ROM_STUBS |
78 | copy_exception_trampoline(); | |
79 | #endif | |
5ff10aa7 TC |
80 | |
81 | return 0; | |
82 | } | |
f72d0d4a | 83 | EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, nios_cpu_setup); |
bcae80e9 | 84 | |
961420fa SG |
85 | static int altera_nios2_get_desc(const struct udevice *dev, char *buf, |
86 | int size) | |
bcae80e9 TC |
87 | { |
88 | const char *cpu_name = "Nios-II"; | |
89 | ||
90 | if (size < strlen(cpu_name)) | |
91 | return -ENOSPC; | |
92 | strcpy(buf, cpu_name); | |
93 | ||
94 | return 0; | |
95 | } | |
96 | ||
961420fa SG |
97 | static int altera_nios2_get_info(const struct udevice *dev, |
98 | struct cpu_info *info) | |
bcae80e9 TC |
99 | { |
100 | info->cpu_freq = gd->cpu_clk; | |
101 | info->features = (1 << CPU_FEAT_L1_CACHE) | | |
102 | (gd->arch.has_mmu ? (1 << CPU_FEAT_MMU) : 0); | |
103 | ||
104 | return 0; | |
105 | } | |
106 | ||
961420fa | 107 | static int altera_nios2_get_count(const struct udevice *dev) |
bcae80e9 TC |
108 | { |
109 | return 1; | |
110 | } | |
111 | ||
112 | static int altera_nios2_probe(struct udevice *dev) | |
113 | { | |
114 | const void *blob = gd->fdt_blob; | |
e160f7d4 | 115 | int node = dev_of_offset(dev); |
bcae80e9 TC |
116 | |
117 | gd->cpu_clk = fdtdec_get_int(blob, node, | |
118 | "clock-frequency", 0); | |
119 | gd->arch.dcache_line_size = fdtdec_get_int(blob, node, | |
120 | "dcache-line-size", 0); | |
121 | gd->arch.icache_line_size = fdtdec_get_int(blob, node, | |
122 | "icache-line-size", 0); | |
123 | gd->arch.dcache_size = fdtdec_get_int(blob, node, | |
124 | "dcache-size", 0); | |
125 | gd->arch.icache_size = fdtdec_get_int(blob, node, | |
126 | "icache-size", 0); | |
127 | gd->arch.reset_addr = fdtdec_get_int(blob, node, | |
128 | "altr,reset-addr", 0); | |
129 | gd->arch.exception_addr = fdtdec_get_int(blob, node, | |
130 | "altr,exception-addr", 0); | |
131 | gd->arch.has_initda = fdtdec_get_int(blob, node, | |
132 | "altr,has-initda", 0); | |
133 | gd->arch.has_mmu = fdtdec_get_int(blob, node, | |
134 | "altr,has-mmu", 0); | |
1ce61cbb TC |
135 | gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x80000000; |
136 | gd->arch.mem_region_base = gd->arch.has_mmu ? 0xc0000000 : 0x00000000; | |
2de4823d | 137 | gd->arch.physaddr_mask = gd->arch.has_mmu ? 0x1fffffff : 0x7fffffff; |
bcae80e9 TC |
138 | |
139 | return 0; | |
140 | } | |
141 | ||
142 | static const struct cpu_ops altera_nios2_ops = { | |
143 | .get_desc = altera_nios2_get_desc, | |
144 | .get_info = altera_nios2_get_info, | |
145 | .get_count = altera_nios2_get_count, | |
146 | }; | |
147 | ||
148 | static const struct udevice_id altera_nios2_ids[] = { | |
149 | { .compatible = "altr,nios2-1.0" }, | |
150 | { .compatible = "altr,nios2-1.1" }, | |
151 | { } | |
152 | }; | |
153 | ||
154 | U_BOOT_DRIVER(altera_nios2) = { | |
155 | .name = "altera_nios2", | |
156 | .id = UCLASS_CPU, | |
157 | .of_match = altera_nios2_ids, | |
158 | .probe = altera_nios2_probe, | |
159 | .ops = &altera_nios2_ops, | |
160 | .flags = DM_FLAG_PRE_RELOC, | |
161 | }; | |
f1683aa7 SG |
162 | |
163 | /* This is a dummy function on nios2 */ | |
164 | int dram_init(void) | |
165 | { | |
166 | return 0; | |
167 | } |