[J-u-boot.git] / arch / arm / dts / versal-net-mini-qspi.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Xilinx Versal NET Mini QSPI Configuration
 *
 * (C) Copyright 2023, Advanced Micro Devices, Inc.
 *
 * Michal Simek <[email protected]>
 * Ashok Reddy Soma <[email protected]>
 */

/dts-v1/;

/ {
	compatible = "xlnx,versal-net-mini";
	#address-cells = <2>;
	#size-cells = <2>;
	model = "Xilinx Versal NET MINI QSPI";

	aliases {
		serial0 = &dcc;
		spi0 = &qspi;
	};

	chosen {
		stdout-path = "serial0:115200";
	};

	memory@bbf00000 {
		device_type = "memory";
		reg = <0 0xbbf00000 0 0x100000>;
	};

	clk150: clk150 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <150000000>;
	};

	dcc: dcc {
		compatible = "arm,dcc";
		status = "okay";
		bootph-all;
	};

	amba: axi {
		bootph-all;
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		qspi: spi@f1030000 {
			compatible = "xlnx,versal-qspi-1.0";
			status = "okay";
			clock-names = "ref_clk", "pclk";
			num-cs = <1>;
			reg = <0 0xf1030000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clk150>, <&clk150>;

			flash0: flash@0 {
				compatible = "n25q512a", "micron,m25p80",
					     "jedec,spi-nor";
				reg = <0>;
				spi-tx-bus-width = <4>;
				spi-rx-bus-width = <4>;
				spi-max-frequency = <20000000>;
			};
		};
	};
};
Commit	Line	Data
96683d34 ARS	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* dts file for Xilinx Versal NET Mini QSPI Configuration
	4	*
	5	* (C) Copyright 2023, Advanced Micro Devices, Inc.
	6	*
	7	* Michal Simek <[email protected]>
	8	* Ashok Reddy Soma <[email protected]>
	9	*/
	10
	11	/dts-v1/;
	12
	13	/ {
	14	compatible = "xlnx,versal-net-mini";
	15	#address-cells = <2>;
	16	#size-cells = <2>;
	17	model = "Xilinx Versal NET MINI QSPI";
	18
	19	aliases {
	20	serial0 = &dcc;
	21	spi0 = &qspi;
	22	};
	23
	24	chosen {
	25	stdout-path = "serial0:115200";
	26	};
	27
	28	memory@bbf00000 {
	29	device_type = "memory";
	30	reg = <0 0xbbf00000 0 0x100000>;
	31	};
	32
	33	clk150: clk150 {
	34	compatible = "fixed-clock";
	35	#clock-cells = <0>;
	36	clock-frequency = <150000000>;
	37	};
	38
	39	dcc: dcc {
	40	compatible = "arm,dcc";
	41	status = "okay";
	42	bootph-all;
	43	};
	44
2b82768d	45	amba: axi {
96683d34 ARS	46	bootph-all;
	47	compatible = "simple-bus";
	48	#address-cells = <2>;
	49	#size-cells = <2>;
	50	ranges;
	51
	52	qspi: spi@f1030000 {
	53	compatible = "xlnx,versal-qspi-1.0";
	54	status = "okay";
	55	clock-names = "ref_clk", "pclk";
	56	num-cs = <1>;
	57	reg = <0 0xf1030000 0 0x1000>;
	58	#address-cells = <1>;
	59	#size-cells = <0>;
	60	clocks = <&clk150>, <&clk150>;
	61
	62	flash0: flash@0 {
	63	compatible = "n25q512a", "micron,m25p80",
	64	"jedec,spi-nor";
	65	reg = <0>;
	66	spi-tx-bus-width = <4>;
	67	spi-rx-bus-width = <4>;
	68	spi-max-frequency = <20000000>;
	69	};
	70	};
	71	};
	72	};