[J-u-boot.git] / arch / arm / dts / fsl-imx8dx.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018, 2021 NXP
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "fsl-imx8-ca35.dtsi"
#include <dt-bindings/soc/imx_rsrc.h>
#include <dt-bindings/soc/imx8_pd.h>
#include <dt-bindings/clock/imx8qxp-clock.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	model = "Freescale i.MX8DX";
	compatible = "fsl,imx8dx", "fsl,imx8qxp";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec1;
		ethernet1 = &fec2;
		serial0 = &lpuart0;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		gpio4 = &gpio4;
		gpio5 = &gpio5;
		gpio6 = &gpio6;
		gpio7 = &gpio7;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
		      /* DRAM space - 1, size : 1 GB DRAM */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/*
		 * reserved-memory layout
		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
		 * Shouldn't be used at A core and Linux side.
		 *
		 */
		decoder_boot: decoder_boot@0x84000000 {
			no-map;
			reg = <0 0x84000000 0 0x2000000>;
		};
		encoder_boot: encoder_boot@0x86000000 {
			no-map;
			reg = <0 0x86000000 0 0x2000000>;
		};
		rpmsg_reserved: rpmsg@0x90000000 {
			no-map;
			reg = <0 0x90000000 0 0x400000>;
		};
		decoder_rpc: decoder_rpc@0x90400000 {
			no-map;
			reg = <0 0x90400000 0 0x1000000>;
		};
		encoder_rpc: encoder_rpc@0x91400000 {
			no-map;
			reg = <0 0x91400000 0 0x1000000>;
		};
		dsp_reserved: dsp@0x92400000 {
			no-map;
			reg = <0 0x92400000 0 0x2000000>;
		};
		decoder_str: str@0x94400000 {
			no-map;
			reg = <0 0x94400000 0 0x1800000>;
		};
		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0 0x28000000>;
			alloc-ranges = <0 0x96000000 0 0x28000000>;
			linux,cma-default;
		};
	};

	gic: interrupt-controller@51a00000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
		      <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9
			(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
		interrupt-parent = <&gic>;
	};

	mu: mu@5d1c0000 {
		compatible = "fsl,imx8-mu";
		reg = <0x0 0x5d1c0000 0x0 0x10000>;
		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		status = "okay";

		clk: clk {
			compatible = "fsl,imx8qxp-clk";
			#clock-cells = <1>;
		};

		iomuxc: iomuxc {
			compatible = "fsl,imx8qxp-iomuxc";
		};
	};

	imx8qx-pm {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		pd_lsio: PD_LSIO {
			compatible = "nxp,imx8-pd";
			reg = <SC_R_NONE>;
			#power-domain-cells = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			pd_lsio_gpio0: PD_LSIO_GPIO_0 {
				reg = <SC_R_GPIO_0>;
				#power-domain-cells = <0>;
				power-domains = <&pd_lsio>;
			};
			pd_lsio_gpio1: PD_LSIO_GPIO_1 {
				reg = <SC_R_GPIO_1>;
				#power-domain-cells = <0>;
				power-domains = <&pd_lsio>;
			};
			pd_lsio_gpio2: PD_LSIO_GPIO_2 {
				reg = <SC_R_GPIO_2>;
				#power-domain-cells = <0>;
				power-domains = <&pd_lsio>;
			};
			pd_lsio_gpio3: PD_LSIO_GPIO_3 {
				reg = <SC_R_GPIO_3>;
				#power-domain-cells = <0>;
				power-domains = <&pd_lsio>;
			};
			pd_lsio_gpio4: PD_LSIO_GPIO_4 {
				reg = <SC_R_GPIO_4>;
				#power-domain-cells = <0>;
				power-domains = <&pd_lsio>;
			};
			pd_lsio_gpio5: PD_LSIO_GPIO_5{
				reg = <SC_R_GPIO_5>;
				#power-domain-cells = <0>;
				power-domains = <&pd_lsio>;
			};
			pd_lsio_gpio6: PD_LSIO_GPIO_6 {
				reg = <SC_R_GPIO_6>;
				#power-domain-cells = <0>;
				power-domains = <&pd_lsio>;
			};
			pd_lsio_gpio7: PD_LSIO_GPIO_7 {
				reg = <SC_R_GPIO_7>;
				#power-domain-cells = <0>;
				power-domains = <&pd_lsio>;
			};
		};

		pd_conn: PD_CONN {
			compatible = "nxp,imx8-pd";
			reg = <SC_R_NONE>;
			#power-domain-cells = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			pd_conn_sdch0: PD_CONN_SDHC_0 {
				reg = <SC_R_SDHC_0>;
				#power-domain-cells = <0>;
				power-domains = <&pd_conn>;
			};
			pd_conn_sdch1: PD_CONN_SDHC_1 {
				reg = <SC_R_SDHC_1>;
				#power-domain-cells = <0>;
				power-domains = <&pd_conn>;
			};
			pd_conn_sdch2: PD_CONN_SDHC_2 {
				reg = <SC_R_SDHC_2>;
				#power-domain-cells = <0>;
				power-domains = <&pd_conn>;
			};
			pd_conn_enet0: PD_CONN_ENET_0 {
				reg = <SC_R_ENET_0>;
				#power-domain-cells = <0>;
				power-domains = <&pd_conn>;
			};
			pd_conn_enet1: PD_CONN_ENET_1 {
				reg = <SC_R_ENET_1>;
				#power-domain-cells = <0>;
				power-domains = <&pd_conn>;
			};
		};

		pd_dma: PD_DMA {
			compatible = "nxp,imx8-pd";
			reg = <SC_R_NONE>;
			#power-domain-cells = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			pd_dma_lpi2c0: PD_DMA_I2C_0 {
				reg = <SC_R_I2C_0>;
				#power-domain-cells = <0>;
				power-domains = <&pd_dma>;
			};
			pd_dma_lpi2c1: PD_DMA_I2C_1 {
				reg = <SC_R_I2C_1>;
				#power-domain-cells = <0>;
				power-domains = <&pd_dma>;
			};
			pd_dma_lpi2c2:PD_DMA_I2C_2 {
				reg = <SC_R_I2C_2>;
				#power-domain-cells = <0>;
				power-domains = <&pd_dma>;
			};
			pd_dma_lpi2c3: PD_DMA_I2C_3 {
				reg = <SC_R_I2C_3>;
				#power-domain-cells = <0>;
				power-domains = <&pd_dma>;
			};
			pd_dma_lpuart0: PD_DMA_UART0 {
				reg = <SC_R_UART_0>;
				#power-domain-cells = <0>;
				power-domains = <&pd_dma>;
				wakeup-irq = <225>;
			};
			pd_dma_lpuart1: PD_DMA_UART1 {
				reg = <SC_R_UART_1>;
				#power-domain-cells = <0>;
				power-domains = <&pd_dma>;
			};
			pd_dma_lpuart2: PD_DMA_UART2 {
				reg = <SC_R_UART_2>;
				#power-domain-cells = <0>;
				power-domains = <&pd_dma>;
			};
			pd_dma_lpuart3: PD_DMA_UART3 {
				reg = <SC_R_UART_3>;
				#power-domain-cells = <0>;
				power-domains = <&pd_dma>;
			};
		};

		pd_caam: PD_CAAM {
			compatible = "nxp,imx8-pd";
			reg = <SC_R_NONE>;
			#power-domain-cells = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			pd_caam_jr1: PD_CAAM_JR1 {
				reg = <SC_R_CAAM_JR1>;
				#power-domain-cells = <0>;
				power-domains = <&pd_caam>;
			};
			pd_caam_jr2: PD_CAAM_JR2 {
				reg = <SC_R_CAAM_JR2>;
				#power-domain-cells = <0>;
				power-domains = <&pd_caam>;
			};
			pd_caam_jr3: PD_CAAM_JR3 {
				reg = <SC_R_CAAM_JR3>;
				#power-domain-cells = <0>;
				power-domains = <&pd_caam>;
			};
		};
	};

	i2c0: i2c@5a800000 {
		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
		reg = <0x0 0x5a800000 0x0 0x4000>;
		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&clk IMX8QXP_I2C0_CLK>,
			<&clk IMX8QXP_I2C0_IPG_CLK>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd_dma_lpi2c0>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c1: i2c@5a810000 {
		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
		reg = <0x0 0x5a810000 0x0 0x4000>;
		interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&clk IMX8QXP_I2C1_CLK>,
			<&clk IMX8QXP_I2C1_IPG_CLK>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd_dma_lpi2c1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c2: i2c@5a820000 {
		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
		reg = <0x0 0x5a820000 0x0 0x4000>;
		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&clk IMX8QXP_I2C2_CLK>,
			<&clk IMX8QXP_I2C2_IPG_CLK>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd_dma_lpi2c2>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c3: i2c@5a830000 {
		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
		reg = <0x0 0x5a830000 0x0 0x4000>;
		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&clk IMX8QXP_I2C3_CLK>,
			<&clk IMX8QXP_I2C3_IPG_CLK>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd_dma_lpi2c3>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	gpio0: gpio@5d080000 {
		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x5d080000 0x0 0x10000>;
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		power-domains = <&pd_lsio_gpio0>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio1: gpio@5d090000 {
		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x5d090000 0x0 0x10000>;
		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		power-domains = <&pd_lsio_gpio1>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio2: gpio@5d0a0000 {
		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x5d0a0000 0x0 0x10000>;
		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		power-domains = <&pd_lsio_gpio2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio3: gpio@5d0b0000 {
		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x5d0b0000 0x0 0x10000>;
		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		power-domains = <&pd_lsio_gpio3>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio4: gpio@5d0c0000 {
		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x5d0c0000 0x0 0x10000>;
		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		power-domains = <&pd_lsio_gpio4>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio5: gpio@5d0d0000 {
		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x5d0d0000 0x0 0x10000>;
		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		power-domains = <&pd_lsio_gpio5>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio6: gpio@5d0e0000 {
		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x5d0e0000 0x0 0x10000>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		power-domains = <&pd_lsio_gpio6>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio7: gpio@5d0f0000 {
		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x5d0f0000 0x0 0x10000>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		power-domains = <&pd_lsio_gpio7>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	lpuart0: serial@5a060000 {
		compatible = "fsl,imx8qm-lpuart";
		reg = <0x0 0x5a060000 0x0 0x1000>;
		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8QXP_UART0_CLK>,
			 <&clk IMX8QXP_UART0_IPG_CLK>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
		assigned-clock-rates = <80000000>;
		power-domains = <&pd_dma_lpuart0>;
		status = "disabled";
	};

	lpuart1: serial@5a070000 {
		compatible = "fsl,imx8qm-lpuart";
		reg = <0x0 0x5a070000 0x0 0x1000>;
		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8QXP_UART1_CLK>,
			 <&clk IMX8QXP_UART1_IPG_CLK>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
		assigned-clock-rates = <80000000>;
		power-domains = <&pd_dma_lpuart1>;
		status = "disabled";
	};

	lpuart2: serial@5a080000 {
		compatible = "fsl,imx8qm-lpuart";
		reg = <0x0 0x5a080000 0x0 0x1000>;
		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8QXP_UART2_CLK>,
			 <&clk IMX8QXP_UART2_IPG_CLK>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
		assigned-clock-rates = <80000000>;
		power-domains = <&pd_dma_lpuart2>;
		status = "disabled";
	};

	lpuart3: serial@5a090000 {
		compatible = "fsl,imx8qm-lpuart";
		reg = <0x0 0x5a090000 0x0 0x1000>;
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8QXP_UART3_CLK>,
			 <&clk IMX8QXP_UART3_IPG_CLK>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
		assigned-clock-rates = <80000000>;
		power-domains = <&pd_dma_lpuart3>;
		status = "disabled";
	};

	usdhc1: usdhc@5b010000 {
		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x0 0x5b010000 0x0 0x10000>;
		clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
			<&clk IMX8QXP_SDHC0_CLK>,
			<&clk IMX8QXP_CLK_DUMMY>;
		clock-names = "ipg", "per", "ahb";
		assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
		assigned-clock-rates = <0>, <400000000>;
		power-domains = <&pd_conn_sdch0>;
		fsl,tuning-start-tap = <20>;
		fsl,tuning-step= <2>;
		status = "disabled";
	};

	usdhc2: usdhc@5b020000 {
		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x0 0x5b020000 0x0 0x10000>;
		clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
			<&clk IMX8QXP_SDHC1_CLK>,
			<&clk IMX8QXP_CLK_DUMMY>;
		clock-names = "ipg", "per", "ahb";
		assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
		assigned-clock-rates = <0>, <200000000>;
		power-domains = <&pd_conn_sdch1>;
		fsl,tuning-start-tap = <20>;
		fsl,tuning-step= <2>;
		status = "disabled";
	};

	usdhc3: usdhc@5b030000 {
		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x0 0x5b030000 0x0 0x10000>;
		clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
			<&clk IMX8QXP_SDHC2_CLK>,
			<&clk IMX8QXP_CLK_DUMMY>;
		clock-names = "ipg", "per", "ahb";
		assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
		assigned-clock-rates = <0>, <200000000>;
		power-domains = <&pd_conn_sdch2>;
		status = "disabled";
	};

	fec1: ethernet@5b040000 {
		compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
		reg = <0x0 0x5b040000 0x0 0x10000>;
		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>,
			<&clk IMX8QXP_ENET0_RGMII_TX_CLK>, <&clk IMX8QXP_ENET0_PTP_CLK>;
		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
		assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>;
		assigned-clock-rates = <125000000>, <125000000>;
		fsl,num-tx-queues=<3>;
		fsl,num-rx-queues=<3>;
		power-domains = <&pd_conn_enet0>;
		status = "disabled";
	};

	fec2: ethernet@5b050000 {
		compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
		reg = <0x0 0x5b050000 0x0 0x10000>;
		interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>,
			<&clk IMX8QXP_ENET1_RGMII_TX_CLK>, <&clk IMX8QXP_ENET1_PTP_CLK>;
		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
		assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>;
		assigned-clock-rates = <125000000>, <125000000>;
		fsl,num-tx-queues=<3>;
		fsl,num-rx-queues=<3>;
		power-domains = <&pd_conn_enet1>;
		status = "disabled";
	};

	tsens: thermal-sensor {
		compatible = "nxp,imx8qxp-sc-tsens";
		/* number of the temp sensor on the chip */
		tsens-num = <2>;
		#thermal-sensor-cells = <1>;
	};

	thermal_zones: thermal-zones {
		/* cpu thermal */
		cpu-thermal0 {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			/*the slope and offset of the temp sensor */
			thermal-sensors = <&tsens 0>;
			trips {
				cpu_alert0: trip0 {
					temperature = <107000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: trip1 {
					temperature = <127000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		drc-thermal0 {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tsens 1>;
			status = "disabled";
			trips {
				drc_alert0: trip0 {
					temperature = <107000>;
					hysteresis = <2000>;
					type = "passive";
				};
				drc_crit0: trip1 {
					temperature = <127000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	crypto: caam@0x31400000 {
		compatible = "fsl,sec-v4.0";
		reg = <0 0x31400000 0 0x400000>;
		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0x31400000 0x400000>;
		fsl,first-jr-index = <2>;
		fsl,sec-era = <9>;

		sec_jr1: jr1@0x20000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x20000 0x1000>;
			interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&pd_caam_jr1>;
			status = "disabled";
		};

		sec_jr2: jr2@30000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x30000 0x1000>;
			interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&pd_caam_jr2>;
			status = "okay";
		};

		sec_jr3: jr3@40000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x40000 0x1000>;
			interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&pd_caam_jr3>;
			status = "okay";
		};
	};
};

&A35_0 {
	clocks = <&clk IMX8QXP_A35_DIV>;
};

/delete-node/ &A35_2;
/delete-node/ &A35_3;
Commit	Line	Data
f180f4a4 PF	1	// SPDX-License-Identifier: GPL-2.0+
f180f4a4 PF	2	/*
0b9c4445	3	* Copyright 2018, 2021 NXP
f180f4a4 PF	4	*/
	5
	6	#include <dt-bindings/interrupt-controller/arm-gic.h>
	7	#include "fsl-imx8-ca35.dtsi"
	8	#include <dt-bindings/soc/imx_rsrc.h>
	9	#include <dt-bindings/soc/imx8_pd.h>
	10	#include <dt-bindings/clock/imx8qxp-clock.h>
	11	#include <dt-bindings/input/input.h>
	12	#include <dt-bindings/pinctrl/pads-imx8qxp.h>
	13	#include <dt-bindings/gpio/gpio.h>
d70c0fce	14	#include <dt-bindings/thermal/thermal.h>
f180f4a4 PF	15
	16	/ {
	17	model = "Freescale i.MX8DX";
	18	compatible = "fsl,imx8dx", "fsl,imx8qxp";
	19	interrupt-parent = <&gic>;
	20	#address-cells = <2>;
	21	#size-cells = <2>;
	22
	23	aliases {
	24	ethernet0 = &fec1;
	25	ethernet1 = &fec2;
	26	serial0 = &lpuart0;
	27	mmc0 = &usdhc1;
	28	mmc1 = &usdhc2;
	29	mmc2 = &usdhc3;
	30	i2c0 = &i2c0;
	31	i2c1 = &i2c1;
	32	i2c2 = &i2c2;
	33	i2c3 = &i2c3;
4e364251 AG	34	gpio0 = &gpio0;
	35	gpio1 = &gpio1;
	36	gpio2 = &gpio2;
	37	gpio3 = &gpio3;
	38	gpio4 = &gpio4;
	39	gpio5 = &gpio5;
	40	gpio6 = &gpio6;
	41	gpio7 = &gpio7;
f180f4a4 PF	42	};
	43
	44	memory@80000000 {
	45	device_type = "memory";
	46	reg = <0x00000000 0x80000000 0 0x40000000>;
	47	/* DRAM space - 1, size : 1 GB DRAM */
	48	};
	49
	50	reserved-memory {
	51	#address-cells = <2>;
	52	#size-cells = <2>;
	53	ranges;
	54
	55	/*
	56	* reserved-memory layout
	57	* 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
	58	* Shouldn't be used at A core and Linux side.
	59	*
	60	*/
	61	decoder_boot: decoder_boot@0x84000000 {
	62	no-map;
	63	reg = <0 0x84000000 0 0x2000000>;
	64	};
	65	encoder_boot: encoder_boot@0x86000000 {
	66	no-map;
	67	reg = <0 0x86000000 0 0x2000000>;
	68	};
	69	rpmsg_reserved: rpmsg@0x90000000 {
	70	no-map;
	71	reg = <0 0x90000000 0 0x400000>;
	72	};
	73	decoder_rpc: decoder_rpc@0x90400000 {
	74	no-map;
	75	reg = <0 0x90400000 0 0x1000000>;
	76	};
	77	encoder_rpc: encoder_rpc@0x91400000 {
	78	no-map;
	79	reg = <0 0x91400000 0 0x1000000>;
	80	};
	81	dsp_reserved: dsp@0x92400000 {
	82	no-map;
	83	reg = <0 0x92400000 0 0x2000000>;
	84	};
	85	decoder_str: str@0x94400000 {
	86	no-map;
	87	reg = <0 0x94400000 0 0x1800000>;
	88	};
	89	/* global autoconfigured region for contiguous allocations */
	90	linux,cma {
	91	compatible = "shared-dma-pool";
	92	reusable;
	93	size = <0 0x28000000>;
	94	alloc-ranges = <0 0x96000000 0 0x28000000>;
	95	linux,cma-default;
	96	};
	97	};
	98
	99	gic: interrupt-controller@51a00000 {
	100	compatible = "arm,gic-v3";
	101	reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
	102	<0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
	103	#interrupt-cells = <3>;
	104	interrupt-controller;
	105	interrupts = <GIC_PPI 9
106	(GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_HIGH)>;
107	interrupt-parent = <&gic>;
108	};
109
110	mu: mu@5d1c0000 {
111	compatible = "fsl,imx8-mu";
112	reg = <0x0 0x5d1c0000 0x0 0x10000>;
113	interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
114	interrupt-parent = <&gic>;
115	status = "okay";
116
117	clk: clk {
118	compatible = "fsl,imx8qxp-clk";
119	#clock-cells = <1>;
120	};
121
122	iomuxc: iomuxc {
123	compatible = "fsl,imx8qxp-iomuxc";
124	};
125	};
126
127	imx8qx-pm {
128	compatible = "simple-bus";
129	#address-cells = <1>;
130	#size-cells = <0>;
131
132	pd_lsio: PD_LSIO {
133	compatible = "nxp,imx8-pd";
6fcb2ee7	134	reg = <SC_R_NONE>;
f180f4a4 PF	135	#power-domain-cells = <0>;
	136	#address-cells = <1>;
	137	#size-cells = <0>;
	138
	139	pd_lsio_gpio0: PD_LSIO_GPIO_0 {
	140	reg = <SC_R_GPIO_0>;
	141	#power-domain-cells = <0>;
	142	power-domains = <&pd_lsio>;
	143	};
	144	pd_lsio_gpio1: PD_LSIO_GPIO_1 {
	145	reg = <SC_R_GPIO_1>;
	146	#power-domain-cells = <0>;
	147	power-domains = <&pd_lsio>;
	148	};
	149	pd_lsio_gpio2: PD_LSIO_GPIO_2 {
	150	reg = <SC_R_GPIO_2>;
	151	#power-domain-cells = <0>;
	152	power-domains = <&pd_lsio>;
	153	};
	154	pd_lsio_gpio3: PD_LSIO_GPIO_3 {
	155	reg = <SC_R_GPIO_3>;
	156	#power-domain-cells = <0>;
	157	power-domains = <&pd_lsio>;
	158	};
	159	pd_lsio_gpio4: PD_LSIO_GPIO_4 {
	160	reg = <SC_R_GPIO_4>;
	161	#power-domain-cells = <0>;
	162	power-domains = <&pd_lsio>;
	163	};
	164	pd_lsio_gpio5: PD_LSIO_GPIO_5{
	165	reg = <SC_R_GPIO_5>;
	166	#power-domain-cells = <0>;
	167	power-domains = <&pd_lsio>;
	168	};
	169	pd_lsio_gpio6: PD_LSIO_GPIO_6 {
	170	reg = <SC_R_GPIO_6>;
	171	#power-domain-cells = <0>;
	172	power-domains = <&pd_lsio>;
	173	};
	174	pd_lsio_gpio7: PD_LSIO_GPIO_7 {
	175	reg = <SC_R_GPIO_7>;
	176	#power-domain-cells = <0>;
	177	power-domains = <&pd_lsio>;
	178	};
	179	};
	180
	181	pd_conn: PD_CONN {
	182	compatible = "nxp,imx8-pd";
6fcb2ee7	183	reg = <SC_R_NONE>;
f180f4a4 PF	184	#power-domain-cells = <0>;
	185	#address-cells = <1>;
	186	#size-cells = <0>;
	187
	188	pd_conn_sdch0: PD_CONN_SDHC_0 {
	189	reg = <SC_R_SDHC_0>;
	190	#power-domain-cells = <0>;
	191	power-domains = <&pd_conn>;
	192	};
	193	pd_conn_sdch1: PD_CONN_SDHC_1 {
	194	reg = <SC_R_SDHC_1>;
	195	#power-domain-cells = <0>;
	196	power-domains = <&pd_conn>;
	197	};
	198	pd_conn_sdch2: PD_CONN_SDHC_2 {
	199	reg = <SC_R_SDHC_2>;
	200	#power-domain-cells = <0>;
	201	power-domains = <&pd_conn>;
	202	};
	203	pd_conn_enet0: PD_CONN_ENET_0 {
	204	reg = <SC_R_ENET_0>;
	205	#power-domain-cells = <0>;
	206	power-domains = <&pd_conn>;
	207	};
	208	pd_conn_enet1: PD_CONN_ENET_1 {
	209	reg = <SC_R_ENET_1>;
	210	#power-domain-cells = <0>;
	211	power-domains = <&pd_conn>;
	212	};
	213	};
	214
	215	pd_dma: PD_DMA {
	216	compatible = "nxp,imx8-pd";
6fcb2ee7	217	reg = <SC_R_NONE>;
f180f4a4 PF	218	#power-domain-cells = <0>;
	219	#address-cells = <1>;
	220	#size-cells = <0>;
	221
	222	pd_dma_lpi2c0: PD_DMA_I2C_0 {
	223	reg = <SC_R_I2C_0>;
	224	#power-domain-cells = <0>;
	225	power-domains = <&pd_dma>;
	226	};
	227	pd_dma_lpi2c1: PD_DMA_I2C_1 {
	228	reg = <SC_R_I2C_1>;
	229	#power-domain-cells = <0>;
	230	power-domains = <&pd_dma>;
	231	};
	232	pd_dma_lpi2c2:PD_DMA_I2C_2 {
	233	reg = <SC_R_I2C_2>;
	234	#power-domain-cells = <0>;
	235	power-domains = <&pd_dma>;
	236	};
	237	pd_dma_lpi2c3: PD_DMA_I2C_3 {
	238	reg = <SC_R_I2C_3>;
	239	#power-domain-cells = <0>;
	240	power-domains = <&pd_dma>;
	241	};
	242	pd_dma_lpuart0: PD_DMA_UART0 {
	243	reg = <SC_R_UART_0>;
	244	#power-domain-cells = <0>;
	245	power-domains = <&pd_dma>;
	246	wakeup-irq = <225>;
	247	};
270f1fb7 MZ	248	pd_dma_lpuart1: PD_DMA_UART1 {
	249	reg = <SC_R_UART_1>;
	250	#power-domain-cells = <0>;
	251	power-domains = <&pd_dma>;
	252	};
	253	pd_dma_lpuart2: PD_DMA_UART2 {
	254	reg = <SC_R_UART_2>;
	255	#power-domain-cells = <0>;
	256	power-domains = <&pd_dma>;
	257	};
	258	pd_dma_lpuart3: PD_DMA_UART3 {
	259	reg = <SC_R_UART_3>;
	260	#power-domain-cells = <0>;
	261	power-domains = <&pd_dma>;
	262	};
f180f4a4	263	};
0b9c4445 GJ	264
	265	pd_caam: PD_CAAM {
	266	compatible = "nxp,imx8-pd";
	267	reg = <SC_R_NONE>;
	268	#power-domain-cells = <0>;
	269	#address-cells = <1>;
	270	#size-cells = <0>;
	271
	272	pd_caam_jr1: PD_CAAM_JR1 {
	273	reg = <SC_R_CAAM_JR1>;
	274	#power-domain-cells = <0>;
	275	power-domains = <&pd_caam>;
	276	};
	277	pd_caam_jr2: PD_CAAM_JR2 {
	278	reg = <SC_R_CAAM_JR2>;
	279	#power-domain-cells = <0>;
	280	power-domains = <&pd_caam>;
	281	};
	282	pd_caam_jr3: PD_CAAM_JR3 {
	283	reg = <SC_R_CAAM_JR3>;
	284	#power-domain-cells = <0>;
	285	power-domains = <&pd_caam>;
	286	};
	287	};
f180f4a4 PF	288	};
	289
	290	i2c0: i2c@5a800000 {
	291	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
	292	reg = <0x0 0x5a800000 0x0 0x4000>;
	293	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
	294	interrupt-parent = <&gic>;
85d89b93 AG	295	clocks = <&clk IMX8QXP_I2C0_CLK>,
	296	<&clk IMX8QXP_I2C0_IPG_CLK>;
	297	clock-names = "per", "ipg";
f180f4a4 PF	298	assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
	299	assigned-clock-rates = <24000000>;
	300	power-domains = <&pd_dma_lpi2c0>;
	301	#address-cells = <1>;
	302	#size-cells = <0>;
	303	status = "disabled";
	304	};
	305
	306	i2c1: i2c@5a810000 {
	307	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
	308	reg = <0x0 0x5a810000 0x0 0x4000>;
	309	interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	310	interrupt-parent = <&gic>;
	311	clocks = <&clk IMX8QXP_I2C1_CLK>,
	312	<&clk IMX8QXP_I2C1_IPG_CLK>;
	313	clock-names = "per", "ipg";
	314	assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
	315	assigned-clock-rates = <24000000>;
	316	power-domains = <&pd_dma_lpi2c1>;
	317	#address-cells = <1>;
	318	#size-cells = <0>;
	319	status = "disabled";
	320	};
	321
	322	i2c2: i2c@5a820000 {
	323	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
	324	reg = <0x0 0x5a820000 0x0 0x4000>;
	325	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
	326	interrupt-parent = <&gic>;
85d89b93 AG	327	clocks = <&clk IMX8QXP_I2C2_CLK>,
	328	<&clk IMX8QXP_I2C2_IPG_CLK>;
	329	clock-names = "per", "ipg";
f180f4a4 PF	330	assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
	331	assigned-clock-rates = <24000000>;
	332	power-domains = <&pd_dma_lpi2c2>;
	333	#address-cells = <1>;
	334	#size-cells = <0>;
	335	status = "disabled";
	336	};
	337
	338	i2c3: i2c@5a830000 {
	339	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
	340	reg = <0x0 0x5a830000 0x0 0x4000>;
	341	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
	342	interrupt-parent = <&gic>;
	343	clocks = <&clk IMX8QXP_I2C3_CLK>,
	344	<&clk IMX8QXP_I2C3_IPG_CLK>;
	345	clock-names = "per", "ipg";
	346	assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
	347	assigned-clock-rates = <24000000>;
	348	power-domains = <&pd_dma_lpi2c3>;
	349	#address-cells = <1>;
	350	#size-cells = <0>;
	351	status = "disabled";
	352	};
	353
	354	gpio0: gpio@5d080000 {
	355	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
	356	reg = <0x0 0x5d080000 0x0 0x10000>;
	357	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	358	gpio-controller;
	359	#gpio-cells = <2>;
	360	power-domains = <&pd_lsio_gpio0>;
	361	interrupt-controller;
	362	#interrupt-cells = <2>;
	363	};
	364
	365	gpio1: gpio@5d090000 {
	366	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
	367	reg = <0x0 0x5d090000 0x0 0x10000>;
	368	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
	369	gpio-controller;
	370	#gpio-cells = <2>;
	371	power-domains = <&pd_lsio_gpio1>;
	372	interrupt-controller;
	373	#interrupt-cells = <2>;
	374	};
	375
	376	gpio2: gpio@5d0a0000 {
	377	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
	378	reg = <0x0 0x5d0a0000 0x0 0x10000>;
	379	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	380	gpio-controller;
	381	#gpio-cells = <2>;
	382	power-domains = <&pd_lsio_gpio2>;
	383	interrupt-controller;
	384	#interrupt-cells = <2>;
	385	};
	386
	387	gpio3: gpio@5d0b0000 {
	388	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
	389	reg = <0x0 0x5d0b0000 0x0 0x10000>;
	390	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
	391	gpio-controller;
	392	#gpio-cells = <2>;
	393	power-domains = <&pd_lsio_gpio3>;
394	interrupt-controller;
395	#interrupt-cells = <2>;
396	};
397
398	gpio4: gpio@5d0c0000 {
399	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
400	reg = <0x0 0x5d0c0000 0x0 0x10000>;
401	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
402	gpio-controller;
403	#gpio-cells = <2>;
404	power-domains = <&pd_lsio_gpio4>;
405	interrupt-controller;
406	#interrupt-cells = <2>;
407	};
408
409	gpio5: gpio@5d0d0000 {
410	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
411	reg = <0x0 0x5d0d0000 0x0 0x10000>;
412	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
413	gpio-controller;
414	#gpio-cells = <2>;
415	power-domains = <&pd_lsio_gpio5>;
416	interrupt-controller;
417	#interrupt-cells = <2>;
418	};
419
420	gpio6: gpio@5d0e0000 {
421	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
422	reg = <0x0 0x5d0e0000 0x0 0x10000>;
423	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
424	gpio-controller;
425	#gpio-cells = <2>;
426	power-domains = <&pd_lsio_gpio6>;
427	interrupt-controller;
428	#interrupt-cells = <2>;
429	};
430
431	gpio7: gpio@5d0f0000 {
432	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
433	reg = <0x0 0x5d0f0000 0x0 0x10000>;
434	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
435	gpio-controller;
436	#gpio-cells = <2>;
437	power-domains = <&pd_lsio_gpio7>;
438	interrupt-controller;
439	#interrupt-cells = <2>;
440	};
441
442	lpuart0: serial@5a060000 {
443	compatible = "fsl,imx8qm-lpuart";
444	reg = <0x0 0x5a060000 0x0 0x1000>;
445	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
446	clocks = <&clk IMX8QXP_UART0_CLK>,
447	<&clk IMX8QXP_UART0_IPG_CLK>;
448	clock-names = "per", "ipg";
449	assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
450	assigned-clock-rates = <80000000>;
451	power-domains = <&pd_dma_lpuart0>;
452	status = "disabled";
453	};
454
270f1fb7 MZ	455	lpuart1: serial@5a070000 {
	456	compatible = "fsl,imx8qm-lpuart";
	457	reg = <0x0 0x5a070000 0x0 0x1000>;
	458	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
	459	clocks = <&clk IMX8QXP_UART1_CLK>,
	460	<&clk IMX8QXP_UART1_IPG_CLK>;
	461	clock-names = "per", "ipg";
	462	assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
	463	assigned-clock-rates = <80000000>;
	464	power-domains = <&pd_dma_lpuart1>;
	465	status = "disabled";
	466	};
	467
	468	lpuart2: serial@5a080000 {
	469	compatible = "fsl,imx8qm-lpuart";
	470	reg = <0x0 0x5a080000 0x0 0x1000>;
	471	interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
	472	clocks = <&clk IMX8QXP_UART2_CLK>,
	473	<&clk IMX8QXP_UART2_IPG_CLK>;
	474	clock-names = "per", "ipg";
	475	assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
	476	assigned-clock-rates = <80000000>;
	477	power-domains = <&pd_dma_lpuart2>;
	478	status = "disabled";
	479	};
	480
	481	lpuart3: serial@5a090000 {
	482	compatible = "fsl,imx8qm-lpuart";
	483	reg = <0x0 0x5a090000 0x0 0x1000>;
	484	interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
	485	clocks = <&clk IMX8QXP_UART3_CLK>,
	486	<&clk IMX8QXP_UART3_IPG_CLK>;
	487	clock-names = "per", "ipg";
	488	assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
	489	assigned-clock-rates = <80000000>;
	490	power-domains = <&pd_dma_lpuart3>;
	491	status = "disabled";
	492	};
	493
f180f4a4 PF	494	usdhc1: usdhc@5b010000 {
	495	compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
	496	interrupt-parent = <&gic>;
	497	interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
	498	reg = <0x0 0x5b010000 0x0 0x10000>;
	499	clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
	500	<&clk IMX8QXP_SDHC0_CLK>,
	501	<&clk IMX8QXP_CLK_DUMMY>;
	502	clock-names = "ipg", "per", "ahb";
	503	assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
	504	assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
	505	assigned-clock-rates = <0>, <400000000>;
	506	power-domains = <&pd_conn_sdch0>;
	507	fsl,tuning-start-tap = <20>;
	508	fsl,tuning-step= <2>;
	509	status = "disabled";
	510	};
	511
	512	usdhc2: usdhc@5b020000 {
	513	compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
	514	interrupt-parent = <&gic>;
	515	interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
	516	reg = <0x0 0x5b020000 0x0 0x10000>;
	517	clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
	518	<&clk IMX8QXP_SDHC1_CLK>,
	519	<&clk IMX8QXP_CLK_DUMMY>;
	520	clock-names = "ipg", "per", "ahb";
	521	assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
	522	assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
	523	assigned-clock-rates = <0>, <200000000>;
	524	power-domains = <&pd_conn_sdch1>;
	525	fsl,tuning-start-tap = <20>;
	526	fsl,tuning-step= <2>;
	527	status = "disabled";
	528	};
	529
	530	usdhc3: usdhc@5b030000 {
	531	compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
	532	interrupt-parent = <&gic>;
	533	interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
	534	reg = <0x0 0x5b030000 0x0 0x10000>;
	535	clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
	536	<&clk IMX8QXP_SDHC2_CLK>,
	537	<&clk IMX8QXP_CLK_DUMMY>;
	538	clock-names = "ipg", "per", "ahb";
	539	assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
	540	assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
	541	assigned-clock-rates = <0>, <200000000>;
	542	power-domains = <&pd_conn_sdch2>;
	543	status = "disabled";
	544	};
	545
	546	fec1: ethernet@5b040000 {
	547	compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
	548	reg = <0x0 0x5b040000 0x0 0x10000>;
	549	interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
	550	<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	551	<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
	552	<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
	553	clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>,
	554	<&clk IMX8QXP_ENET0_RGMII_TX_CLK>, <&clk IMX8QXP_ENET0_PTP_CLK>;
	555	clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
	556	assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>;
	557	assigned-clock-rates = <125000000>, <125000000>;
558	fsl,num-tx-queues=<3>;
559	fsl,num-rx-queues=<3>;
560	power-domains = <&pd_conn_enet0>;
561	status = "disabled";
562	};
563
564	fec2: ethernet@5b050000 {
565	compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
566	reg = <0x0 0x5b050000 0x0 0x10000>;
567	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
568	<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
569	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
570	<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
571	clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>,
572	<&clk IMX8QXP_ENET1_RGMII_TX_CLK>, <&clk IMX8QXP_ENET1_PTP_CLK>;
573	clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
574	assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>;
575	assigned-clock-rates = <125000000>, <125000000>;
576	fsl,num-tx-queues=<3>;
577	fsl,num-rx-queues=<3>;
578	power-domains = <&pd_conn_enet1>;
579	status = "disabled";
580	};
d70c0fce PF	581
	582	tsens: thermal-sensor {
	583	compatible = "nxp,imx8qxp-sc-tsens";
	584	/* number of the temp sensor on the chip */
	585	tsens-num = <2>;
	586	#thermal-sensor-cells = <1>;
	587	};
	588
	589	thermal_zones: thermal-zones {
	590	/* cpu thermal */
	591	cpu-thermal0 {
	592	polling-delay-passive = <250>;
	593	polling-delay = <2000>;
	594	/the slope and offset of the temp sensor /
	595	thermal-sensors = <&tsens 0>;
	596	trips {
	597	cpu_alert0: trip0 {
	598	temperature = <107000>;
	599	hysteresis = <2000>;
	600	type = "passive";
	601	};
	602	cpu_crit0: trip1 {
	603	temperature = <127000>;
	604	hysteresis = <2000>;
	605	type = "critical";
	606	};
	607	};
	608	cooling-maps {
	609	map0 {
	610	trip = <&cpu_alert0>;
	611	cooling-device =
	612	<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	613	};
	614	};
	615	};
	616
	617	drc-thermal0 {
	618	polling-delay-passive = <250>;
	619	polling-delay = <2000>;
	620	thermal-sensors = <&tsens 1>;
	621	status = "disabled";
	622	trips {
	623	drc_alert0: trip0 {
	624	temperature = <107000>;
	625	hysteresis = <2000>;
	626	type = "passive";
	627	};
	628	drc_crit0: trip1 {
	629	temperature = <127000>;
	630	hysteresis = <2000>;
	631	type = "critical";
	632	};
	633	};
	634	};
	635	};
0b9c4445 GJ	636
	637	crypto: caam@0x31400000 {
	638	compatible = "fsl,sec-v4.0";
	639	reg = <0 0x31400000 0 0x400000>;
	640	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	641	#address-cells = <1>;
	642	#size-cells = <1>;
	643	ranges = <0 0 0x31400000 0x400000>;
	644	fsl,first-jr-index = <2>;
	645	fsl,sec-era = <9>;
	646
	647	sec_jr1: jr1@0x20000 {
	648	compatible = "fsl,sec-v4.0-job-ring";
	649	reg = <0x20000 0x1000>;
	650	interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
	651	power-domains = <&pd_caam_jr1>;
	652	status = "disabled";
	653	};
	654
	655	sec_jr2: jr2@30000 {
	656	compatible = "fsl,sec-v4.0-job-ring";
	657	reg = <0x30000 0x1000>;
	658	interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
	659	power-domains = <&pd_caam_jr2>;
	660	status = "okay";
	661	};
	662
	663	sec_jr3: jr3@40000 {
	664	compatible = "fsl,sec-v4.0-job-ring";
	665	reg = <0x40000 0x1000>;
	666	interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
	667	power-domains = <&pd_caam_jr3>;
	668	status = "okay";
	669	};
	670	};
f180f4a4 PF	671	};
	672
	673	&A35_0 {
	674	clocks = <&clk IMX8QXP_A35_DIV>;
	675	};
	676
	677	/delete-node/ &A35_2;
	678	/delete-node/ &A35_3;