[J-u-boot.git] / include / configs / ixdp425.h

/*
 * (C) Copyright 2003
 * Kyle Harris, Nexus Technologies, Inc. [email protected]
 *
 * Configuation settings for the IXDP425 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_IXP425           1       /* This is an IXP425 CPU    */
#define CONFIG_IXDP425          1       /* on an IXDP425 Board      */

#define CONFIG_DISPLAY_CPUINFO	1	/* display cpu info (and speed)	*/
#define CONFIG_DISPLAY_BOARDINFO 1	/* display board info		*/

/***************************************************************
 * U-boot generic defines start here.
 ***************************************************************/

#undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN      (CONFIG_ENV_SIZE + 128*1024)

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE         115200


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ELF
#define CONFIG_CMD_PCI


#define CONFIG_PCI
#define CONFIG_IXP_PCI
#define CONFIG_NET_MULTI
#define CONFIG_EEPRO100

#define CONFIG_BOOTDELAY        3
/*#define CONFIG_ETHADDR          08:00:3e:26:0a:5b*/
#define CONFIG_NETMASK          255.255.255.0
#define CONFIG_IPADDR           192.168.0.21
#define CONFIG_SERVERIP         192.168.0.148
#define CONFIG_BOOTCOMMAND      "bootm 50040000"
#define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
#define CONFIG_CMDLINE_TAG

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP                            /* undef to save memory         */
#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt       */
#define CONFIG_SYS_CBSIZE              256             /* Console I/O Buffer Size      */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS             16              /* max number of command args   */
#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE      /* Boot Argument Buffer Size    */

#define CONFIG_SYS_MEMTEST_START       0x00400000      /* memtest works on     */
#define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */

#define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */

#define CONFIG_SYS_HZ                  3333333         /* spec says 66.666 MHz, but it appears to be 33 */
						/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }

/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
#endif

/***************************************************************
 * Platform/Board specific defines start here.
 ***************************************************************/

/*
 * Hardware drivers
 */


/*
 * select serial console configuration
 */
#define CONFIG_IXP_SERIAL
#define CONFIG_SYS_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS    1          /* we have 2 banks of DRAM */
#define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE       0x01000000 /* 16 MB */

#define PHYS_FLASH_1            0x50000000 /* Flash Bank #1 */
#define PHYS_FLASH_SIZE         0x00800000 /* 8 MB */
#define PHYS_FLASH_BANK_SIZE    0x00800000 /* 8 MB Banks */
#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */

#define CONFIG_SYS_DRAM_BASE           0x00000000
#define CONFIG_SYS_DRAM_SIZE           0x01000000

#define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/

/*
 * Expansion bus settings
 */
#define CONFIG_SYS_EXP_CS0				0xbcd23c42

/*
 * SDRAM settings
 */
#define CONFIG_SYS_SDR_CONFIG		0xd
#define CONFIG_SYS_SDR_MODE_CONFIG	0x1
#define CONFIG_SYS_SDRAM_REFRESH_CNT	0x81a

/*
 * GPIO settings
 */

/*
 * FLASH and environment organization
 */
/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks           */
#define CONFIG_SYS_MAX_FLASH_SECT      128	/* max number of sectors on one chip    */

#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
#define	CONFIG_ENV_IS_IN_FLASH	1

#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1 }

#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x20000)
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

#endif  /* __CONFIG_H */
Commit	Line	Data
2d5b561e WD	1	/*
	2	* (C) Copyright 2003
	3	* Kyle Harris, Nexus Technologies, Inc. [email protected]
	4	*
	5	* Configuation settings for the IXDP425 board.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	/*
	30	* High Level Configuration Options
	31	* (easy to change)
	32	*/
	33	#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
	34	#define CONFIG_IXDP425 1 /* on an IXDP425 Board */
	35
ba94a1bb WD	36	#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
	37	#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
	38
2d5b561e WD	39	/***************************************************************
	40	* U-boot generic defines start here.
	41	***************************************************************/
	42
2d5b561e WD	43	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	44
	45	/*
	46	* Size of malloc() pool
	47	*/
6d0f6bcf	48	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
2d5b561e WD	49
	50	/* allow to overwrite serial and ethaddr */
	51	#define CONFIG_ENV_OVERWRITE
	52
	53	#define CONFIG_BAUDRATE 115200
	54
1d2c6bc4	55
7f5c0157 JL	56	/*
	57	* BOOTP options
	58	*/
	59	#define CONFIG_BOOTP_BOOTFILESIZE
	60	#define CONFIG_BOOTP_BOOTPATH
	61	#define CONFIG_BOOTP_GATEWAY
	62	#define CONFIG_BOOTP_HOSTNAME
	63
	64
1d2c6bc4 JL	65	/*
	66	* Command line configuration.
	67	*/
	68	#include <config_cmd_default.h>
	69
	70	#define CONFIG_CMD_ELF
	71	#define CONFIG_CMD_PCI
	72
2d5b561e	73
a1191902	74	#define CONFIG_PCI
8cb79b5f	75	#define CONFIG_IXP_PCI
a1191902 WD	76	#define CONFIG_NET_MULTI
a1191902 WD	77	#define CONFIG_EEPRO100
2d5b561e WD	78
2d5b561e WD	79	#define CONFIG_BOOTDELAY 3
a1191902 WD	80	/#define CONFIG_ETHADDR 08:00:3e:26:0a:5b/
a1191902 WD	81	#define CONFIG_NETMASK 255.255.255.0
2d5b561e	82	#define CONFIG_IPADDR 192.168.0.21
a1191902	83	#define CONFIG_SERVERIP 192.168.0.148
2d5b561e WD	84	#define CONFIG_BOOTCOMMAND "bootm 50040000"
2d5b561e WD	85	#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
42d1f039	86	#define CONFIG_CMDLINE_TAG
2d5b561e	87
1d2c6bc4	88	#if defined(CONFIG_CMD_KGDB)
2d5b561e WD	89	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	90	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	91	#endif
	92
	93	/*
	94	* Miscellaneous configurable options
	95	*/
6d0f6bcf JCPV	96	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	97	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	98	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	99	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	100	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	101	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
2d5b561e	102
6d0f6bcf JCPV	103	#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
6d0f6bcf JCPV	104	#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
2d5b561e	105
6d0f6bcf	106	#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
2d5b561e	107
6d0f6bcf	108	#define CONFIG_SYS_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */
42d1f039	109	/* valid baudrates */
6d0f6bcf	110	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
2d5b561e WD	111
	112	/*
	113	* Stack sizes
	114	*
	115	* The stack sizes are set up in start.S using the settings below
	116	*/
	117	#define CONFIG_STACKSIZE (1281024) / regular stack */
	118	#ifdef CONFIG_USE_IRQ
	119	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	120	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	121	#endif
	122
	123	/***************************************************************
	124	* Platform/Board specific defines start here.
	125	***************************************************************/
	126
	127	/*
	128	* Hardware drivers
	129	*/
	130
	131
	132	/*
	133	* select serial console configuration
	134	*/
930590f3	135	#define CONFIG_IXP_SERIAL
6d0f6bcf	136	#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
2d5b561e WD	137
	138	/*
	139	* Physical Memory Map
	140	*/
	141	#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */
	142	#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
	143	#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
	144
	145	#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
	146	#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
	147	#define PHYS_FLASH_BANK_SIZE 0x00800000 /* 8 MB Banks */
	148	#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
	149
6d0f6bcf JCPV	150	#define CONFIG_SYS_DRAM_BASE 0x00000000
6d0f6bcf JCPV	151	#define CONFIG_SYS_DRAM_SIZE 0x01000000
2d5b561e	152
6d0f6bcf JCPV	153	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	154	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	155	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
2d5b561e WD	156
	157	/*
	158	* Expansion bus settings
	159	*/
6d0f6bcf	160	#define CONFIG_SYS_EXP_CS0 0xbcd23c42
2d5b561e WD	161
	162	/*
	163	* SDRAM settings
	164	*/
6d0f6bcf JCPV	165	#define CONFIG_SYS_SDR_CONFIG 0xd
	166	#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
	167	#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
2d5b561e WD	168
	169	/*
	170	* GPIO settings
	171	*/
	172
ba94a1bb WD	173	/*
	174	* FLASH and environment organization
	175	*/
2d5b561e WD	176	/*
	177	* FLASH and environment organization
	178	*/
6d0f6bcf JCPV	179	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	180	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
ba94a1bb	181
6d0f6bcf	182	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	183	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
5a1aceb0	184	#define CONFIG_ENV_IS_IN_FLASH 1
ba94a1bb	185
6d0f6bcf	186	#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
ba94a1bb	187
6d0f6bcf	188	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
ba94a1bb	189
6d0f6bcf JCPV	190	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	191	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
2d5b561e	192
6d0f6bcf	193	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
2d5b561e	194
0e8d1586 JCPV	195	#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
	196	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000)
	197	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
2d5b561e WD	198
2d5b561e WD	199	#endif /* __CONFIG_H */